1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright (C) 2020 HabanaLabs Ltd. 4 * All Rights Reserved. 5 */ 6 7 #ifndef __GAUDI2_ARC_COMMON_PACKETS_H__ 8 #define __GAUDI2_ARC_COMMON_PACKETS_H__ 9 10 enum { 11 CPU_ID_SCHED_ARC0 = 0, /* FARM_ARC0 */ 12 CPU_ID_SCHED_ARC1 = 1, /* FARM_ARC1 */ 13 CPU_ID_SCHED_ARC2 = 2, /* FARM_ARC2 */ 14 CPU_ID_SCHED_ARC3 = 3, /* FARM_ARC3 */ 15 /* Dcore1 MME Engine ARC instance used as scheduler */ 16 CPU_ID_SCHED_ARC4 = 4, /* DCORE1_MME0 */ 17 /* Dcore3 MME Engine ARC instance used as scheduler */ 18 CPU_ID_SCHED_ARC5 = 5, /* DCORE3_MME0 */ 19 20 CPU_ID_TPC_QMAN_ARC0 = 6, /* DCORE0_TPC0 */ 21 CPU_ID_TPC_QMAN_ARC1 = 7, /* DCORE0_TPC1 */ 22 CPU_ID_TPC_QMAN_ARC2 = 8, /* DCORE0_TPC2 */ 23 CPU_ID_TPC_QMAN_ARC3 = 9, /* DCORE0_TPC3 */ 24 CPU_ID_TPC_QMAN_ARC4 = 10, /* DCORE0_TPC4 */ 25 CPU_ID_TPC_QMAN_ARC5 = 11, /* DCORE0_TPC5 */ 26 CPU_ID_TPC_QMAN_ARC6 = 12, /* DCORE1_TPC0 */ 27 CPU_ID_TPC_QMAN_ARC7 = 13, /* DCORE1_TPC1 */ 28 CPU_ID_TPC_QMAN_ARC8 = 14, /* DCORE1_TPC2 */ 29 CPU_ID_TPC_QMAN_ARC9 = 15, /* DCORE1_TPC3 */ 30 CPU_ID_TPC_QMAN_ARC10 = 16, /* DCORE1_TPC4 */ 31 CPU_ID_TPC_QMAN_ARC11 = 17, /* DCORE1_TPC5 */ 32 CPU_ID_TPC_QMAN_ARC12 = 18, /* DCORE2_TPC0 */ 33 CPU_ID_TPC_QMAN_ARC13 = 19, /* DCORE2_TPC1 */ 34 CPU_ID_TPC_QMAN_ARC14 = 20, /* DCORE2_TPC2 */ 35 CPU_ID_TPC_QMAN_ARC15 = 21, /* DCORE2_TPC3 */ 36 CPU_ID_TPC_QMAN_ARC16 = 22, /* DCORE2_TPC4 */ 37 CPU_ID_TPC_QMAN_ARC17 = 23, /* DCORE2_TPC5 */ 38 CPU_ID_TPC_QMAN_ARC18 = 24, /* DCORE3_TPC0 */ 39 CPU_ID_TPC_QMAN_ARC19 = 25, /* DCORE3_TPC1 */ 40 CPU_ID_TPC_QMAN_ARC20 = 26, /* DCORE3_TPC2 */ 41 CPU_ID_TPC_QMAN_ARC21 = 27, /* DCORE3_TPC3 */ 42 CPU_ID_TPC_QMAN_ARC22 = 28, /* DCORE3_TPC4 */ 43 CPU_ID_TPC_QMAN_ARC23 = 29, /* DCORE3_TPC5 */ 44 CPU_ID_TPC_QMAN_ARC24 = 30, /* DCORE0_TPC6 - Never present */ 45 46 CPU_ID_MME_QMAN_ARC0 = 31, /* DCORE0_MME0 */ 47 CPU_ID_MME_QMAN_ARC1 = 32, /* DCORE2_MME0 */ 48 49 CPU_ID_EDMA_QMAN_ARC0 = 33, /* DCORE0_EDMA0 */ 50 CPU_ID_EDMA_QMAN_ARC1 = 34, /* DCORE0_EDMA1 */ 51 CPU_ID_EDMA_QMAN_ARC2 = 35, /* DCORE1_EDMA0 */ 52 CPU_ID_EDMA_QMAN_ARC3 = 36, /* DCORE1_EDMA1 */ 53 CPU_ID_EDMA_QMAN_ARC4 = 37, /* DCORE2_EDMA0 */ 54 CPU_ID_EDMA_QMAN_ARC5 = 38, /* DCORE2_EDMA1 */ 55 CPU_ID_EDMA_QMAN_ARC6 = 39, /* DCORE3_EDMA0 */ 56 CPU_ID_EDMA_QMAN_ARC7 = 40, /* DCORE3_EDMA1 */ 57 58 CPU_ID_PDMA_QMAN_ARC0 = 41, /* DCORE0_PDMA0 */ 59 CPU_ID_PDMA_QMAN_ARC1 = 42, /* DCORE0_PDMA1 */ 60 61 CPU_ID_ROT_QMAN_ARC0 = 43, /* ROT0 */ 62 CPU_ID_ROT_QMAN_ARC1 = 44, /* ROT1 */ 63 64 CPU_ID_NIC_QMAN_ARC0 = 45, /* NIC0_0 */ 65 CPU_ID_NIC_QMAN_ARC1 = 46, /* NIC0_1 */ 66 CPU_ID_NIC_QMAN_ARC2 = 47, /* NIC1_0 */ 67 CPU_ID_NIC_QMAN_ARC3 = 48, /* NIC1_1 */ 68 CPU_ID_NIC_QMAN_ARC4 = 49, /* NIC2_0 */ 69 CPU_ID_NIC_QMAN_ARC5 = 50, /* NIC2_1 */ 70 CPU_ID_NIC_QMAN_ARC6 = 51, /* NIC3_0 */ 71 CPU_ID_NIC_QMAN_ARC7 = 52, /* NIC3_1 */ 72 CPU_ID_NIC_QMAN_ARC8 = 53, /* NIC4_0 */ 73 CPU_ID_NIC_QMAN_ARC9 = 54, /* NIC4_1 */ 74 CPU_ID_NIC_QMAN_ARC10 = 55, /* NIC5_0 */ 75 CPU_ID_NIC_QMAN_ARC11 = 56, /* NIC5_1 */ 76 CPU_ID_NIC_QMAN_ARC12 = 57, /* NIC6_0 */ 77 CPU_ID_NIC_QMAN_ARC13 = 58, /* NIC6_1 */ 78 CPU_ID_NIC_QMAN_ARC14 = 59, /* NIC7_0 */ 79 CPU_ID_NIC_QMAN_ARC15 = 60, /* NIC7_1 */ 80 CPU_ID_NIC_QMAN_ARC16 = 61, /* NIC8_0 */ 81 CPU_ID_NIC_QMAN_ARC17 = 62, /* NIC8_1 */ 82 CPU_ID_NIC_QMAN_ARC18 = 63, /* NIC9_0 */ 83 CPU_ID_NIC_QMAN_ARC19 = 64, /* NIC9_1 */ 84 CPU_ID_NIC_QMAN_ARC20 = 65, /* NIC10_0 */ 85 CPU_ID_NIC_QMAN_ARC21 = 66, /* NIC10_1 */ 86 CPU_ID_NIC_QMAN_ARC22 = 67, /* NIC11_0 */ 87 CPU_ID_NIC_QMAN_ARC23 = 68, /* NIC11_1 */ 88 89 CPU_ID_MAX = 69, 90 CPU_ID_SCHED_MAX = 6, 91 92 CPU_ID_ALL = 0xFE, 93 CPU_ID_INVALID = 0xFF, 94 }; 95 96 enum arc_regions_t { 97 ARC_REGION0_UNSED = 0, 98 /* 99 * Extension registers 100 * None 101 */ 102 ARC_REGION1_SRAM = 1, 103 /* 104 * Extension registers 105 * AUX_SRAM_LSB_ADDR 106 * AUX_SRAM_MSB_ADDR 107 * ARC Address: 0x1000_0000 108 */ 109 ARC_REGION2_CFG = 2, 110 /* 111 * Extension registers 112 * AUX_CFG_LSB_ADDR 113 * AUX_CFG_MSB_ADDR 114 * ARC Address: 0x2000_0000 115 */ 116 ARC_REGION3_GENERAL = 3, 117 /* 118 * Extension registers 119 * AUX_GENERAL_PURPOSE_LSB_ADDR_0 120 * AUX_GENERAL_PURPOSE_MSB_ADDR_0 121 * ARC Address: 0x3000_0000 122 */ 123 ARC_REGION4_HBM0_FW = 4, 124 /* 125 * Extension registers 126 * AUX_HBM0_LSB_ADDR 127 * AUX_HBM0_MSB_ADDR 128 * AUX_HBM0_OFFSET 129 * ARC Address: 0x4000_0000 130 */ 131 ARC_REGION5_HBM1_GC_DATA = 5, 132 /* 133 * Extension registers 134 * AUX_HBM1_LSB_ADDR 135 * AUX_HBM1_MSB_ADDR 136 * AUX_HBM1_OFFSET 137 * ARC Address: 0x5000_0000 138 */ 139 ARC_REGION6_HBM2_GC_DATA = 6, 140 /* 141 * Extension registers 142 * AUX_HBM2_LSB_ADDR 143 * AUX_HBM2_MSB_ADDR 144 * AUX_HBM2_OFFSET 145 * ARC Address: 0x6000_0000 146 */ 147 ARC_REGION7_HBM3_GC_DATA = 7, 148 /* 149 * Extension registers 150 * AUX_HBM3_LSB_ADDR 151 * AUX_HBM3_MSB_ADDR 152 * AUX_HBM3_OFFSET 153 * ARC Address: 0x7000_0000 154 */ 155 ARC_REGION8_DCCM = 8, 156 /* 157 * Extension registers 158 * None 159 * ARC Address: 0x8000_0000 160 */ 161 ARC_REGION9_PCIE = 9, 162 /* 163 * Extension registers 164 * AUX_PCIE_LSB_ADDR 165 * AUX_PCIE_MSB_ADDR 166 * ARC Address: 0x9000_0000 167 */ 168 ARC_REGION10_GENERAL = 10, 169 /* 170 * Extension registers 171 * AUX_GENERAL_PURPOSE_LSB_ADDR_1 172 * AUX_GENERAL_PURPOSE_MSB_ADDR_1 173 * ARC Address: 0xA000_0000 174 */ 175 ARC_REGION11_GENERAL = 11, 176 /* 177 * Extension registers 178 * AUX_GENERAL_PURPOSE_LSB_ADDR_2 179 * AUX_GENERAL_PURPOSE_MSB_ADDR_2 180 * ARC Address: 0xB000_0000 181 */ 182 ARC_REGION12_GENERAL = 12, 183 /* 184 * Extension registers 185 * AUX_GENERAL_PURPOSE_LSB_ADDR_3 186 * AUX_GENERAL_PURPOSE_MSB_ADDR_3 187 * ARC Address: 0xC000_0000 188 */ 189 ARC_REGION13_GENERAL = 13, 190 /* 191 * Extension registers 192 * AUX_GENERAL_PURPOSE_LSB_ADDR_4 193 * AUX_GENERAL_PURPOSE_MSB_ADDR_4 194 * ARC Address: 0xD000_0000 195 */ 196 ARC_REGION14_GENERAL = 14, 197 /* 198 * Extension registers 199 * AUX_GENERAL_PURPOSE_LSB_ADDR_5 200 * AUX_GENERAL_PURPOSE_MSB_ADDR_5 201 * ARC Address: 0xE000_0000 202 */ 203 ARC_REGION15_LBU = 15 204 /* 205 * Extension registers 206 * None 207 * ARC Address: 0xF000_0000 208 */ 209 }; 210 211 #endif /* __GAUDI2_ARC_COMMON_PACKETS_H__ */ 212