1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2001 Navin Boppuri / Prashant Patel
4 * <nboppuri@trinetcommunication.com>,
5 * <pmpatel@trinetcommunication.com>
6 * Copyright (c) 2001 Gerd Mennchen <Gerd.Mennchen@icn.siemens.de>
7 * Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>.
8 */
9
10 /*
11 * MPC8xx CPM SPI interface.
12 *
13 * Parts of this code are probably not portable and/or specific to
14 * the board which I used for the tests. Please send fixes/complaints
15 * to wd@denx.de
16 *
17 */
18
19 #include <common.h>
20 #include <dm.h>
21 #include <mpc8xx.h>
22 #include <spi.h>
23
24 #include <asm/cpm_8xx.h>
25 #include <asm/io.h>
26
27 #define CPM_SPI_BASE_RX CPM_SPI_BASE
28 #define CPM_SPI_BASE_TX (CPM_SPI_BASE + sizeof(cbd_t))
29
30 #define MAX_BUFFER 0x104
31
mpc8xx_spi_probe(struct udevice * dev)32 static int mpc8xx_spi_probe(struct udevice *dev)
33 {
34 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
35 cpm8xx_t __iomem *cp = &immr->im_cpm;
36 spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI];
37 cbd_t __iomem *tbdf, *rbdf;
38
39 /* Disable relocation */
40 out_be16(&spi->spi_rpbase, 0);
41
42 /* 1 */
43 /* ------------------------------------------------
44 * Initialize Port B SPI pins -> page 34-8 MPC860UM
45 * (we are only in Master Mode !)
46 * ------------------------------------------------ */
47
48 /* --------------------------------------------
49 * GPIO or per. Function
50 * PBPAR[28] = 1 [0x00000008] -> PERI: (SPIMISO)
51 * PBPAR[29] = 1 [0x00000004] -> PERI: (SPIMOSI)
52 * PBPAR[30] = 1 [0x00000002] -> PERI: (SPICLK)
53 * PBPAR[31] = 0 [0x00000001] -> GPIO: (CS for PCUE/CCM-EEPROM)
54 * -------------------------------------------- */
55 clrsetbits_be32(&cp->cp_pbpar, 0x00000001, 0x0000000E); /* set bits */
56
57 /* ----------------------------------------------
58 * In/Out or per. Function 0/1
59 * PBDIR[28] = 1 [0x00000008] -> PERI1: SPIMISO
60 * PBDIR[29] = 1 [0x00000004] -> PERI1: SPIMOSI
61 * PBDIR[30] = 1 [0x00000002] -> PERI1: SPICLK
62 * PBDIR[31] = 1 [0x00000001] -> GPIO OUT: CS for PCUE/CCM-EEPROM
63 * ---------------------------------------------- */
64 setbits_be32(&cp->cp_pbdir, 0x0000000F);
65
66 /* ----------------------------------------------
67 * open drain or active output
68 * PBODR[28] = 1 [0x00000008] -> open drain: SPIMISO
69 * PBODR[29] = 0 [0x00000004] -> active output SPIMOSI
70 * PBODR[30] = 0 [0x00000002] -> active output: SPICLK
71 * PBODR[31] = 0 [0x00000001] -> active output GPIO OUT: CS for PCUE/CCM
72 * ---------------------------------------------- */
73
74 clrsetbits_be16(&cp->cp_pbodr, 0x00000007, 0x00000008);
75
76 /* Initialize the parameter ram.
77 * We need to make sure many things are initialized to zero
78 */
79 out_be32(&spi->spi_rstate, 0);
80 out_be32(&spi->spi_rdp, 0);
81 out_be16(&spi->spi_rbptr, 0);
82 out_be16(&spi->spi_rbc, 0);
83 out_be32(&spi->spi_rxtmp, 0);
84 out_be32(&spi->spi_tstate, 0);
85 out_be32(&spi->spi_tdp, 0);
86 out_be16(&spi->spi_tbptr, 0);
87 out_be16(&spi->spi_tbc, 0);
88 out_be32(&spi->spi_txtmp, 0);
89
90 /* 3 */
91 /* Set up the SPI parameters in the parameter ram */
92 out_be16(&spi->spi_rbase, CPM_SPI_BASE_RX);
93 out_be16(&spi->spi_tbase, CPM_SPI_BASE_TX);
94
95 /***********IMPORTANT******************/
96
97 /*
98 * Setting transmit and receive buffer descriptor pointers
99 * initially to rbase and tbase. Only the microcode patches
100 * documentation talks about initializing this pointer. This
101 * is missing from the sample I2C driver. If you dont
102 * initialize these pointers, the kernel hangs.
103 */
104 out_be16(&spi->spi_rbptr, CPM_SPI_BASE_RX);
105 out_be16(&spi->spi_tbptr, CPM_SPI_BASE_TX);
106
107 /* 4 */
108 /* Init SPI Tx + Rx Parameters */
109 while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG)
110 ;
111
112 out_be16(&cp->cp_cpcr, mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) |
113 CPM_CR_FLG);
114 while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG)
115 ;
116
117 /* 5 */
118 /* Set SDMA configuration register */
119 out_be32(&immr->im_siu_conf.sc_sdcr, 0x0001);
120
121 /* 6 */
122 /* Set to big endian. */
123 out_8(&spi->spi_tfcr, SMC_EB);
124 out_8(&spi->spi_rfcr, SMC_EB);
125
126 /* 7 */
127 /* Set maximum receive size. */
128 out_be16(&spi->spi_mrblr, MAX_BUFFER);
129
130 /* 8 + 9 */
131 /* tx and rx buffer descriptors */
132 tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
133 rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
134
135 clrbits_be16(&tbdf->cbd_sc, BD_SC_READY);
136 clrbits_be16(&rbdf->cbd_sc, BD_SC_EMPTY);
137
138 /* 10 + 11 */
139 out_8(&cp->cp_spim, 0); /* Mask all SPI events */
140 out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */
141
142 return 0;
143 }
144
mpc8xx_spi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)145 static int mpc8xx_spi_xfer(struct udevice *dev, unsigned int bitlen,
146 const void *dout, void *din, unsigned long flags)
147 {
148 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
149 cpm8xx_t __iomem *cp = &immr->im_cpm;
150 cbd_t __iomem *tbdf, *rbdf;
151 int tm;
152 size_t count = (bitlen + 7) / 8;
153
154 if (count > MAX_BUFFER)
155 return -EINVAL;
156
157 tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
158 rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
159
160 /* Set CS for device */
161 clrbits_be32(&cp->cp_pbdat, 0x0001);
162
163 /* Setting tx bd status and data length */
164 out_be32(&tbdf->cbd_bufaddr, (ulong)dout);
165 out_be16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_LAST | BD_SC_WRAP);
166 out_be16(&tbdf->cbd_datlen, count);
167
168 /* Setting rx bd status and data length */
169 out_be32(&rbdf->cbd_bufaddr, (ulong)din);
170 out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_WRAP);
171 out_be16(&rbdf->cbd_datlen, 0); /* rx length has no significance */
172
173 clrsetbits_be16(&cp->cp_spmode, ~SPMODE_LOOP, SPMODE_REV | SPMODE_MSTR |
174 SPMODE_EN | SPMODE_LEN(8) | SPMODE_PM(0x8));
175 out_8(&cp->cp_spim, 0); /* Mask all SPI events */
176 out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */
177
178 /* start spi transfer */
179 setbits_8(&cp->cp_spcom, SPI_STR); /* Start transmit */
180
181 /* --------------------------------
182 * Wait for SPI transmit to get out
183 * or time out (1 second = 1000 ms)
184 * -------------------------------- */
185 for (tm = 0; tm < 1000; ++tm) {
186 if (in_8(&cp->cp_spie) & SPI_TXB) /* Tx Buffer Empty */
187 break;
188 if ((in_be16(&tbdf->cbd_sc) & BD_SC_READY) == 0)
189 break;
190 udelay(1000);
191 }
192 if (tm >= 1000)
193 printf("*** spi_xfer: Time out while xferring to/from SPI!\n");
194
195 /* Clear CS for device */
196 setbits_be32(&cp->cp_pbdat, 0x0001);
197
198 return count;
199 }
200
201 static const struct dm_spi_ops mpc8xx_spi_ops = {
202 .xfer = mpc8xx_spi_xfer,
203 };
204
205 static const struct udevice_id mpc8xx_spi_ids[] = {
206 { .compatible = "fsl,mpc8xx-spi" },
207 { }
208 };
209
210 U_BOOT_DRIVER(mpc8xx_spi) = {
211 .name = "mpc8xx_spi",
212 .id = UCLASS_SPI,
213 .of_match = mpc8xx_spi_ids,
214 .ops = &mpc8xx_spi_ops,
215 .probe = mpc8xx_spi_probe,
216 };
217