1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2014 Freescale Semiconductor, Inc.
4  */
5 
6 #include <common.h>
7 #include <i2c.h>
8 #include <asm/io.h>
9 #include <asm/arch/immap_ls102xa.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/fsl_serdes.h>
12 #include <asm/arch/ls102xa_devdis.h>
13 #include <asm/arch/ls102xa_soc.h>
14 #include <hwconfig.h>
15 #include <mmc.h>
16 #include <fsl_csu.h>
17 #include <fsl_esdhc.h>
18 #include <fsl_ifc.h>
19 #include <fsl_immap.h>
20 #include <netdev.h>
21 #include <fsl_mdio.h>
22 #include <tsec.h>
23 #include <fsl_sec.h>
24 #include <fsl_devdis.h>
25 #include <spl.h>
26 #include "../common/sleep.h"
27 #ifdef CONFIG_U_QE
28 #include <fsl_qe.h>
29 #endif
30 #include <fsl_validate.h>
31 
32 
33 DECLARE_GLOBAL_DATA_PTR;
34 
35 #define VERSION_MASK		0x00FF
36 #define BANK_MASK		0x0001
37 #define CONFIG_RESET		0x1
38 #define INIT_RESET		0x1
39 
40 #define CPLD_SET_MUX_SERDES	0x20
41 #define CPLD_SET_BOOT_BANK	0x40
42 
43 #define BOOT_FROM_UPPER_BANK	0x0
44 #define BOOT_FROM_LOWER_BANK	0x1
45 
46 #define LANEB_SATA		(0x01)
47 #define LANEB_SGMII1		(0x02)
48 #define LANEC_SGMII1		(0x04)
49 #define LANEC_PCIEX1		(0x08)
50 #define LANED_PCIEX2		(0x10)
51 #define LANED_SGMII2		(0x20)
52 
53 #define MASK_LANE_B		0x1
54 #define MASK_LANE_C		0x2
55 #define MASK_LANE_D		0x4
56 #define MASK_SGMII		0x8
57 
58 #define KEEP_STATUS		0x0
59 #define NEED_RESET		0x1
60 
61 #define SOFT_MUX_ON_I2C3_IFC	0x2
62 #define SOFT_MUX_ON_CAN3_USB2	0x8
63 #define SOFT_MUX_ON_QE_LCD	0x10
64 
65 #define PIN_I2C3_IFC_MUX_I2C3	0x0
66 #define PIN_I2C3_IFC_MUX_IFC	0x1
67 #define PIN_CAN3_USB2_MUX_USB2	0x0
68 #define PIN_CAN3_USB2_MUX_CAN3	0x1
69 #define PIN_QE_LCD_MUX_LCD	0x0
70 #define PIN_QE_LCD_MUX_QE	0x1
71 
72 struct cpld_data {
73 	u8 cpld_ver;		/* cpld revision */
74 	u8 cpld_ver_sub;	/* cpld sub revision */
75 	u8 pcba_ver;		/* pcb revision number */
76 	u8 system_rst;		/* reset system by cpld */
77 	u8 soft_mux_on;		/* CPLD override physical switches Enable */
78 	u8 cfg_rcw_src1;	/* Reset config word 1 */
79 	u8 cfg_rcw_src2;	/* Reset config word 2 */
80 	u8 vbank;		/* Flash bank selection Control */
81 	u8 gpio;		/* GPIO for TWR-ELEV */
82 	u8 i2c3_ifc_mux;
83 	u8 mux_spi2;
84 	u8 can3_usb2_mux;	/* CAN3 and USB2 Selection */
85 	u8 qe_lcd_mux;		/* QE and LCD Selection */
86 	u8 serdes_mux;		/* Multiplexed pins for SerDes Lanes */
87 	u8 global_rst;		/* reset with init CPLD reg to default */
88 	u8 rev1;		/* Reserved */
89 	u8 rev2;		/* Reserved */
90 };
91 
92 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
cpld_show(void)93 static void cpld_show(void)
94 {
95 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
96 
97 	printf("CPLD:  V%x.%x\nPCBA:  V%x.0\nVBank: %d\n",
98 	       in_8(&cpld_data->cpld_ver) & VERSION_MASK,
99 	       in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
100 	       in_8(&cpld_data->pcba_ver) & VERSION_MASK,
101 	       in_8(&cpld_data->vbank) & BANK_MASK);
102 
103 #ifdef CONFIG_DEBUG
104 	printf("soft_mux_on =%x\n",
105 	       in_8(&cpld_data->soft_mux_on));
106 	printf("cfg_rcw_src1 =%x\n",
107 	       in_8(&cpld_data->cfg_rcw_src1));
108 	printf("cfg_rcw_src2 =%x\n",
109 	       in_8(&cpld_data->cfg_rcw_src2));
110 	printf("vbank =%x\n",
111 	       in_8(&cpld_data->vbank));
112 	printf("gpio =%x\n",
113 	       in_8(&cpld_data->gpio));
114 	printf("i2c3_ifc_mux =%x\n",
115 	       in_8(&cpld_data->i2c3_ifc_mux));
116 	printf("mux_spi2 =%x\n",
117 	       in_8(&cpld_data->mux_spi2));
118 	printf("can3_usb2_mux =%x\n",
119 	       in_8(&cpld_data->can3_usb2_mux));
120 	printf("qe_lcd_mux =%x\n",
121 	       in_8(&cpld_data->qe_lcd_mux));
122 	printf("serdes_mux =%x\n",
123 	       in_8(&cpld_data->serdes_mux));
124 #endif
125 }
126 #endif
127 
checkboard(void)128 int checkboard(void)
129 {
130 	puts("Board: LS1021ATWR\n");
131 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
132 	cpld_show();
133 #endif
134 
135 	return 0;
136 }
137 
ddrmc_init(void)138 void ddrmc_init(void)
139 {
140 	struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
141 	u32 temp_sdram_cfg, tmp;
142 
143 	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
144 
145 	out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
146 	out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
147 
148 	out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
149 	out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
150 	out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
151 	out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
152 	out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
153 	out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
154 
155 #ifdef CONFIG_DEEP_SLEEP
156 	if (is_warm_boot()) {
157 		out_be32(&ddr->sdram_cfg_2,
158 			 DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
159 		out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
160 		out_be32(&ddr->init_ext_addr, (1 << 31));
161 
162 		/* DRAM VRef will not be trained */
163 		out_be32(&ddr->ddr_cdr2,
164 			 DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
165 	} else
166 #endif
167 	{
168 		out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
169 		out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
170 	}
171 
172 	out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
173 	out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
174 
175 	out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
176 
177 	out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
178 
179 	out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
180 	out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
181 
182 	out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
183 
184 	out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
185 	out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
186 
187 	out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
188 
189 	/* DDR erratum A-009942 */
190 	tmp = in_be32(&ddr->debug[28]);
191 	out_be32(&ddr->debug[28], tmp | 0x0070006f);
192 
193 	udelay(1);
194 
195 #ifdef CONFIG_DEEP_SLEEP
196 	if (is_warm_boot()) {
197 		/* enter self-refresh */
198 		temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
199 		temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
200 		out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
201 
202 		temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
203 	} else
204 #endif
205 		temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
206 
207 	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
208 
209 #ifdef CONFIG_DEEP_SLEEP
210 	if (is_warm_boot()) {
211 		/* exit self-refresh */
212 		temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
213 		temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
214 		out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
215 	}
216 #endif
217 }
218 
dram_init(void)219 int dram_init(void)
220 {
221 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
222 	ddrmc_init();
223 #endif
224 
225 	erratum_a008850_post();
226 
227 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
228 
229 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
230 	fsl_dp_resume();
231 #endif
232 
233 	return 0;
234 }
235 
236 #ifdef CONFIG_FSL_ESDHC
237 struct fsl_esdhc_cfg esdhc_cfg[1] = {
238 	{CONFIG_SYS_FSL_ESDHC_ADDR},
239 };
240 
board_mmc_init(bd_t * bis)241 int board_mmc_init(bd_t *bis)
242 {
243 	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
244 
245 	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
246 }
247 #endif
248 
board_eth_init(bd_t * bis)249 int board_eth_init(bd_t *bis)
250 {
251 #ifdef CONFIG_TSEC_ENET
252 	struct fsl_pq_mdio_info mdio_info;
253 	struct tsec_info_struct tsec_info[4];
254 	int num = 0;
255 
256 #ifdef CONFIG_TSEC1
257 	SET_STD_TSEC_INFO(tsec_info[num], 1);
258 	if (is_serdes_configured(SGMII_TSEC1)) {
259 		puts("eTSEC1 is in sgmii mode.\n");
260 		tsec_info[num].flags |= TSEC_SGMII;
261 	}
262 	num++;
263 #endif
264 #ifdef CONFIG_TSEC2
265 	SET_STD_TSEC_INFO(tsec_info[num], 2);
266 	if (is_serdes_configured(SGMII_TSEC2)) {
267 		puts("eTSEC2 is in sgmii mode.\n");
268 		tsec_info[num].flags |= TSEC_SGMII;
269 	}
270 	num++;
271 #endif
272 #ifdef CONFIG_TSEC3
273 	SET_STD_TSEC_INFO(tsec_info[num], 3);
274 	tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
275 	num++;
276 #endif
277 	if (!num) {
278 		printf("No TSECs initialized\n");
279 		return 0;
280 	}
281 
282 	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
283 	mdio_info.name = DEFAULT_MII_NAME;
284 	fsl_pq_mdio_init(bis, &mdio_info);
285 
286 	tsec_eth_init(bis, tsec_info, num);
287 #endif
288 
289 	return pci_eth_init(bis);
290 }
291 
292 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
convert_serdes_mux(int type,int need_reset)293 static void convert_serdes_mux(int type, int need_reset)
294 {
295 	char current_serdes;
296 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
297 
298 	current_serdes = cpld_data->serdes_mux;
299 
300 	switch (type) {
301 	case LANEB_SATA:
302 		current_serdes &= ~MASK_LANE_B;
303 		break;
304 	case LANEB_SGMII1:
305 		current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
306 		break;
307 	case LANEC_SGMII1:
308 		current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
309 		break;
310 	case LANED_SGMII2:
311 		current_serdes |= MASK_LANE_D;
312 		break;
313 	case LANEC_PCIEX1:
314 		current_serdes |= MASK_LANE_C;
315 		break;
316 	case (LANED_PCIEX2 | LANEC_PCIEX1):
317 		current_serdes |= MASK_LANE_C;
318 		current_serdes &= ~MASK_LANE_D;
319 		break;
320 	default:
321 		printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
322 		return;
323 	}
324 
325 	cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
326 	cpld_data->serdes_mux = current_serdes;
327 
328 	if (need_reset == 1) {
329 		printf("Reset board to enable configuration\n");
330 		cpld_data->system_rst = CONFIG_RESET;
331 	}
332 }
333 
config_serdes_mux(void)334 int config_serdes_mux(void)
335 {
336 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
337 	u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
338 
339 	protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
340 	switch (protocol) {
341 	case 0x10:
342 		convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
343 		convert_serdes_mux(LANED_PCIEX2 |
344 				LANEC_PCIEX1, KEEP_STATUS);
345 		break;
346 	case 0x20:
347 		convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
348 		convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
349 		convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
350 		break;
351 	case 0x30:
352 		convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
353 		convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
354 		convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
355 		break;
356 	case 0x70:
357 		convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
358 		convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
359 		convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
360 		break;
361 	}
362 
363 	return 0;
364 }
365 #endif
366 
367 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
config_board_mux(void)368 int config_board_mux(void)
369 {
370 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
371 	int conflict_flag;
372 
373 	conflict_flag = 0;
374 	if (hwconfig("i2c3")) {
375 		conflict_flag++;
376 		cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
377 		cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3;
378 	}
379 
380 	if (hwconfig("ifc")) {
381 		conflict_flag++;
382 		/* some signals can not enable simultaneous*/
383 		if (conflict_flag > 1)
384 			goto conflict;
385 		cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
386 		cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC;
387 	}
388 
389 	conflict_flag = 0;
390 	if (hwconfig("usb2")) {
391 		conflict_flag++;
392 		cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
393 		cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2;
394 	}
395 
396 	if (hwconfig("can3")) {
397 		conflict_flag++;
398 		/* some signals can not enable simultaneous*/
399 		if (conflict_flag > 1)
400 			goto conflict;
401 		cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
402 		cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3;
403 	}
404 
405 	conflict_flag = 0;
406 	if (hwconfig("lcd")) {
407 		conflict_flag++;
408 		cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
409 		cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD;
410 	}
411 
412 	if (hwconfig("qe")) {
413 		conflict_flag++;
414 		/* some signals can not enable simultaneous*/
415 		if (conflict_flag > 1)
416 			goto conflict;
417 		cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
418 		cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE;
419 	}
420 
421 	return 0;
422 
423 conflict:
424 	printf("WARNING: pin conflict! MUX setting may failed!\n");
425 	return 0;
426 }
427 #endif
428 
board_early_init_f(void)429 int board_early_init_f(void)
430 {
431 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
432 
433 #ifdef CONFIG_TSEC_ENET
434 	/* clear BD & FR bits for BE BD's and frame data */
435 	clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
436 	out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
437 #endif
438 
439 #ifdef CONFIG_FSL_IFC
440 	init_early_memctl_regs();
441 #endif
442 
443 	arch_soc_init();
444 
445 #if defined(CONFIG_DEEP_SLEEP)
446 	if (is_warm_boot()) {
447 		timer_init();
448 		dram_init();
449 	}
450 #endif
451 
452 	return 0;
453 }
454 
455 #ifdef CONFIG_SPL_BUILD
board_init_f(ulong dummy)456 void board_init_f(ulong dummy)
457 {
458 	void (*second_uboot)(void);
459 
460 	/* Clear the BSS */
461 	memset(__bss_start, 0, __bss_end - __bss_start);
462 
463 	get_clocks();
464 
465 #if defined(CONFIG_DEEP_SLEEP)
466 	if (is_warm_boot())
467 		fsl_dp_disable_console();
468 #endif
469 
470 	preloader_console_init();
471 
472 	timer_init();
473 	dram_init();
474 
475 	/* Allow OCRAM access permission as R/W */
476 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
477 	enable_layerscape_ns_access();
478 #endif
479 
480 	/*
481 	 * if it is woken up from deep sleep, then jump to second
482 	 * stage uboot and continue executing without recopying
483 	 * it from SD since it has already been reserved in memeory
484 	 * in last boot.
485 	 */
486 	if (is_warm_boot()) {
487 		second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
488 		second_uboot();
489 	}
490 
491 	board_init_r(NULL, 0);
492 }
493 #endif
494 
495 #ifdef CONFIG_DEEP_SLEEP
496 /* program the regulator (MC34VR500) to support deep sleep */
ls1twr_program_regulator(void)497 void ls1twr_program_regulator(void)
498 {
499 	unsigned int i2c_bus;
500 	u8 i2c_device_id;
501 
502 #define LS1TWR_I2C_BUS_MC34VR500	1
503 #define MC34VR500_ADDR			0x8
504 #define MC34VR500_DEVICEID		0x4
505 #define MC34VR500_DEVICEID_MASK		0x0f
506 
507 	i2c_bus = i2c_get_bus_num();
508 	i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
509 	i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
510 					MC34VR500_DEVICEID_MASK;
511 	if (i2c_device_id != MC34VR500_DEVICEID) {
512 		printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
513 		return;
514 	}
515 
516 	i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4);
517 	i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4);
518 	i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38);
519 	i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37);
520 	i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
521 
522 	i2c_set_bus_num(i2c_bus);
523 }
524 #endif
525 
board_init(void)526 int board_init(void)
527 {
528 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
529 	erratum_a010315();
530 #endif
531 
532 #ifndef CONFIG_SYS_FSL_NO_SERDES
533 	fsl_serdes_init();
534 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
535 	config_serdes_mux();
536 #endif
537 #endif
538 
539 	ls102xa_smmu_stream_id_init();
540 
541 #ifdef CONFIG_U_QE
542 	u_qe_init();
543 #endif
544 
545 #ifdef CONFIG_DEEP_SLEEP
546 	ls1twr_program_regulator();
547 #endif
548 	return 0;
549 }
550 
551 #if defined(CONFIG_SPL_BUILD)
spl_board_init(void)552 void spl_board_init(void)
553 {
554 	ls102xa_smmu_stream_id_init();
555 }
556 #endif
557 
558 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)559 int board_late_init(void)
560 {
561 #ifdef CONFIG_CHAIN_OF_TRUST
562 	fsl_setenv_chain_of_trust();
563 #endif
564 
565 	return 0;
566 }
567 #endif
568 
569 #if defined(CONFIG_MISC_INIT_R)
misc_init_r(void)570 int misc_init_r(void)
571 {
572 #ifdef CONFIG_FSL_DEVICE_DISABLE
573 	device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
574 #endif
575 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
576 	config_board_mux();
577 #endif
578 
579 #ifdef CONFIG_FSL_CAAM
580 	return sec_init();
581 #endif
582 }
583 #endif
584 
585 #if defined(CONFIG_DEEP_SLEEP)
board_sleep_prepare(void)586 void board_sleep_prepare(void)
587 {
588 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
589 	enable_layerscape_ns_access();
590 #endif
591 }
592 #endif
593 
ft_board_setup(void * blob,bd_t * bd)594 int ft_board_setup(void *blob, bd_t *bd)
595 {
596 	ft_cpu_setup(blob, bd);
597 
598 #ifdef CONFIG_PCI
599 	ft_pci_setup(blob, bd);
600 #endif
601 
602 	return 0;
603 }
604 
flash_read8(void * addr)605 u8 flash_read8(void *addr)
606 {
607 	return __raw_readb(addr + 1);
608 }
609 
flash_write16(u16 val,void * addr)610 void flash_write16(u16 val, void *addr)
611 {
612 	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
613 
614 	__raw_writew(shftval, addr);
615 }
616 
flash_read16(void * addr)617 u16 flash_read16(void *addr)
618 {
619 	u16 val = __raw_readw(addr);
620 
621 	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
622 }
623 
624 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) \
625 	&& !defined(CONFIG_SPL_BUILD)
convert_flash_bank(char bank)626 static void convert_flash_bank(char bank)
627 {
628 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
629 
630 	printf("Now switch to boot from flash bank %d.\n", bank);
631 	cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
632 	cpld_data->vbank = bank;
633 
634 	printf("Reset board to enable configuration.\n");
635 	cpld_data->system_rst = CONFIG_RESET;
636 }
637 
flash_bank_cmd(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])638 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
639 			  char * const argv[])
640 {
641 	if (argc != 2)
642 		return CMD_RET_USAGE;
643 	if (strcmp(argv[1], "0") == 0)
644 		convert_flash_bank(BOOT_FROM_UPPER_BANK);
645 	else if (strcmp(argv[1], "1") == 0)
646 		convert_flash_bank(BOOT_FROM_LOWER_BANK);
647 	else
648 		return CMD_RET_USAGE;
649 
650 	return 0;
651 }
652 
653 U_BOOT_CMD(
654 	boot_bank, 2, 0, flash_bank_cmd,
655 	"Flash bank Selection Control",
656 	"bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
657 );
658 
cpld_reset_cmd(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])659 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
660 			  char * const argv[])
661 {
662 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
663 
664 	if (argc > 2)
665 		return CMD_RET_USAGE;
666 	if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
667 		cpld_data->system_rst = CONFIG_RESET;
668 	else if (strcmp(argv[1], "init") == 0)
669 		cpld_data->global_rst = INIT_RESET;
670 	else
671 		return CMD_RET_USAGE;
672 
673 	return 0;
674 }
675 
676 U_BOOT_CMD(
677 	cpld_reset, 2, 0, cpld_reset_cmd,
678 	"Reset via CPLD",
679 	"conf\n"
680 	"	-reset with current CPLD configuration\n"
681 	"init\n"
682 	"	-reset and initial CPLD configuration with default value"
683 
684 );
685 
print_serdes_mux(void)686 static void print_serdes_mux(void)
687 {
688 	char current_serdes;
689 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
690 
691 	current_serdes = cpld_data->serdes_mux;
692 
693 	printf("Serdes Lane B: ");
694 	if ((current_serdes & MASK_LANE_B) == 0)
695 		printf("SATA,\n");
696 	else
697 		printf("SGMII 1,\n");
698 
699 	printf("Serdes Lane C: ");
700 	if ((current_serdes & MASK_LANE_C) == 0)
701 		printf("SGMII 1,\n");
702 	else
703 		printf("PCIe,\n");
704 
705 	printf("Serdes Lane D: ");
706 	if ((current_serdes & MASK_LANE_D) == 0)
707 		printf("PCIe,\n");
708 	else
709 		printf("SGMII 2,\n");
710 
711 	printf("SGMII 1 is on lane ");
712 	if ((current_serdes & MASK_SGMII) == 0)
713 		printf("C.\n");
714 	else
715 		printf("B.\n");
716 }
717 
serdes_mux_cmd(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])718 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
719 			  char * const argv[])
720 {
721 	if (argc != 2)
722 		return CMD_RET_USAGE;
723 	if (strcmp(argv[1], "sata") == 0) {
724 		printf("Set serdes lane B to SATA.\n");
725 		convert_serdes_mux(LANEB_SATA, NEED_RESET);
726 	} else if (strcmp(argv[1], "sgmii1b") == 0) {
727 		printf("Set serdes lane B to SGMII 1.\n");
728 		convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
729 	} else if (strcmp(argv[1], "sgmii1c") == 0) {
730 		printf("Set serdes lane C to SGMII 1.\n");
731 		convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
732 	} else if (strcmp(argv[1], "sgmii2") == 0) {
733 		printf("Set serdes lane D to SGMII 2.\n");
734 		convert_serdes_mux(LANED_SGMII2, NEED_RESET);
735 	} else if (strcmp(argv[1], "pciex1") == 0) {
736 		printf("Set serdes lane C to PCIe X1.\n");
737 		convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
738 	} else if (strcmp(argv[1], "pciex2") == 0) {
739 		printf("Set serdes lane C & lane D to PCIe X2.\n");
740 		convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
741 	} else if (strcmp(argv[1], "show") == 0) {
742 		print_serdes_mux();
743 	} else {
744 		return CMD_RET_USAGE;
745 	}
746 
747 	return 0;
748 }
749 
750 U_BOOT_CMD(
751 	lane_bank, 2, 0, serdes_mux_cmd,
752 	"Multiplexed function setting for SerDes Lanes",
753 	"sata\n"
754 	"	-change lane B to sata\n"
755 	"lane_bank sgmii1b\n"
756 	"	-change lane B to SGMII1\n"
757 	"lane_bank sgmii1c\n"
758 	"	-change lane C to SGMII1\n"
759 	"lane_bank sgmii2\n"
760 	"	-change lane D to SGMII2\n"
761 	"lane_bank pciex1\n"
762 	"	-change lane C to PCIeX1\n"
763 	"lane_bank pciex2\n"
764 	"	-change lane C & lane D to PCIeX2\n"
765 	"\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
766 );
767 #endif
768