1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R-Car Gen4 Clock Pulse Generator
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 *
7 * Based on rcar-gen3-cpg.c
8 *
9 * Copyright (C) 2015-2018 Glider bvba
10 * Copyright (C) 2019 Renesas Electronics Corp.
11 */
12
13 #include <linux/bitfield.h>
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
16 #include <linux/device.h>
17 #include <linux/err.h>
18 #include <linux/init.h>
19 #include <linux/io.h>
20 #include <linux/iopoll.h>
21 #include <linux/slab.h>
22
23 #include "renesas-cpg-mssr.h"
24 #include "rcar-gen4-cpg.h"
25 #include "rcar-cpg-lib.h"
26
27 static const struct rcar_gen4_cpg_pll_config *cpg_pll_config __initdata;
28 static unsigned int cpg_clk_extalr __initdata;
29 static u32 cpg_mode __initdata;
30
31 #define CPG_PLLECR 0x0820 /* PLL Enable Control Register */
32
33 #define CPG_PLLECR_PLLST(n) BIT(8 + ((n) < 3 ? (n) - 1 : \
34 (n) > 3 ? (n) + 1 : n)) /* PLLn Circuit Status */
35
36 #define CPG_PLL1CR0 0x830 /* PLLn Control Registers */
37 #define CPG_PLL1CR1 0x8b0
38 #define CPG_PLL2CR0 0x834
39 #define CPG_PLL2CR1 0x8b8
40 #define CPG_PLL3CR0 0x83c
41 #define CPG_PLL3CR1 0x8c0
42 #define CPG_PLL4CR0 0x844
43 #define CPG_PLL4CR1 0x8c8
44 #define CPG_PLL6CR0 0x84c
45 #define CPG_PLL6CR1 0x8d8
46
47 #define CPG_PLLxCR0_KICK BIT(31)
48 #define CPG_PLLxCR0_NI GENMASK(27, 20) /* Integer mult. factor */
49 #define CPG_PLLxCR0_SSMODE GENMASK(18, 16) /* PLL mode */
50 #define CPG_PLLxCR0_SSMODE_FM BIT(18) /* Fractional Multiplication */
51 #define CPG_PLLxCR0_SSMODE_DITH BIT(17) /* Frequency Dithering */
52 #define CPG_PLLxCR0_SSMODE_CENT BIT(16) /* Center (vs. Down) Spread Dithering */
53 #define CPG_PLLxCR0_SSFREQ GENMASK(14, 8) /* SSCG Modulation Frequency */
54 #define CPG_PLLxCR0_SSDEPT GENMASK(6, 0) /* SSCG Modulation Depth */
55
56 #define SSMODE_FM BIT(2) /* Fractional Multiplication */
57 #define SSMODE_DITHER BIT(1) /* Frequency Dithering */
58 #define SSMODE_CENTER BIT(0) /* Center (vs. Down) Spread Dithering */
59
60 /* PLL Clocks */
61 struct cpg_pll_clk {
62 struct clk_hw hw;
63 void __iomem *pllcr0_reg;
64 void __iomem *pllecr_reg;
65 u32 pllecr_pllst_mask;
66 };
67
68 #define to_pll_clk(_hw) container_of(_hw, struct cpg_pll_clk, hw)
69
cpg_pll_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)70 static unsigned long cpg_pll_clk_recalc_rate(struct clk_hw *hw,
71 unsigned long parent_rate)
72 {
73 struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
74 unsigned int mult;
75
76 mult = FIELD_GET(CPG_PLLxCR0_NI, readl(pll_clk->pllcr0_reg)) + 1;
77
78 return parent_rate * mult * 2;
79 }
80
cpg_pll_clk_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)81 static int cpg_pll_clk_determine_rate(struct clk_hw *hw,
82 struct clk_rate_request *req)
83 {
84 unsigned int min_mult, max_mult, mult;
85 unsigned long prate;
86
87 prate = req->best_parent_rate * 2;
88 min_mult = max(div64_ul(req->min_rate, prate), 1ULL);
89 max_mult = min(div64_ul(req->max_rate, prate), 256ULL);
90 if (max_mult < min_mult)
91 return -EINVAL;
92
93 mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate);
94 mult = clamp(mult, min_mult, max_mult);
95
96 req->rate = prate * mult;
97 return 0;
98 }
99
cpg_pll_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)100 static int cpg_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
101 unsigned long parent_rate)
102 {
103 struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
104 unsigned int mult;
105 u32 val;
106
107 mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * 2);
108 mult = clamp(mult, 1U, 256U);
109
110 if (readl(pll_clk->pllcr0_reg) & CPG_PLLxCR0_KICK)
111 return -EBUSY;
112
113 cpg_reg_modify(pll_clk->pllcr0_reg, CPG_PLLxCR0_NI,
114 FIELD_PREP(CPG_PLLxCR0_NI, mult - 1));
115
116 /*
117 * Set KICK bit in PLLxCR0 to update hardware setting and wait for
118 * clock change completion.
119 */
120 cpg_reg_modify(pll_clk->pllcr0_reg, 0, CPG_PLLxCR0_KICK);
121
122 /*
123 * Note: There is no HW information about the worst case latency.
124 *
125 * Using experimental measurements, it seems that no more than
126 * ~45 µs are needed, independently of the CPU rate.
127 * Since this value might be dependent on external xtal rate, pll
128 * rate or even the other emulation clocks rate, use 1000 as a
129 * "super" safe value.
130 */
131 return readl_poll_timeout(pll_clk->pllecr_reg, val,
132 val & pll_clk->pllecr_pllst_mask, 0, 1000);
133 }
134
135 static const struct clk_ops cpg_pll_clk_ops = {
136 .recalc_rate = cpg_pll_clk_recalc_rate,
137 .determine_rate = cpg_pll_clk_determine_rate,
138 .set_rate = cpg_pll_clk_set_rate,
139 };
140
cpg_pll_clk_register(const char * name,const char * parent_name,void __iomem * base,unsigned int cr0_offset,unsigned int cr1_offset,unsigned int index)141 static struct clk * __init cpg_pll_clk_register(const char *name,
142 const char *parent_name,
143 void __iomem *base,
144 unsigned int cr0_offset,
145 unsigned int cr1_offset,
146 unsigned int index)
147
148 {
149 struct cpg_pll_clk *pll_clk;
150 struct clk_init_data init = {};
151 struct clk *clk;
152
153 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
154 if (!pll_clk)
155 return ERR_PTR(-ENOMEM);
156
157 init.name = name;
158 init.ops = &cpg_pll_clk_ops;
159 init.parent_names = &parent_name;
160 init.num_parents = 1;
161
162 pll_clk->hw.init = &init;
163 pll_clk->pllcr0_reg = base + cr0_offset;
164 pll_clk->pllecr_reg = base + CPG_PLLECR;
165 pll_clk->pllecr_pllst_mask = CPG_PLLECR_PLLST(index);
166
167 /* Disable Fractional Multiplication and Frequency Dithering */
168 writel(0, base + cr1_offset);
169 cpg_reg_modify(pll_clk->pllcr0_reg, CPG_PLLxCR0_SSMODE, 0);
170
171 clk = clk_register(NULL, &pll_clk->hw);
172 if (IS_ERR(clk))
173 kfree(pll_clk);
174
175 return clk;
176 }
177 /*
178 * Z0 Clock & Z1 Clock
179 */
180 #define CPG_FRQCRB 0x00000804
181 #define CPG_FRQCRB_KICK BIT(31)
182 #define CPG_FRQCRC 0x00000808
183
184 struct cpg_z_clk {
185 struct clk_hw hw;
186 void __iomem *reg;
187 void __iomem *kick_reg;
188 unsigned long max_rate; /* Maximum rate for normal mode */
189 unsigned int fixed_div;
190 u32 mask;
191 };
192
193 #define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
194
cpg_z_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)195 static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
196 unsigned long parent_rate)
197 {
198 struct cpg_z_clk *zclk = to_z_clk(hw);
199 unsigned int mult;
200 u32 val;
201
202 val = readl(zclk->reg) & zclk->mask;
203 mult = 32 - (val >> __ffs(zclk->mask));
204
205 return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult,
206 32 * zclk->fixed_div);
207 }
208
cpg_z_clk_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)209 static int cpg_z_clk_determine_rate(struct clk_hw *hw,
210 struct clk_rate_request *req)
211 {
212 struct cpg_z_clk *zclk = to_z_clk(hw);
213 unsigned int min_mult, max_mult, mult;
214 unsigned long rate, prate;
215
216 rate = min(req->rate, req->max_rate);
217 if (rate <= zclk->max_rate) {
218 /* Set parent rate to initial value for normal modes */
219 prate = zclk->max_rate;
220 } else {
221 /* Set increased parent rate for boost modes */
222 prate = rate;
223 }
224 req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
225 prate * zclk->fixed_div);
226
227 prate = req->best_parent_rate / zclk->fixed_div;
228 min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL);
229 max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL);
230 if (max_mult < min_mult)
231 return -EINVAL;
232
233 mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate);
234 mult = clamp(mult, min_mult, max_mult);
235
236 req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32);
237 return 0;
238 }
239
cpg_z_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)240 static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
241 unsigned long parent_rate)
242 {
243 struct cpg_z_clk *zclk = to_z_clk(hw);
244 unsigned int mult;
245 unsigned int i;
246
247 mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div,
248 parent_rate);
249 mult = clamp(mult, 1U, 32U);
250
251 if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
252 return -EBUSY;
253
254 cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask));
255
256 /*
257 * Set KICK bit in FRQCRB to update hardware setting and wait for
258 * clock change completion.
259 */
260 cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK);
261
262 /*
263 * Note: There is no HW information about the worst case latency.
264 *
265 * Using experimental measurements, it seems that no more than
266 * ~10 iterations are needed, independently of the CPU rate.
267 * Since this value might be dependent on external xtal rate, pll1
268 * rate or even the other emulation clocks rate, use 1000 as a
269 * "super" safe value.
270 */
271 for (i = 1000; i; i--) {
272 if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
273 return 0;
274
275 cpu_relax();
276 }
277
278 return -ETIMEDOUT;
279 }
280
281 static const struct clk_ops cpg_z_clk_ops = {
282 .recalc_rate = cpg_z_clk_recalc_rate,
283 .determine_rate = cpg_z_clk_determine_rate,
284 .set_rate = cpg_z_clk_set_rate,
285 };
286
cpg_z_clk_register(const char * name,const char * parent_name,void __iomem * reg,unsigned int div,unsigned int offset)287 static struct clk * __init cpg_z_clk_register(const char *name,
288 const char *parent_name,
289 void __iomem *reg,
290 unsigned int div,
291 unsigned int offset)
292 {
293 struct clk_init_data init = {};
294 struct cpg_z_clk *zclk;
295 struct clk *clk;
296
297 zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
298 if (!zclk)
299 return ERR_PTR(-ENOMEM);
300
301 init.name = name;
302 init.ops = &cpg_z_clk_ops;
303 init.flags = CLK_SET_RATE_PARENT;
304 init.parent_names = &parent_name;
305 init.num_parents = 1;
306
307 zclk->reg = reg + CPG_FRQCRC;
308 zclk->kick_reg = reg + CPG_FRQCRB;
309 zclk->hw.init = &init;
310 zclk->mask = GENMASK(offset + 4, offset);
311 zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */
312
313 clk = clk_register(NULL, &zclk->hw);
314 if (IS_ERR(clk)) {
315 kfree(zclk);
316 return clk;
317 }
318
319 zclk->max_rate = clk_hw_get_rate(clk_hw_get_parent(&zclk->hw)) /
320 zclk->fixed_div;
321 return clk;
322 }
323
324 /*
325 * RPC Clocks
326 */
327 static const struct clk_div_table cpg_rpcsrc_div_table[] = {
328 { 0, 4 }, { 1, 6 }, { 2, 5 }, { 3, 6 }, { 0, 0 },
329 };
330
rcar_gen4_cpg_clk_register(struct device * dev,const struct cpg_core_clk * core,const struct cpg_mssr_info * info,struct clk ** clks,void __iomem * base,struct raw_notifier_head * notifiers)331 struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev,
332 const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
333 struct clk **clks, void __iomem *base,
334 struct raw_notifier_head *notifiers)
335 {
336 const struct clk *parent;
337 unsigned int mult = 1;
338 unsigned int div = 1;
339 u32 value;
340
341 parent = clks[core->parent & 0xffff]; /* some types use high bits */
342 if (IS_ERR(parent))
343 return ERR_CAST(parent);
344
345 switch (core->type) {
346 case CLK_TYPE_GEN4_MAIN:
347 div = cpg_pll_config->extal_div;
348 break;
349
350 case CLK_TYPE_GEN4_PLL1:
351 mult = cpg_pll_config->pll1_mult;
352 div = cpg_pll_config->pll1_div;
353 break;
354
355 case CLK_TYPE_GEN4_PLL2_VAR:
356 /*
357 * PLL2 is implemented as a custom clock, to change the
358 * multiplier when cpufreq changes between normal and boost
359 * modes.
360 */
361 return cpg_pll_clk_register(core->name, __clk_get_name(parent),
362 base, CPG_PLL2CR0, CPG_PLL2CR1, 2);
363
364 case CLK_TYPE_GEN4_PLL2:
365 mult = cpg_pll_config->pll2_mult;
366 div = cpg_pll_config->pll2_div;
367 break;
368
369 case CLK_TYPE_GEN4_PLL3:
370 mult = cpg_pll_config->pll3_mult;
371 div = cpg_pll_config->pll3_div;
372 break;
373
374 case CLK_TYPE_GEN4_PLL4:
375 mult = cpg_pll_config->pll4_mult;
376 div = cpg_pll_config->pll4_div;
377 break;
378
379 case CLK_TYPE_GEN4_PLL5:
380 mult = cpg_pll_config->pll5_mult;
381 div = cpg_pll_config->pll5_div;
382 break;
383
384 case CLK_TYPE_GEN4_PLL6:
385 mult = cpg_pll_config->pll6_mult;
386 div = cpg_pll_config->pll6_div;
387 break;
388
389 case CLK_TYPE_GEN4_PLL2X_3X:
390 value = readl(base + core->offset);
391 mult = (((value >> 24) & 0x7f) + 1) * 2;
392 break;
393
394 case CLK_TYPE_GEN4_Z:
395 return cpg_z_clk_register(core->name, __clk_get_name(parent),
396 base, core->div, core->offset);
397
398 case CLK_TYPE_GEN4_SDSRC:
399 div = ((readl(base + SD0CKCR1) >> 29) & 0x03) + 4;
400 break;
401
402 case CLK_TYPE_GEN4_SDH:
403 return cpg_sdh_clk_register(core->name, base + core->offset,
404 __clk_get_name(parent), notifiers);
405
406 case CLK_TYPE_GEN4_SD:
407 return cpg_sd_clk_register(core->name, base + core->offset,
408 __clk_get_name(parent));
409
410 case CLK_TYPE_GEN4_MDSEL:
411 /*
412 * Clock selectable between two parents and two fixed dividers
413 * using a mode pin
414 */
415 if (cpg_mode & BIT(core->offset)) {
416 div = core->div & 0xffff;
417 } else {
418 parent = clks[core->parent >> 16];
419 if (IS_ERR(parent))
420 return ERR_CAST(parent);
421 div = core->div >> 16;
422 }
423 mult = 1;
424 break;
425
426 case CLK_TYPE_GEN4_OSC:
427 /*
428 * Clock combining OSC EXTAL predivider and a fixed divider
429 */
430 div = cpg_pll_config->osc_prediv * core->div;
431 break;
432
433 case CLK_TYPE_GEN4_RPCSRC:
434 return clk_register_divider_table(NULL, core->name,
435 __clk_get_name(parent), 0,
436 base + CPG_RPCCKCR, 3, 2, 0,
437 cpg_rpcsrc_div_table,
438 &cpg_lock);
439
440 case CLK_TYPE_GEN4_RPC:
441 return cpg_rpc_clk_register(core->name, base + CPG_RPCCKCR,
442 __clk_get_name(parent), notifiers);
443
444 case CLK_TYPE_GEN4_RPCD2:
445 return cpg_rpcd2_clk_register(core->name, base + CPG_RPCCKCR,
446 __clk_get_name(parent));
447
448 default:
449 return ERR_PTR(-EINVAL);
450 }
451
452 return clk_register_fixed_factor(NULL, core->name,
453 __clk_get_name(parent), 0, mult, div);
454 }
455
rcar_gen4_cpg_init(const struct rcar_gen4_cpg_pll_config * config,unsigned int clk_extalr,u32 mode)456 int __init rcar_gen4_cpg_init(const struct rcar_gen4_cpg_pll_config *config,
457 unsigned int clk_extalr, u32 mode)
458 {
459 cpg_pll_config = config;
460 cpg_clk_extalr = clk_extalr;
461 cpg_mode = mode;
462
463 spin_lock_init(&cpg_lock);
464
465 return 0;
466 }
467