1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Loongson ipi interrupt header files
4  *
5  * Copyright (C) 2021 Loongson Technology Corporation Limited
6  */
7 
8 #ifndef HW_LOONGSON_IPI_COMMON_H
9 #define HW_LOONGSON_IPI_COMMON_H
10 
11 #include "qom/object.h"
12 #include "hw/sysbus.h"
13 #include "exec/memattrs.h"
14 
15 #define IPI_MBX_NUM           4
16 
17 #define TYPE_LOONGSON_IPI_COMMON "loongson_ipi_common"
18 OBJECT_DECLARE_TYPE(LoongsonIPICommonState,
19                     LoongsonIPICommonClass, LOONGSON_IPI_COMMON)
20 
21 typedef struct IPICore {
22     LoongsonIPICommonState *ipi;
23     uint32_t status;
24     uint32_t en;
25     uint32_t set;
26     uint32_t clear;
27     /* 64bit buf divide into 2 32-bit buf */
28     uint32_t buf[IPI_MBX_NUM * 2];
29     qemu_irq irq;
30 } IPICore;
31 
32 struct LoongsonIPICommonState {
33     SysBusDevice parent_obj;
34 
35     MemoryRegion ipi_iocsr_mem;
36     MemoryRegion ipi64_iocsr_mem;
37     uint32_t num_cpu;
38     IPICore *cpu;
39 };
40 
41 struct LoongsonIPICommonClass {
42     SysBusDeviceClass parent_class;
43 
44     DeviceRealize parent_realize;
45     DeviceUnrealize parent_unrealize;
46     AddressSpace *(*get_iocsr_as)(CPUState *cpu);
47     CPUState *(*cpu_by_arch_id)(int64_t id);
48 };
49 
50 MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data,
51                                     unsigned size, MemTxAttrs attrs);
52 MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val,
53                                      unsigned size, MemTxAttrs attrs);
54 
55 /* Mainy used by iocsr read and write */
56 #define SMP_IPI_MAILBOX         0x1000ULL
57 
58 #define CORE_STATUS_OFF         0x0
59 #define CORE_EN_OFF             0x4
60 #define CORE_SET_OFF            0x8
61 #define CORE_CLEAR_OFF          0xc
62 #define CORE_BUF_20             0x20
63 #define CORE_BUF_28             0x28
64 #define CORE_BUF_30             0x30
65 #define CORE_BUF_38             0x38
66 #define IOCSR_IPI_SEND          0x40
67 #define IOCSR_MAIL_SEND         0x48
68 #define IOCSR_ANY_SEND          0x158
69 
70 #define MAIL_SEND_ADDR          (SMP_IPI_MAILBOX + IOCSR_MAIL_SEND)
71 #define MAIL_SEND_OFFSET        0
72 #define ANY_SEND_OFFSET         (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
73 
74 #endif
75