xref: /openbmc/qemu/include/hw/misc/imx6_src.h (revision c122bca9)
1 /*
2  * IMX6 System Reset Controller
3  *
4  * Copyright (C) 2012 NICTA
5  * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
6  *
7  * This work is licensed under the terms of the GNU GPL, version 2 or later.
8  * See the COPYING file in the top-level directory.
9  */
10 
11 #ifndef IMX6_SRC_H
12 #define IMX6_SRC_H
13 
14 #include "hw/sysbus.h"
15 #include "qemu/bitops.h"
16 #include "qom/object.h"
17 
18 #define SRC_SCR 0
19 #define SRC_SBMR1 1
20 #define SRC_SRSR 2
21 #define SRC_SISR 5
22 #define SRC_SIMR 6
23 #define SRC_SBMR2 7
24 #define SRC_GPR1 8
25 #define SRC_GPR2 9
26 #define SRC_GPR3 10
27 #define SRC_GPR4 11
28 #define SRC_GPR5 12
29 #define SRC_GPR6 13
30 #define SRC_GPR7 14
31 #define SRC_GPR8 15
32 #define SRC_GPR9 16
33 #define SRC_GPR10 17
34 #define SRC_MAX 18
35 
36 /* SRC_SCR */
37 #define CORE3_ENABLE_SHIFT     24
38 #define CORE3_ENABLE_LENGTH    1
39 #define CORE2_ENABLE_SHIFT     23
40 #define CORE2_ENABLE_LENGTH    1
41 #define CORE1_ENABLE_SHIFT     22
42 #define CORE1_ENABLE_LENGTH    1
43 #define CORE3_RST_SHIFT        16
44 #define CORE3_RST_LENGTH       1
45 #define CORE2_RST_SHIFT        15
46 #define CORE2_RST_LENGTH       1
47 #define CORE1_RST_SHIFT        14
48 #define CORE1_RST_LENGTH       1
49 #define CORE0_RST_SHIFT        13
50 #define CORE0_RST_LENGTH       1
51 #define SW_IPU1_RST_SHIFT      3
52 #define SW_IPU1_RST_LENGTH     1
53 #define SW_IPU2_RST_SHIFT      12
54 #define SW_IPU2_RST_LENGTH     1
55 #define WARM_RST_ENABLE_SHIFT  0
56 #define WARM_RST_ENABLE_LENGTH 1
57 
58 #define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH)
59 
60 #define TYPE_IMX6_SRC "imx6.src"
61 OBJECT_DECLARE_SIMPLE_TYPE(IMX6SRCState, IMX6_SRC)
62 
63 struct IMX6SRCState {
64     /* <private> */
65     SysBusDevice parent_obj;
66 
67     /* <public> */
68     MemoryRegion iomem;
69 
70     uint32_t regs[SRC_MAX];
71 
72 };
73 
74 #endif /* IMX6_SRC_H */
75