xref: /openbmc/u-boot/include/configs/MPC8569MDS.h (revision f18b7b27)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2009-2011 Freescale Semiconductor, Inc.
4  */
5 
6 /*
7  * mpc8569mds board configuration file
8  */
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11 
12 #define CONFIG_SYS_SRIO
13 #define CONFIG_SRIO1			/* SRIO port 1 */
14 
15 #define CONFIG_PCIE1		1	/* PCIE controller */
16 #define CONFIG_FSL_PCI_INIT	1	/* use common fsl pci init code */
17 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
18 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
19 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
20 #define CONFIG_QE			/* Enable QE */
21 #define CONFIG_ENV_OVERWRITE
22 
23 #ifndef __ASSEMBLY__
24 extern unsigned long get_clock_freq(void);
25 #endif
26 /* Replace a call to get_clock_freq (after it is implemented)*/
27 #define CONFIG_SYS_CLK_FREQ	66666666
28 #define CONFIG_DDR_CLK_FREQ	CONFIG_SYS_CLK_FREQ
29 
30 #ifdef CONFIG_ATM
31 #define CONFIG_PQ_MDS_PIB
32 #define CONFIG_PQ_MDS_PIB_ATM
33 #endif
34 
35 /*
36  * These can be toggled for performance analysis, otherwise use default.
37  */
38 #define CONFIG_L2_CACHE				/* toggle L2 cache	*/
39 #define CONFIG_BTB				/* toggle branch predition */
40 
41 #ifndef CONFIG_SYS_MONITOR_BASE
42 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
43 #endif
44 
45 /*
46  * Only possible on E500 Version 2 or newer cores.
47  */
48 #define CONFIG_ENABLE_36BIT_PHYS	1
49 
50 #define CONFIG_HWCONFIG
51 
52 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
53 #define CONFIG_SYS_MEMTEST_END		0x00400000
54 
55 /*
56  * Config the L2 Cache as L2 SRAM
57  */
58 #define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
59 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
60 #define CONFIG_SYS_L2_SIZE		(512 << 10)
61 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
62 
63 #define CONFIG_SYS_CCSRBAR		0xe0000000
64 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
65 
66 #if defined(CONFIG_NAND_SPL)
67 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
68 #endif
69 
70 /* DDR Setup */
71 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
72 #define CONFIG_DDR_SPD
73 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
74 
75 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
76 
77 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
78 					/* DDR is system memory*/
79 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
80 
81 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
82 #define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
83 
84 /* I2C addresses of SPD EEPROMs */
85 #define SPD_EEPROM_ADDRESS    0x51    /* CTLR 0 DIMM 0 */
86 
87 /* These are used when DDR doesn't use SPD.  */
88 #define CONFIG_SYS_SDRAM_SIZE           1024		/* DDR is 1024MB */
89 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
90 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
91 #define CONFIG_SYS_DDR_TIMING_3         0x00020000
92 #define CONFIG_SYS_DDR_TIMING_0         0x00330004
93 #define CONFIG_SYS_DDR_TIMING_1         0x6F6B4644
94 #define CONFIG_SYS_DDR_TIMING_2         0x002888D0
95 #define CONFIG_SYS_DDR_SDRAM_CFG	0x47000000
96 #define CONFIG_SYS_DDR_SDRAM_CFG_2	0x04401040
97 #define CONFIG_SYS_DDR_SDRAM_MODE	0x40401521
98 #define CONFIG_SYS_DDR_SDRAM_MODE_2	0x8000C000
99 #define CONFIG_SYS_DDR_SDRAM_INTERVAL	0x03E00000
100 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
101 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	0x01000000
102 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
103 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
104 #define CONFIG_SYS_DDR_ZQ_CNTL		0x89080600
105 #define CONFIG_SYS_DDR_WRLVL_CNTL	0x0655A604
106 #define CONFIG_SYS_DDR_CDR_1		0x80040000
107 #define CONFIG_SYS_DDR_CDR_2		0x00000000
108 #define CONFIG_SYS_DDR_OCD_CTRL         0x00000000
109 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
110 #define CONFIG_SYS_DDR_CONTROL          0xc7000000      /* Type = DDR3 */
111 #define CONFIG_SYS_DDR_CONTROL2         0x24400000
112 
113 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
114 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
115 #define CONFIG_SYS_DDR_SBE              0x00010000
116 
117 #undef CONFIG_CLOCKS_IN_MHZ
118 
119 /*
120  * Local Bus Definitions
121  */
122 
123 #define CONFIG_SYS_FLASH_BASE		0xfe000000	/* start of FLASH 32M */
124 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
125 
126 #define CONFIG_SYS_BCSR_BASE		0xf8000000
127 #define CONFIG_SYS_BCSR_BASE_PHYS	CONFIG_SYS_BCSR_BASE
128 
129 /*Chip select 0 - Flash*/
130 #define CONFIG_FLASH_BR_PRELIM		0xfe000801
131 #define	CONFIG_FLASH_OR_PRELIM		0xfe000ff7
132 
133 /*Chip select 1 - BCSR*/
134 #define CONFIG_SYS_BR1_PRELIM		0xf8000801
135 #define	CONFIG_SYS_OR1_PRELIM		0xffffe9f7
136 
137 /*Chip select 4 - PIB*/
138 #define CONFIG_SYS_BR4_PRELIM		0xf8008801
139 #define CONFIG_SYS_OR4_PRELIM		0xffffe9f7
140 
141 /*Chip select 5 - PIB*/
142 #define CONFIG_SYS_BR5_PRELIM		0xf8010801
143 #define CONFIG_SYS_OR5_PRELIM		0xffffe9f7
144 
145 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
146 #define CONFIG_SYS_MAX_FLASH_SECT	512	/* sectors per device */
147 #undef	CONFIG_SYS_FLASH_CHECKSUM
148 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
149 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
150 
151 #undef CONFIG_SYS_RAMBOOT
152 
153 #define CONFIG_SYS_FLASH_EMPTY_INFO
154 
155 /* Chip select 3 - NAND */
156 #ifndef CONFIG_NAND_SPL
157 #define CONFIG_SYS_NAND_BASE		0xFC000000
158 #else
159 #define CONFIG_SYS_NAND_BASE		0xFFF00000
160 #endif
161 
162 /* NAND boot: 4K NAND loader config */
163 #define CONFIG_SYS_NAND_SPL_SIZE	0x1000
164 #define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) - 0x2000)
165 #define CONFIG_SYS_NAND_U_BOOT_DST	(CONFIG_SYS_INIT_L2_ADDR)
166 #define CONFIG_SYS_NAND_U_BOOT_START \
167 	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
168 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(0)
169 #define CONFIG_SYS_NAND_U_BOOT_RELOC	(CONFIG_SYS_INIT_L2_END - 0x2000)
170 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
171 
172 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
173 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE, }
174 #define CONFIG_SYS_MAX_NAND_DEVICE	1
175 #define CONFIG_NAND_FSL_ELBC		1
176 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
177 #define CONFIG_SYS_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE_PHYS \
178 				| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
179 				| BR_PS_8	     /* Port Size = 8 bit */ \
180 				| BR_MS_FCM	     /* MSEL = FCM */ \
181 				| BR_V)		     /* valid */
182 #define CONFIG_SYS_NAND_OR_PRELIM	(0xFFFC0000	     /* length 256K */ \
183 				| OR_FCM_CSCT \
184 				| OR_FCM_CST \
185 				| OR_FCM_CHT \
186 				| OR_FCM_SCY_1 \
187 				| OR_FCM_TRLX \
188 				| OR_FCM_EHTR)
189 
190 #define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
191 #define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
192 #define CONFIG_SYS_BR3_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
193 #define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
194 
195 #define CONFIG_SYS_LBC_LCRR	0x00000004	/* LB clock ratio reg */
196 #define CONFIG_SYS_LBC_LBCR	0x00040000	/* LB config reg */
197 #define CONFIG_SYS_LBC_LSRT	0x20000000	/* LB sdram refresh timer */
198 #define CONFIG_SYS_LBC_MRTPR	0x00000000	/* LB refresh timer prescal*/
199 
200 #define CONFIG_SYS_INIT_RAM_LOCK	1
201 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000  /* Initial RAM address */
202 #define CONFIG_SYS_INIT_RAM_SIZE	0x4000	    /* Size of used area in RAM */
203 
204 #define CONFIG_SYS_GBL_DATA_OFFSET	\
205 			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
206 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
207 
208 #define CONFIG_SYS_MONITOR_LEN	(256 * 1024)	/* Reserve 256 kB for Mon */
209 #define CONFIG_SYS_MALLOC_LEN	(512 * 1024)	/* Reserved for malloc */
210 
211 /* Serial Port */
212 #define CONFIG_SYS_NS16550_SERIAL
213 #define CONFIG_SYS_NS16550_REG_SIZE    1
214 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
215 #ifdef CONFIG_NAND_SPL
216 #define CONFIG_NS16550_MIN_FUNCTIONS
217 #endif
218 
219 #define CONFIG_SYS_BAUDRATE_TABLE  \
220 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
221 
222 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
223 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
224 
225 /*
226  * I2C
227  */
228 #define CONFIG_SYS_I2C
229 #define CONFIG_SYS_I2C_FSL
230 #define CONFIG_SYS_FSL_I2C_SPEED	400000
231 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
232 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
233 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
234 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
235 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
236 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
237 
238 /*
239  * I2C2 EEPROM
240  */
241 #define CONFIG_ID_EEPROM
242 #ifdef CONFIG_ID_EEPROM
243 #define CONFIG_SYS_I2C_EEPROM_NXID
244 #endif
245 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52
246 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
247 #define CONFIG_SYS_EEPROM_BUS_NUM       1
248 
249 #define PLPPAR1_I2C_BIT_MASK		0x0000000F
250 #define PLPPAR1_I2C2_VAL		0x00000000
251 #define PLPPAR1_ESDHC_VAL		0x0000000A
252 #define PLPDIR1_I2C_BIT_MASK		0x0000000F
253 #define PLPDIR1_I2C2_VAL		0x0000000F
254 #define PLPDIR1_ESDHC_VAL		0x00000006
255 #define PLPPAR1_UART0_BIT_MASK		0x00000fc0
256 #define PLPPAR1_ESDHC_4BITS_VAL		0x00000a80
257 #define PLPDIR1_UART0_BIT_MASK		0x00000fc0
258 #define PLPDIR1_ESDHC_4BITS_VAL		0x00000a80
259 
260 /*
261  * General PCI
262  * Memory Addresses are mapped 1-1. I/O is mapped from 0
263  */
264 #define CONFIG_SYS_PCIE1_NAME		"Slot"
265 #define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
266 #define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
267 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
268 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
269 #define CONFIG_SYS_PCIE1_IO_VIRT	0xe2800000
270 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
271 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe2800000
272 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
273 
274 #define CONFIG_SYS_SRIO1_MEM_VIRT	0xC0000000
275 #define CONFIG_SYS_SRIO1_MEM_BUS	0xC0000000
276 #define CONFIG_SYS_SRIO1_MEM_PHYS	CONFIG_SYS_SRIO1_MEM_BUS
277 #define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */
278 
279 #ifdef CONFIG_QE
280 /*
281  * QE UEC ethernet configuration
282  */
283 #define CONFIG_SYS_UCC_RGMII_MODE	/* Set UCC work at RGMII by default */
284 #undef CONFIG_SYS_UCC_RMII_MODE		/* Set UCC work at RMII mode */
285 
286 #define CONFIG_MIIM_ADDRESS	(CONFIG_SYS_CCSRBAR + 0x82120)
287 #define CONFIG_UEC_ETH
288 #define CONFIG_ETHPRIME         "UEC0"
289 #define CONFIG_PHY_MODE_NEED_CHANGE
290 
291 #define CONFIG_UEC_ETH1         /* GETH1 */
292 #define CONFIG_HAS_ETH0
293 
294 #ifdef CONFIG_UEC_ETH1
295 #define CONFIG_SYS_UEC1_UCC_NUM        0       /* UCC1 */
296 #define CONFIG_SYS_UEC1_RX_CLK         QE_CLK_NONE
297 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
298 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK12
299 #define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
300 #define CONFIG_SYS_UEC1_PHY_ADDR       7
301 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
302 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
303 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
304 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK16	/* CLK16 for RMII */
305 #define CONFIG_SYS_UEC1_ETH_TYPE       FAST_ETH
306 #define CONFIG_SYS_UEC1_PHY_ADDR       8	/* 0x8 for RMII */
307 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
308 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
309 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
310 #endif /* CONFIG_UEC_ETH1 */
311 
312 #define CONFIG_UEC_ETH2         /* GETH2 */
313 #define CONFIG_HAS_ETH1
314 
315 #ifdef CONFIG_UEC_ETH2
316 #define CONFIG_SYS_UEC2_UCC_NUM        1       /* UCC2 */
317 #define CONFIG_SYS_UEC2_RX_CLK         QE_CLK_NONE
318 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
319 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK17
320 #define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
321 #define CONFIG_SYS_UEC2_PHY_ADDR       1
322 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
323 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
324 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
325 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK16	/* CLK 16 for RMII */
326 #define CONFIG_SYS_UEC2_ETH_TYPE       FAST_ETH
327 #define CONFIG_SYS_UEC2_PHY_ADDR       0x9	/* 0x9 for RMII */
328 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
329 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
330 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
331 #endif /* CONFIG_UEC_ETH2 */
332 
333 #define CONFIG_UEC_ETH3         /* GETH3 */
334 #define CONFIG_HAS_ETH2
335 
336 #ifdef CONFIG_UEC_ETH3
337 #define CONFIG_SYS_UEC3_UCC_NUM        2       /* UCC3 */
338 #define CONFIG_SYS_UEC3_RX_CLK         QE_CLK_NONE
339 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
340 #define CONFIG_SYS_UEC3_TX_CLK         QE_CLK12
341 #define CONFIG_SYS_UEC3_ETH_TYPE       GIGA_ETH
342 #define CONFIG_SYS_UEC3_PHY_ADDR       2
343 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
344 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
345 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
346 #define CONFIG_SYS_UEC3_TX_CLK		QE_CLK16 /* CLK_16 for RMII */
347 #define CONFIG_SYS_UEC3_ETH_TYPE	FAST_ETH
348 #define CONFIG_SYS_UEC3_PHY_ADDR	0xA     /* 0xA for RMII */
349 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
350 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
351 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
352 #endif /* CONFIG_UEC_ETH3 */
353 
354 #define CONFIG_UEC_ETH4         /* GETH4 */
355 #define CONFIG_HAS_ETH3
356 
357 #ifdef CONFIG_UEC_ETH4
358 #define CONFIG_SYS_UEC4_UCC_NUM        3       /* UCC4 */
359 #define CONFIG_SYS_UEC4_RX_CLK         QE_CLK_NONE
360 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
361 #define CONFIG_SYS_UEC4_TX_CLK         QE_CLK17
362 #define CONFIG_SYS_UEC4_ETH_TYPE       GIGA_ETH
363 #define CONFIG_SYS_UEC4_PHY_ADDR       3
364 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
365 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
366 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
367 #define CONFIG_SYS_UEC4_TX_CLK		QE_CLK16 /* CLK16 for RMII */
368 #define CONFIG_SYS_UEC4_ETH_TYPE	FAST_ETH
369 #define CONFIG_SYS_UEC4_PHY_ADDR	0xB     /* 0xB for RMII */
370 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
371 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
372 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
373 #endif /* CONFIG_UEC_ETH4 */
374 
375 #undef CONFIG_UEC_ETH6         /* GETH6 */
376 #define CONFIG_HAS_ETH5
377 
378 #ifdef CONFIG_UEC_ETH6
379 #define CONFIG_SYS_UEC6_UCC_NUM        5       /* UCC6 */
380 #define CONFIG_SYS_UEC6_RX_CLK         QE_CLK_NONE
381 #define CONFIG_SYS_UEC6_TX_CLK         QE_CLK_NONE
382 #define CONFIG_SYS_UEC6_ETH_TYPE       GIGA_ETH
383 #define CONFIG_SYS_UEC6_PHY_ADDR       4
384 #define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
385 #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
386 #endif /* CONFIG_UEC_ETH6 */
387 
388 #undef CONFIG_UEC_ETH8         /* GETH8 */
389 #define CONFIG_HAS_ETH7
390 
391 #ifdef CONFIG_UEC_ETH8
392 #define CONFIG_SYS_UEC8_UCC_NUM        7       /* UCC8 */
393 #define CONFIG_SYS_UEC8_RX_CLK         QE_CLK_NONE
394 #define CONFIG_SYS_UEC8_TX_CLK         QE_CLK_NONE
395 #define CONFIG_SYS_UEC8_ETH_TYPE       GIGA_ETH
396 #define CONFIG_SYS_UEC8_PHY_ADDR       6
397 #define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
398 #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
399 #endif /* CONFIG_UEC_ETH8 */
400 
401 #endif /* CONFIG_QE */
402 
403 #if defined(CONFIG_PCI)
404 #undef CONFIG_EEPRO100
405 #undef CONFIG_TULIP
406 
407 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
408 
409 #endif	/* CONFIG_PCI */
410 
411 /*
412  * Environment
413  */
414 #if defined(CONFIG_SYS_RAMBOOT)
415 #else
416 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
417 #define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
418 #define CONFIG_ENV_SIZE		0x2000
419 #endif
420 
421 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
422 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
423 
424 /* QE microcode/firmware address */
425 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
426 #define CONFIG_SYS_QE_FW_ADDR	0xfff00000
427 
428 /*
429  * BOOTP options
430  */
431 #define CONFIG_BOOTP_BOOTFILESIZE
432 
433 #undef CONFIG_WATCHDOG			/* watchdog disabled */
434 
435 #ifdef CONFIG_MMC
436 #define CONFIG_FSL_ESDHC_PIN_MUX
437 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
438 #endif
439 
440 /*
441  * Miscellaneous configurable options
442  */
443 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
444 #if defined(CONFIG_CMD_KGDB)
445 #define CONFIG_SYS_CBSIZE	2048		/* Console I/O Buffer Size */
446 #else
447 #define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size */
448 #endif
449 #define CONFIG_SYS_MAXARGS	32		/* max number of command args */
450 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
451 						/* Boot Argument Buffer Size */
452 
453 /*
454  * For booting Linux, the board info and command line data
455  * have to be in the first 64 MB of memory, since this is
456  * the maximum mapped by the Linux kernel during initialization.
457  */
458 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20) /* Initial Memory map for Linux*/
459 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
460 
461 #if defined(CONFIG_CMD_KGDB)
462 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
463 #endif
464 
465 /*
466  * Environment Configuration
467  */
468 #define CONFIG_HOSTNAME "mpc8569mds"
469 #define CONFIG_ROOTPATH  "/nfsroot"
470 #define CONFIG_BOOTFILE  "your.uImage"
471 
472 #define CONFIG_SERVERIP  192.168.1.1
473 #define CONFIG_GATEWAYIP 192.168.1.1
474 #define CONFIG_NETMASK   255.255.255.0
475 
476 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
477 
478 #define	CONFIG_EXTRA_ENV_SETTINGS					\
479 	"netdev=eth0\0"							\
480 	"consoledev=ttyS0\0"						\
481 	"ramdiskaddr=600000\0"						\
482 	"ramdiskfile=your.ramdisk.u-boot\0"				\
483 	"fdtaddr=400000\0"						\
484 	"fdtfile=your.fdt.dtb\0"					\
485 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
486 	"nfsroot=$serverip:$rootpath "					\
487 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
488 	"console=$consoledev,$baudrate $othbootargs\0"			\
489 	"ramargs=setenv bootargs root=/dev/ram rw "			\
490 	"console=$consoledev,$baudrate $othbootargs\0"			\
491 
492 #define CONFIG_NFSBOOTCOMMAND						\
493 	"run nfsargs;"							\
494 	"tftp $loadaddr $bootfile;"					\
495 	"tftp $fdtaddr $fdtfile;"					\
496 	"bootm $loadaddr - $fdtaddr"
497 
498 #define CONFIG_RAMBOOTCOMMAND						\
499 	"run ramargs;"							\
500 	"tftp $ramdiskaddr $ramdiskfile;"				\
501 	"tftp $loadaddr $bootfile;"					\
502 	"bootm $loadaddr $ramdiskaddr"
503 
504 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
505 
506 #endif	/* __CONFIG_H */
507