1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2008 Extreme Engineering Solutions, Inc. 4 * Copyright 2007-2008 Freescale Semiconductor, Inc. 5 */ 6 7 /* 8 * xpedite537x board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* 14 * High Level Configuration Options 15 */ 16 #define CONFIG_SYS_BOARD_NAME "XPedite5370" 17 #define CONFIG_SYS_FORM_3U_VPX 1 18 19 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ 20 #define CONFIG_PCIE1 1 /* PCIE controller 1 */ 21 #define CONFIG_PCIE2 1 /* PCIE controller 2 */ 22 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 23 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 24 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 25 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 26 27 /* 28 * Multicore config 29 */ 30 #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */ 31 #define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */ 32 33 /* 34 * DDR config 35 */ 36 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 37 #define CONFIG_DDR_SPD 38 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 39 #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */ 40 #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */ 41 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ 42 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 43 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 44 #define CONFIG_DDR_ECC 45 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 46 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 47 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 48 #define CONFIG_VERY_BIG_RAM 49 50 #ifndef __ASSEMBLY__ 51 extern unsigned long get_board_sys_clk(unsigned long dummy); 52 extern unsigned long get_board_ddr_clk(unsigned long dummy); 53 #endif 54 55 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 56 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ 57 58 /* 59 * These can be toggled for performance analysis, otherwise use default. 60 */ 61 #define CONFIG_L2_CACHE /* toggle L2 cache */ 62 #define CONFIG_BTB /* toggle branch predition */ 63 #define CONFIG_ENABLE_36BIT_PHYS 1 64 65 #define CONFIG_SYS_CCSRBAR 0xef000000 66 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 67 68 /* 69 * Diagnostics 70 */ 71 #define CONFIG_SYS_MEMTEST_START 0x10000000 72 #define CONFIG_SYS_MEMTEST_END 0x20000000 73 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ 74 CONFIG_SYS_POST_I2C) 75 /* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */ 76 #define I2C_ADDR_IGNORE_LIST {0x50} 77 78 /* 79 * Memory map 80 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 81 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable 82 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable 83 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable 84 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable 85 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable 86 * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable 87 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable 88 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable 89 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable 90 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable 91 */ 92 93 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) 94 95 /* 96 * NAND flash configuration 97 */ 98 #define CONFIG_SYS_NAND_BASE 0xef800000 99 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ 100 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ 101 CONFIG_SYS_NAND_BASE2} 102 #define CONFIG_SYS_MAX_NAND_DEVICE 2 103 #define CONFIG_NAND_FSL_ELBC 104 105 /* 106 * NOR flash configuration 107 */ 108 #define CONFIG_SYS_FLASH_BASE 0xf8000000 109 #define CONFIG_SYS_FLASH_BASE2 0xf0000000 110 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 111 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 112 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 113 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 114 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 115 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ 116 {0xf7f40000, 0xc0000} } 117 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 118 119 /* 120 * Chip select configuration 121 */ 122 /* NOR Flash 0 on CS0 */ 123 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 124 BR_PS_16 | \ 125 BR_V) 126 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \ 127 OR_GPCM_CSNT | \ 128 OR_GPCM_XACS | \ 129 OR_GPCM_ACS_DIV2 | \ 130 OR_GPCM_SCY_8 | \ 131 OR_GPCM_TRLX | \ 132 OR_GPCM_EHTR | \ 133 OR_GPCM_EAD) 134 135 /* NOR Flash 1 on CS1 */ 136 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ 137 BR_PS_16 | \ 138 BR_V) 139 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 140 141 /* NAND flash on CS2 */ 142 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ 143 (2<<BR_DECC_SHIFT) | \ 144 BR_PS_8 | \ 145 BR_MS_FCM | \ 146 BR_V) 147 148 /* NAND flash on CS2 */ 149 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ 150 OR_FCM_PGS | \ 151 OR_FCM_CSCT | \ 152 OR_FCM_CST | \ 153 OR_FCM_CHT | \ 154 OR_FCM_SCY_1 | \ 155 OR_FCM_TRLX | \ 156 OR_FCM_EHTR) 157 158 /* NAND flash on CS3 */ 159 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ 160 (2<<BR_DECC_SHIFT) | \ 161 BR_PS_8 | \ 162 BR_MS_FCM | \ 163 BR_V) 164 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 165 166 /* 167 * Use L1 as initial stack 168 */ 169 #define CONFIG_SYS_INIT_RAM_LOCK 1 170 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 171 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 172 173 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 174 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 175 176 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 177 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 178 179 /* 180 * Serial Port 181 */ 182 #define CONFIG_SYS_NS16550_SERIAL 183 #define CONFIG_SYS_NS16550_REG_SIZE 1 184 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 185 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 186 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 187 #define CONFIG_SYS_BAUDRATE_TABLE \ 188 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 189 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 190 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 191 192 /* 193 * I2C 194 */ 195 #define CONFIG_SYS_I2C 196 #define CONFIG_SYS_I2C_FSL 197 #define CONFIG_SYS_FSL_I2C_SPEED 400000 198 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 199 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 200 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 201 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 202 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 203 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 204 205 /* PEX8518 slave I2C interface */ 206 #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70 207 208 /* I2C DS1631 temperature sensor */ 209 #define CONFIG_SYS_I2C_LM90_ADDR 0x4c 210 211 /* I2C EEPROM - AT24C128B */ 212 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 213 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 214 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ 215 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ 216 217 /* I2C RTC */ 218 #define CONFIG_RTC_M41T11 1 219 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 220 #define CONFIG_SYS_M41T11_BASE_YEAR 2000 221 222 /* GPIO */ 223 #define CONFIG_PCA953X 224 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 225 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c 226 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e 227 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f 228 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 229 230 /* 231 * PU = pulled high, PD = pulled low 232 * I = input, O = output, IO = input/output 233 */ 234 /* PCA9557 @ 0x18*/ 235 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ 236 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */ 237 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ 238 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */ 239 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ 240 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */ 241 #define CONFIG_SYS_PCA953X_C0_VCORE_VID2 0x40 /* VID2 of ISL6262 */ 242 #define CONFIG_SYS_PCA953X_C0_VCORE_VID3 0x80 /* VID3 of ISL6262 */ 243 244 /* PCA9557 @ 0x1c*/ 245 #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */ 246 #define CONFIG_SYS_PCA953X_XMC0_MVMR0 0x02 /* XMC EEPROM write protect */ 247 #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */ 248 #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */ 249 #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */ 250 #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */ 251 #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */ 252 #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */ 253 254 /* PCA9557 @ 0x1e*/ 255 #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */ 256 #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */ 257 #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */ 258 #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */ 259 #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */ 260 #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; tied to VPX P0.GAP */ 261 #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */ 262 263 /* PCA9557 @ 0x1f */ 264 #define CONFIG_SYS_PCA953X_GPIO_VPX0 0x01 /* PU */ 265 #define CONFIG_SYS_PCA953X_GPIO_VPX1 0x02 /* PU */ 266 #define CONFIG_SYS_PCA953X_GPIO_VPX2 0x04 /* PU */ 267 #define CONFIG_SYS_PCA953X_GPIO_VPX3 0x08 /* PU */ 268 #define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL 0x10 /* PD; I2C master source for FRU SEEPROM */ 269 270 /* 271 * General PCI 272 * Memory space is mapped 1-1, but I/O space must start from 0. 273 */ 274 /* PCIE1 - VPX P1 */ 275 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 276 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 277 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ 278 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 279 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 280 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 281 282 /* PCIE2 - PEX8518 */ 283 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 284 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 285 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 286 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 287 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000 288 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */ 289 290 /* 291 * Networking options 292 */ 293 #define CONFIG_TSEC_TBI 294 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 295 #define CONFIG_ETHPRIME "eTSEC2" 296 297 /* 298 * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force 299 * 1000mbps SGMII link 300 */ 301 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 302 TBICR_PHY_RESET \ 303 | TBICR_FULL_DUPLEX \ 304 | TBICR_SPEED1_SET \ 305 ) 306 307 #define CONFIG_TSEC1 1 308 #define CONFIG_TSEC1_NAME "eTSEC1" 309 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 310 #define TSEC1_PHY_ADDR 1 311 #define TSEC1_PHYIDX 0 312 #define CONFIG_HAS_ETH0 313 314 #define CONFIG_TSEC2 1 315 #define CONFIG_TSEC2_NAME "eTSEC2" 316 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 317 #define TSEC2_PHY_ADDR 2 318 #define TSEC2_PHYIDX 0 319 #define CONFIG_HAS_ETH1 320 321 /* 322 * Miscellaneous configurable options 323 */ 324 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 325 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ 326 #define CONFIG_PREBOOT /* enable preboot variable */ 327 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ 328 329 /* 330 * For booting Linux, the board info and command line data 331 * have to be in the first 16 MB of memory, since this is 332 * the maximum mapped by the Linux kernel during initialization. 333 */ 334 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 335 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 336 337 /* 338 * Environment Configuration 339 */ 340 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ 341 #define CONFIG_ENV_SIZE 0x8000 342 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) 343 344 /* 345 * Flash memory map: 346 * fff80000 - ffffffff Pri U-Boot (512 KB) 347 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) 348 * fff00000 - fff3ffff Pri FDT (256KB) 349 * fef00000 - ffefffff Pri OS image (16MB) 350 * f8000000 - feefffff Pri OS Use/Filesystem (111MB) 351 * 352 * f7f80000 - f7ffffff Sec U-Boot (512 KB) 353 * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB) 354 * f7f00000 - f7f3ffff Sec FDT (256KB) 355 * f6f00000 - f7efffff Sec OS image (16MB) 356 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) 357 */ 358 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000) 359 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000) 360 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000) 361 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000) 362 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) 363 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000) 364 365 #define CONFIG_PROG_UBOOT1 \ 366 "$download_cmd $loadaddr $ubootfile; " \ 367 "if test $? -eq 0; then " \ 368 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 369 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 370 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ 371 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 372 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ 373 "if test $? -ne 0; then " \ 374 "echo PROGRAM FAILED; " \ 375 "else; " \ 376 "echo PROGRAM SUCCEEDED; " \ 377 "fi; " \ 378 "else; " \ 379 "echo DOWNLOAD FAILED; " \ 380 "fi;" 381 382 #define CONFIG_PROG_UBOOT2 \ 383 "$download_cmd $loadaddr $ubootfile; " \ 384 "if test $? -eq 0; then " \ 385 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 386 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 387 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ 388 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 389 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ 390 "if test $? -ne 0; then " \ 391 "echo PROGRAM FAILED; " \ 392 "else; " \ 393 "echo PROGRAM SUCCEEDED; " \ 394 "fi; " \ 395 "else; " \ 396 "echo DOWNLOAD FAILED; " \ 397 "fi;" 398 399 #define CONFIG_BOOT_OS_NET \ 400 "$download_cmd $osaddr $osfile; " \ 401 "if test $? -eq 0; then " \ 402 "if test -n $fdtaddr; then " \ 403 "$download_cmd $fdtaddr $fdtfile; " \ 404 "if test $? -eq 0; then " \ 405 "bootm $osaddr - $fdtaddr; " \ 406 "else; " \ 407 "echo FDT DOWNLOAD FAILED; " \ 408 "fi; " \ 409 "else; " \ 410 "bootm $osaddr; " \ 411 "fi; " \ 412 "else; " \ 413 "echo OS DOWNLOAD FAILED; " \ 414 "fi;" 415 416 #define CONFIG_PROG_OS1 \ 417 "$download_cmd $osaddr $osfile; " \ 418 "if test $? -eq 0; then " \ 419 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ 420 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 421 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 422 "if test $? -ne 0; then " \ 423 "echo OS PROGRAM FAILED; " \ 424 "else; " \ 425 "echo OS PROGRAM SUCCEEDED; " \ 426 "fi; " \ 427 "else; " \ 428 "echo OS DOWNLOAD FAILED; " \ 429 "fi;" 430 431 #define CONFIG_PROG_OS2 \ 432 "$download_cmd $osaddr $osfile; " \ 433 "if test $? -eq 0; then " \ 434 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ 435 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 436 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 437 "if test $? -ne 0; then " \ 438 "echo OS PROGRAM FAILED; " \ 439 "else; " \ 440 "echo OS PROGRAM SUCCEEDED; " \ 441 "fi; " \ 442 "else; " \ 443 "echo OS DOWNLOAD FAILED; " \ 444 "fi;" 445 446 #define CONFIG_PROG_FDT1 \ 447 "$download_cmd $fdtaddr $fdtfile; " \ 448 "if test $? -eq 0; then " \ 449 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ 450 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 451 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 452 "if test $? -ne 0; then " \ 453 "echo FDT PROGRAM FAILED; " \ 454 "else; " \ 455 "echo FDT PROGRAM SUCCEEDED; " \ 456 "fi; " \ 457 "else; " \ 458 "echo FDT DOWNLOAD FAILED; " \ 459 "fi;" 460 461 #define CONFIG_PROG_FDT2 \ 462 "$download_cmd $fdtaddr $fdtfile; " \ 463 "if test $? -eq 0; then " \ 464 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ 465 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 466 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 467 "if test $? -ne 0; then " \ 468 "echo FDT PROGRAM FAILED; " \ 469 "else; " \ 470 "echo FDT PROGRAM SUCCEEDED; " \ 471 "fi; " \ 472 "else; " \ 473 "echo FDT DOWNLOAD FAILED; " \ 474 "fi;" 475 476 #define CONFIG_EXTRA_ENV_SETTINGS \ 477 "autoload=yes\0" \ 478 "download_cmd=tftp\0" \ 479 "console_args=console=ttyS0,115200\0" \ 480 "root_args=root=/dev/nfs rw\0" \ 481 "misc_args=ip=on\0" \ 482 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ 483 "bootfile=/home/user/file\0" \ 484 "osfile=/home/user/board.uImage\0" \ 485 "fdtfile=/home/user/board.dtb\0" \ 486 "ubootfile=/home/user/u-boot.bin\0" \ 487 "fdtaddr=0x1e00000\0" \ 488 "osaddr=0x1000000\0" \ 489 "loadaddr=0x1000000\0" \ 490 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ 491 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ 492 "prog_os1="CONFIG_PROG_OS1"\0" \ 493 "prog_os2="CONFIG_PROG_OS2"\0" \ 494 "prog_fdt1="CONFIG_PROG_FDT1"\0" \ 495 "prog_fdt2="CONFIG_PROG_FDT2"\0" \ 496 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ 497 "bootcmd_flash1=run set_bootargs; " \ 498 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ 499 "bootcmd_flash2=run set_bootargs; " \ 500 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ 501 "bootcmd=run bootcmd_flash1\0" 502 #endif /* __CONFIG_H */ 503