xref: /openbmc/u-boot/drivers/i2c/Kconfig (revision a1fee7bc) 
1#
2# I2C subsystem configuration
3#
4
5menu "I2C support"
6
7config DM_I2C
8	bool "Enable Driver Model for I2C drivers"
9	depends on DM
10	help
11	  Enable driver model for I2C. The I2C uclass interface: probe, read,
12	  write and speed, is implemented with the bus drivers operations,
13	  which provide methods for bus setting and data transfer. Each chip
14	  device (bus child) info is kept as parent platdata. The interface
15	  is defined in include/i2c.h. When i2c bus driver supports the i2c
16	  uclass, but the device drivers not, then DM_I2C_COMPAT config can
17	  be used as compatibility layer.
18
19config DM_I2C_COMPAT
20	bool "Enable I2C compatibility layer"
21	depends on DM
22	help
23	  Enable old-style I2C functions for compatibility with existing code.
24	  This option can be enabled as a temporary measure to avoid needing
25	  to convert all code for a board in a single commit. It should not
26	  be enabled for any board in an official release.
27
28config I2C_CROS_EC_TUNNEL
29	tristate "Chrome OS EC tunnel I2C bus"
30	depends on CROS_EC
31	help
32	  This provides an I2C bus that will tunnel i2c commands through to
33	  the other side of the Chrome OS EC to the I2C bus connected there.
34	  This will work whatever the interface used to talk to the EC (SPI,
35	  I2C or LPC). Some Chromebooks use this when the hardware design
36	  does not allow direct access to the main PMIC from the AP.
37
38config I2C_CROS_EC_LDO
39	bool "Provide access to LDOs on the Chrome OS EC"
40	depends on CROS_EC
41	---help---
42	On many Chromebooks the main PMIC is inaccessible to the AP. This is
43	often dealt with by using an I2C pass-through interface provided by
44	the EC. On some unfortunate models (e.g. Spring) the pass-through
45	is not available, and an LDO message is available instead. This
46	option enables a driver which provides very basic access to those
47	regulators, via the EC. We implement this as an I2C bus	which
48	emulates just the TPS65090 messages we know about. This is done to
49	avoid duplicating the logic in the TPS65090 regulator driver for
50	enabling/disabling an LDO.
51
52config I2C_SET_DEFAULT_BUS_NUM
53	bool "Set default I2C bus number"
54	depends on DM_I2C
55	help
56	  Set default number of I2C bus to be accessed. This option provides
57	  behaviour similar to old (i.e. pre DM) I2C bus driver.
58
59config I2C_DEFAULT_BUS_NUMBER
60	hex "I2C default bus number"
61	depends on I2C_SET_DEFAULT_BUS_NUM
62	default 0x0
63	help
64	  Number of default I2C bus to use
65
66config DM_I2C_GPIO
67	bool "Enable Driver Model for software emulated I2C bus driver"
68	depends on DM_I2C && DM_GPIO
69	help
70	  Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
71	  configuration is given by the device tree. Kernel-style device tree
72	  bindings are supported.
73	  Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
74
75config SYS_I2C_AT91
76	bool "Atmel I2C driver"
77	depends on DM_I2C && ARCH_AT91
78	help
79	  Add support for the Atmel I2C driver. A serious problem is that there
80	  is no documented way to issue repeated START conditions for more than
81	  two messages, as needed to support combined I2C messages. Use the
82	  i2c-gpio driver unless your system can cope with this limitation.
83	  Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt
84
85config SYS_I2C_FSL
86       bool "Freescale I2C bus driver"
87       depends on DM_I2C
88       help
89	  Add support for Freescale I2C busses as used on MPC8240, MPC8245, and
90	  MPC85xx processors.
91
92config SYS_I2C_CADENCE
93	tristate "Cadence I2C Controller"
94	depends on DM_I2C && (ARCH_ZYNQ || ARM64)
95	help
96	  Say yes here to select Cadence I2C Host Controller. This controller is
97	  e.g. used by Xilinx Zynq.
98
99config SYS_I2C_DAVINCI
100	bool "Davinci I2C Controller"
101	depends on (ARCH_KEYSTONE || ARCH_DAVINCI)
102	help
103	  Say yes here to add support for Davinci and Keystone I2C controller
104
105config SYS_I2C_DW
106	bool "Designware I2C Controller"
107	default n
108	help
109	  Say yes here to select the Designware I2C Host Controller. This
110	  controller is used in various SoCs, e.g. the ST SPEAr, Altera
111	  SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
112
113config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
114	bool "DW I2C Enable Status Register not supported"
115	depends on SYS_I2C_DW && (TARGET_SPEAR300 || TARGET_SPEAR310 || \
116		TARGET_SPEAR320 || TARGET_SPEAR600 || TARGET_X600)
117	default y
118	help
119	  Some versions of the Designware I2C controller do not support the
120	  enable status register. This config option can be enabled in such
121	  cases.
122
123config I2C_ASPEED_GLOBAL
124    bool
125
126config SYS_I2C_AST2600
127    bool "AST2600 I2C Controller"
128    depends on DM_I2C && ARCH_ASPEED
129    select I2C_ASPEED_GLOBAL
130    help
131      Say yes here to select AST2600 I2C Host Controller. The driver
132      support AST2600 I2C new mode register.
133
134config SYS_I2C_ASPEED
135	bool "Aspeed I2C Controller"
136	depends on DM_I2C && ARCH_ASPEED
137    select I2C_ASPEED_GLOBAL
138	help
139	  Say yes here to select Aspeed I2C Host Controller. The driver
140	  supports AST2500 and AST2400 controllers, but is very limited.
141	  Only single master mode is supported and only byte-by-byte
142	  synchronous reads and writes are supported, no Pool Buffers or DMA.
143
144config SYS_I2C_INTEL
145	bool "Intel I2C/SMBUS driver"
146	depends on DM_I2C
147	help
148	  Add support for the Intel SMBUS driver. So far this driver is just
149	  a stub which perhaps some basic init. There is no implementation of
150	  the I2C API meaning that any I2C operations will immediately fail
151	  for now.
152
153config SYS_I2C_IMX_LPI2C
154	bool "NXP i.MX LPI2C driver"
155	help
156	  Add support for the NXP i.MX LPI2C driver.
157
158config SYS_I2C_MESON
159	bool "Amlogic Meson I2C driver"
160	depends on DM_I2C && ARCH_MESON
161	help
162	  Add support for the I2C controller available in Amlogic Meson
163	  SoCs. The controller supports programmable bus speed including
164	  standard (100kbits/s) and fast (400kbit/s) speed and allows the
165	  software to define a flexible format of the bit streams. It has an
166	  internal buffer holding up to 8 bytes for transfers and supports
167	  both 7-bit and 10-bit addresses.
168
169config SYS_I2C_MXC
170	bool "NXP MXC I2C driver"
171	help
172	  Add support for the NXP I2C driver. This supports up to four bus
173	  channels and operating on standard mode up to 100 kbits/s and fast
174	  mode up to 400 kbits/s.
175
176if SYS_I2C_MXC
177config SYS_I2C_MXC_I2C1
178	bool "NXP MXC I2C1"
179	help
180	 Add support for NXP MXC I2C Controller 1.
181	 Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A
182
183config SYS_I2C_MXC_I2C2
184	bool "NXP MXC I2C2"
185	help
186	 Add support for NXP MXC I2C Controller 2.
187	 Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A
188
189config SYS_I2C_MXC_I2C3
190	bool "NXP MXC I2C3"
191	help
192	 Add support for NXP MXC I2C Controller 3.
193	 Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A
194
195config SYS_I2C_MXC_I2C4
196	bool "NXP MXC I2C4"
197	help
198	 Add support for NXP MXC I2C Controller 4.
199	 Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A
200
201config SYS_I2C_MXC_I2C5
202	bool "NXP MXC I2C5"
203	help
204	 Add support for NXP MXC I2C Controller 5.
205	 Required for SoCs which have I2C MXC controller 5 eg LX2160A
206
207config SYS_I2C_MXC_I2C6
208	bool "NXP MXC I2C6"
209	help
210	 Add support for NXP MXC I2C Controller 6.
211	 Required for SoCs which have I2C MXC controller 6 eg LX2160A
212
213config SYS_I2C_MXC_I2C7
214	bool "NXP MXC I2C7"
215	help
216	 Add support for NXP MXC I2C Controller 7.
217	 Required for SoCs which have I2C MXC controller 7 eg LX2160A
218
219config SYS_I2C_MXC_I2C8
220	bool "NXP MXC I2C8"
221	help
222	 Add support for NXP MXC I2C Controller 8.
223	 Required for SoCs which have I2C MXC controller 8 eg LX2160A
224endif
225
226if SYS_I2C_MXC_I2C1
227config SYS_MXC_I2C1_SPEED
228	int "I2C Channel 1 speed"
229	default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU
230	default 100000
231	help
232	 MXC I2C Channel 1 speed
233
234config SYS_MXC_I2C1_SLAVE
235	int "I2C1 Slave"
236	default 0
237	help
238	 MXC I2C1 Slave
239endif
240
241if SYS_I2C_MXC_I2C2
242config SYS_MXC_I2C2_SPEED
243	int "I2C Channel 2 speed"
244	default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU
245	default 100000
246	help
247	 MXC I2C Channel 2 speed
248
249config SYS_MXC_I2C2_SLAVE
250	int "I2C2 Slave"
251	default 0
252	help
253	 MXC I2C2 Slave
254endif
255
256if SYS_I2C_MXC_I2C3
257config SYS_MXC_I2C3_SPEED
258	int "I2C Channel 3 speed"
259	default 100000
260	help
261	 MXC I2C Channel 3 speed
262
263config SYS_MXC_I2C3_SLAVE
264	int "I2C3 Slave"
265	default 0
266	help
267	 MXC I2C3 Slave
268endif
269
270if SYS_I2C_MXC_I2C4
271config SYS_MXC_I2C4_SPEED
272	int "I2C Channel 4 speed"
273	default 100000
274	help
275	 MXC I2C Channel 4 speed
276
277config SYS_MXC_I2C4_SLAVE
278	int "I2C4 Slave"
279	default 0
280	help
281	 MXC I2C4 Slave
282endif
283
284if SYS_I2C_MXC_I2C5
285config SYS_MXC_I2C5_SPEED
286	int "I2C Channel 5 speed"
287	default 100000
288	help
289	 MXC I2C Channel 5 speed
290
291config SYS_MXC_I2C5_SLAVE
292	int "I2C5 Slave"
293	default 0
294	help
295	 MXC I2C5 Slave
296endif
297
298if SYS_I2C_MXC_I2C6
299config SYS_MXC_I2C6_SPEED
300	int "I2C Channel 6 speed"
301	default 100000
302	help
303	 MXC I2C Channel 6 speed
304
305config SYS_MXC_I2C6_SLAVE
306	int "I2C6 Slave"
307	default 0
308	help
309	 MXC I2C6 Slave
310endif
311
312if SYS_I2C_MXC_I2C7
313config SYS_MXC_I2C7_SPEED
314	int "I2C Channel 7 speed"
315	default 100000
316	help
317	 MXC I2C Channel 7 speed
318
319config SYS_MXC_I2C7_SLAVE
320	int "I2C7 Slave"
321	default 0
322	help
323	 MXC I2C7 Slave
324endif
325
326if SYS_I2C_MXC_I2C8
327config SYS_MXC_I2C8_SPEED
328	int "I2C Channel 8 speed"
329	default 100000
330	help
331	 MXC I2C Channel 8 speed
332
333config SYS_MXC_I2C8_SLAVE
334	int "I2C8 Slave"
335	default 0
336	help
337	 MXC I2C8 Slave
338endif
339
340config SYS_I2C_OMAP24XX
341	bool "TI OMAP2+ I2C driver"
342	depends on ARCH_OMAP2PLUS
343	help
344	  Add support for the OMAP2+ I2C driver.
345
346if SYS_I2C_OMAP24XX
347config SYS_OMAP24_I2C_SLAVE
348	int "I2C Slave addr channel 0"
349	default 1
350	help
351	  OMAP24xx I2C Slave address channel 0
352
353config SYS_OMAP24_I2C_SPEED
354	int "I2C Slave channel 0 speed"
355	default 100000
356	help
357	  OMAP24xx Slave speed channel 0
358endif
359
360config SYS_I2C_RCAR_I2C
361	bool "Renesas RCar I2C driver"
362	depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
363	help
364	  Support for Renesas RCar I2C controller.
365
366config SYS_I2C_RCAR_IIC
367	bool "Renesas RCar Gen3 IIC driver"
368	depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
369	help
370	  Support for Renesas RCar Gen3 IIC controller.
371
372config SYS_I2C_ROCKCHIP
373	bool "Rockchip I2C driver"
374	depends on DM_I2C
375	help
376	  Add support for the Rockchip I2C driver. This is used with various
377	  Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips
378	  have several I2C ports and all are provided, controlled by the
379	  device tree.
380
381config SYS_I2C_SANDBOX
382	bool "Sandbox I2C driver"
383	depends on SANDBOX && DM_I2C
384	help
385	  Enable I2C support for sandbox. This is an emulation of a real I2C
386	  bus. Devices can be attached to the bus using the device tree
387	  which specifies the driver to use.  See sandbox.dts as an example.
388
389config SYS_I2C_S3C24X0
390	bool "Samsung I2C driver"
391	depends on ARCH_EXYNOS4 && DM_I2C
392	help
393	  Support for Samsung I2C controller as Samsung SoCs.
394
395config SYS_I2C_STM32F7
396	bool "STMicroelectronics STM32F7 I2C support"
397	depends on (STM32F7 || STM32H7 || ARCH_STM32MP) && DM_I2C
398	help
399	  Enable this option to add support for STM32 I2C controller
400	  introduced with STM32F7/H7 SoCs. This I2C controller supports :
401	   _ Slave and master modes
402	   _ Multimaster capability
403	   _ Standard-mode (up to 100 kHz)
404	   _ Fast-mode (up to 400 kHz)
405	   _ Fast-mode Plus (up to 1 MHz)
406	   _ 7-bit and 10-bit addressing mode
407	   _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
408	   _ All 7-bit addresses acknowledge mode
409	   _ General call
410	   _ Programmable setup and hold times
411	   _ Easy to use event management
412	   _ Optional clock stretching
413	   _ Software reset
414
415config SYS_I2C_TEGRA
416	bool "NVIDIA Tegra internal I2C controller"
417	depends on TEGRA
418	help
419	  Support for NVIDIA I2C controller available in Tegra SoCs.
420
421config SYS_I2C_UNIPHIER
422	bool "UniPhier I2C driver"
423	depends on ARCH_UNIPHIER && DM_I2C
424	default y
425	help
426	  Support for UniPhier I2C controller driver.  This I2C controller
427	  is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs.
428
429config SYS_I2C_UNIPHIER_F
430	bool "UniPhier FIFO-builtin I2C driver"
431	depends on ARCH_UNIPHIER && DM_I2C
432	default y
433	help
434	  Support for UniPhier FIFO-builtin I2C controller driver.
435	  This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
436
437config SYS_I2C_VERSATILE
438	bool "Arm Ltd Versatile I2C bus driver"
439	depends on DM_I2C && (TARGET_VEXPRESS_CA15_TC2 || TARGET_VEXPRESS64_JUNO)
440	help
441	  Add support for the Arm Ltd Versatile Express I2C driver. The I2C host
442	  controller is present in the development boards manufactured by Arm Ltd.
443
444config SYS_I2C_MVTWSI
445	bool "Marvell I2C driver"
446	depends on DM_I2C
447	help
448	  Support for Marvell I2C controllers as used on the orion5x and
449	  kirkwood SoC families.
450
451config TEGRA186_BPMP_I2C
452	bool "Enable Tegra186 BPMP-based I2C driver"
453	depends on TEGRA186_BPMP
454	help
455	  Support for Tegra I2C controllers managed by the BPMP (Boot and
456	  Power Management Processor). On Tegra186, some I2C controllers are
457	  directly controlled by the main CPU, whereas others are controlled
458	  by the BPMP, and can only be accessed by the main CPU via IPC
459	  requests to the BPMP. This driver covers the latter case.
460
461config SYS_I2C_BUS_MAX
462	int "Max I2C busses"
463	depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA
464	default 2 if TI816X
465	default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE
466	default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X
467	default 5 if OMAP54XX
468	help
469	  Define the maximum number of available I2C buses.
470
471config SYS_I2C_XILINX_XIIC
472	bool "Xilinx AXI I2C driver"
473	depends on DM_I2C
474	help
475	  Support for Xilinx AXI I2C controller.
476
477config SYS_I2C_IHS
478        bool "gdsys IHS I2C driver"
479        depends on DM_I2C
480        help
481          Support for gdsys IHS I2C driver on FPGA bus.
482
483source "drivers/i2c/muxes/Kconfig"
484
485endmenu
486