xref: /openbmc/u-boot/include/configs/adp-ag101p.h (revision cf033e04)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2011 Andes Technology Corporation
4  * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
5  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
6  */
7 
8 #ifndef __CONFIG_H
9 #define __CONFIG_H
10 
11 #include <asm/arch-ag101/ag101.h>
12 
13 /*
14  * CPU and Board Configuration Options
15  */
16 #define CONFIG_USE_INTERRUPT
17 
18 #define CONFIG_SKIP_LOWLEVEL_INIT
19 
20 #define CONFIG_ARCH_MAP_SYSMEM
21 
22 #define CONFIG_BOOTP_SEND_HOSTNAME
23 #define CONFIG_BOOTP_SERVERIP
24 
25 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
26 #define CONFIG_MEM_REMAP
27 #endif
28 
29 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
30 #ifdef CONFIG_OF_CONTROL
31 #undef CONFIG_OF_SEPARATE
32 #define CONFIG_OF_EMBED
33 #endif
34 #endif
35 
36 /*
37  * Timer
38  */
39 #define CONFIG_SYS_CLK_FREQ	39062500
40 #define VERSION_CLOCK		CONFIG_SYS_CLK_FREQ
41 
42 /*
43  * Use Externel CLOCK or PCLK
44  */
45 #undef CONFIG_FTRTC010_EXTCLK
46 
47 #ifndef CONFIG_FTRTC010_EXTCLK
48 #define CONFIG_FTRTC010_PCLK
49 #endif
50 
51 #ifdef CONFIG_FTRTC010_EXTCLK
52 #define TIMER_CLOCK	32768			/* CONFIG_FTRTC010_EXTCLK */
53 #else
54 #define TIMER_CLOCK	CONFIG_SYS_HZ		/* CONFIG_FTRTC010_PCLK */
55 #endif
56 
57 #define TIMER_LOAD_VAL	0xffffffff
58 
59 /*
60  * Real Time Clock
61  */
62 #define CONFIG_RTC_FTRTC010
63 
64 /*
65  * Real Time Clock Divider
66  * RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
67  */
68 #define OSC_5MHZ			(5*1000000)
69 #define OSC_CLK				(4*OSC_5MHZ)
70 #define RTC_DIV_COUNT			(0.5)	/* Why?? */
71 
72 /*
73  * Serial console configuration
74  */
75 
76 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
77 #define CONFIG_SYS_NS16550_SERIAL
78 #define CONFIG_SYS_NS16550_COM1		CONFIG_FTUART010_02_BASE
79 #ifndef CONFIG_DM_SERIAL
80 #define CONFIG_SYS_NS16550_REG_SIZE	-4
81 #endif
82 #define CONFIG_SYS_NS16550_CLK		((18432000 * 20) / 25)	/* AG101P */
83 
84 /*
85  * Miscellaneous configurable options
86  */
87 
88 /*
89  * Size of malloc() pool
90  */
91 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
92 #define CONFIG_SYS_MALLOC_LEN		(512 << 10)
93 
94 /*
95  * AHB Controller configuration
96  */
97 #define CONFIG_FTAHBC020S
98 
99 #ifdef CONFIG_FTAHBC020S
100 #include <faraday/ftahbc020s.h>
101 
102 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
103 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE	0x100
104 
105 /*
106  * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
107  * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
108  * in C language.
109  */
110 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
111 	(FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
112 					FTAHBC020S_SLAVE_BSR_SIZE(0xb))
113 #endif
114 
115 /*
116  * Watchdog
117  */
118 #define CONFIG_FTWDT010_WATCHDOG
119 
120 /*
121  * PMU Power controller configuration
122  */
123 #define CONFIG_PMU
124 #define CONFIG_FTPMU010_POWER
125 
126 #ifdef CONFIG_FTPMU010_POWER
127 #include <faraday/ftpmu010.h>
128 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS		0x0E
129 #define CONFIG_SYS_FTPMU010_SDRAMHTC	(FTPMU010_SDRAMHTC_EBICTRL_DCSR  | \
130 					 FTPMU010_SDRAMHTC_EBIDATA_DCSR  | \
131 					 FTPMU010_SDRAMHTC_SDRAMCS_DCSR  | \
132 					 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
133 					 FTPMU010_SDRAMHTC_CKE_DCSR	 | \
134 					 FTPMU010_SDRAMHTC_DQM_DCSR	 | \
135 					 FTPMU010_SDRAMHTC_SDCLK_DCSR)
136 #endif
137 
138 /*
139  * SDRAM controller configuration
140  */
141 #define CONFIG_FTSDMC021
142 
143 #ifdef CONFIG_FTSDMC021
144 #include <faraday/ftsdmc021.h>
145 
146 #define CONFIG_SYS_FTSDMC021_TP1	(FTSDMC021_TP1_TRAS(2)	|	\
147 					 FTSDMC021_TP1_TRP(1)	|	\
148 					 FTSDMC021_TP1_TRCD(1)	|	\
149 					 FTSDMC021_TP1_TRF(3)	|	\
150 					 FTSDMC021_TP1_TWR(1)	|	\
151 					 FTSDMC021_TP1_TCL(2))
152 
153 #define CONFIG_SYS_FTSDMC021_TP2	(FTSDMC021_TP2_INI_PREC(4) |	\
154 					 FTSDMC021_TP2_INI_REFT(8) |	\
155 					 FTSDMC021_TP2_REF_INTV(0x180))
156 
157 /*
158  * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
159  * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
160  * C language.
161  */
162 #define CONFIG_SYS_FTSDMC021_CR1	(FTSDMC021_CR1_DDW(2)	 |	\
163 					 FTSDMC021_CR1_DSZ(3)	 |	\
164 					 FTSDMC021_CR1_MBW(2)	 |	\
165 					 FTSDMC021_CR1_BNKSIZE(6))
166 
167 #define CONFIG_SYS_FTSDMC021_CR2	(FTSDMC021_CR2_IPREC	 |	\
168 					 FTSDMC021_CR2_IREF	 |	\
169 					 FTSDMC021_CR2_ISMR)
170 
171 #define CONFIG_SYS_FTSDMC021_BANK0_BASE	CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
172 #define CONFIG_SYS_FTSDMC021_BANK0_BSR	(FTSDMC021_BANK_ENABLE	 |	\
173 					 CONFIG_SYS_FTSDMC021_BANK0_BASE)
174 
175 #define CONFIG_SYS_FTSDMC021_BANK1_BASE	\
176 	(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
177 #define CONFIG_SYS_FTSDMC021_BANK1_BSR	(FTSDMC021_BANK_ENABLE	 |	\
178 					 CONFIG_SYS_FTSDMC021_BANK1_BASE)
179 #endif
180 
181 /*
182  * Physical Memory Map
183  */
184 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
185 #define PHYS_SDRAM_0	0x00000000  /* SDRAM Bank #1 */
186 #else
187 #ifdef CONFIG_MEM_REMAP
188 #define PHYS_SDRAM_0	0x00000000	/* SDRAM Bank #1 */
189 #else
190 #define PHYS_SDRAM_0	0x80000000	/* SDRAM Bank #1 */
191 #endif
192 #endif
193 
194 #define PHYS_SDRAM_1 \
195 	(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)	/* SDRAM Bank #2 */
196 
197 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
198 #define PHYS_SDRAM_0_SIZE	0x20000000	/* 512 MB */
199 #define PHYS_SDRAM_1_SIZE	0x20000000	/* 512 MB */
200 #else
201 #ifdef CONFIG_MEM_REMAP
202 #define PHYS_SDRAM_0_SIZE	0x20000000	/* 512 MB */
203 #define PHYS_SDRAM_1_SIZE	0x20000000	/* 512 MB */
204 #else
205 #define PHYS_SDRAM_0_SIZE	0x08000000	/* 128 MB */
206 #define PHYS_SDRAM_1_SIZE	0x08000000	/* 128 MB */
207 #endif
208 #endif
209 
210 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_0
211 
212 #ifdef CONFIG_MEM_REMAP
213 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
214 					GENERATED_GBL_DATA_SIZE)
215 #else
216 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
217 					GENERATED_GBL_DATA_SIZE)
218 #endif /* CONFIG_MEM_REMAP */
219 
220 /*
221  * Load address and memory test area should agree with
222  * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
223  */
224 #define CONFIG_SYS_LOAD_ADDR		0x300000
225 
226 /* memtest works on 63 MB in DRAM */
227 #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_0
228 #define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_0 + 0x03F00000)
229 
230 /*
231  * Static memory controller configuration
232  */
233 #define CONFIG_FTSMC020
234 
235 #ifdef CONFIG_FTSMC020
236 #include <faraday/ftsmc020.h>
237 
238 #define CONFIG_SYS_FTSMC020_CONFIGS	{			\
239 	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },	\
240 	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
241 }
242 
243 #ifndef CONFIG_SKIP_LOWLEVEL_INIT	/* FLASH is on BANK 0 */
244 #define FTSMC020_BANK0_LOWLV_CONFIG	(FTSMC020_BANK_ENABLE	|	\
245 					 FTSMC020_BANK_SIZE_32M	|	\
246 					 FTSMC020_BANK_MBW_32)
247 
248 #define FTSMC020_BANK0_LOWLV_TIMING	(FTSMC020_TPR_RBE	|	\
249 					 FTSMC020_TPR_AST(1)	|	\
250 					 FTSMC020_TPR_CTW(1)	|	\
251 					 FTSMC020_TPR_ATI(1)	|	\
252 					 FTSMC020_TPR_AT2(1)	|	\
253 					 FTSMC020_TPR_WTC(1)	|	\
254 					 FTSMC020_TPR_AHT(1)	|	\
255 					 FTSMC020_TPR_TRNA(1))
256 #endif
257 
258 /*
259  * FLASH on ADP_AG101P is connected to BANK0
260  * Just disalbe the other BANK to avoid detection error.
261  */
262 #define FTSMC020_BANK0_CONFIG	(FTSMC020_BANK_ENABLE             |	\
263 				 FTSMC020_BANK_BASE(PHYS_FLASH_1) |	\
264 				 FTSMC020_BANK_SIZE_32M           |	\
265 				 FTSMC020_BANK_MBW_32)
266 
267 #define FTSMC020_BANK0_TIMING	(FTSMC020_TPR_AST(3)   |	\
268 				 FTSMC020_TPR_CTW(3)   |	\
269 				 FTSMC020_TPR_ATI(0xf) |	\
270 				 FTSMC020_TPR_AT2(3)   |	\
271 				 FTSMC020_TPR_WTC(3)   |	\
272 				 FTSMC020_TPR_AHT(3)   |	\
273 				 FTSMC020_TPR_TRNA(0xf))
274 
275 #define FTSMC020_BANK1_CONFIG	(0x00)
276 #define FTSMC020_BANK1_TIMING	(0x00)
277 #endif /* CONFIG_FTSMC020 */
278 
279 /*
280  * FLASH and environment organization
281  */
282 /* use CFI framework */
283 
284 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
285 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
286 
287 /* support JEDEC */
288 
289 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
290 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
291 #define PHYS_FLASH_1			0x80000000	/* BANK 0 */
292 #else
293 #ifdef CONFIG_MEM_REMAP
294 #define PHYS_FLASH_1			0x80000000	/* BANK 0 */
295 #else
296 #define PHYS_FLASH_1			0x00000000	/* BANK 0 */
297 #endif
298 #endif	/* CONFIG_MEM_REMAP */
299 
300 #define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
301 #define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, }
302 #define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
303 
304 #define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* TO for Flash Erase (ms) */
305 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* TO for Flash Write (ms) */
306 
307 /* max number of memory banks */
308 /*
309  * There are 4 banks supported for this Controller,
310  * but we have only 1 bank connected to flash on board
311  */
312 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
313 #define CONFIG_SYS_MAX_FLASH_BANKS	1
314 #endif
315 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
316 
317 /* max number of sectors on one chip */
318 #define CONFIG_FLASH_SECTOR_SIZE	(0x10000*2)
319 #define CONFIG_ENV_SECT_SIZE		CONFIG_FLASH_SECTOR_SIZE
320 #define CONFIG_SYS_MAX_FLASH_SECT	512
321 
322 /* environments */
323 #define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE + 0x140000)
324 #define CONFIG_ENV_SIZE			8192
325 #define CONFIG_ENV_OVERWRITE
326 
327 /*
328  * For booting Linux, the board info and command line data
329  * have to be in the first 16 MB of memory, since this is
330  * the maximum mapped by the Linux kernel during initialization.
331  */
332 
333 /* Initial Memory map for Linux*/
334 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)
335 /* Increase max gunzip size */
336 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)
337 
338 #endif	/* __CONFIG_H */
339