1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2009-2012 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * Corenet DS style board configuration file 8 */ 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include "../board/freescale/common/ics307_clk.h" 13 14 #ifdef CONFIG_RAMBOOT_PBL 15 #ifdef CONFIG_SECURE_BOOT 16 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 17 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 18 #ifdef CONFIG_NAND 19 #define CONFIG_RAMBOOT_NAND 20 #endif 21 #define CONFIG_BOOTSCRIPT_COPY_RAM 22 #else 23 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 25 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 26 #if defined(CONFIG_TARGET_P3041DS) 27 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg 28 #elif defined(CONFIG_TARGET_P4080DS) 29 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg 30 #elif defined(CONFIG_TARGET_P5020DS) 31 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg 32 #elif defined(CONFIG_TARGET_P5040DS) 33 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg 34 #endif 35 #endif 36 #endif 37 38 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 39 /* Set 1M boot space */ 40 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 42 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 43 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 44 #endif 45 46 /* High Level Configuration Options */ 47 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 48 49 #ifndef CONFIG_RESET_VECTOR_ADDRESS 50 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 51 #endif 52 53 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 54 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 55 #define CONFIG_PCIE1 /* PCIE controller 1 */ 56 #define CONFIG_PCIE2 /* PCIE controller 2 */ 57 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 58 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 59 60 #define CONFIG_ENV_OVERWRITE 61 62 #if defined(CONFIG_SPIFLASH) 63 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 64 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 65 #define CONFIG_ENV_SECT_SIZE 0x10000 66 #elif defined(CONFIG_SDCARD) 67 #define CONFIG_FSL_FIXED_MMC_LOCATION 68 #define CONFIG_SYS_MMC_ENV_DEV 0 69 #define CONFIG_ENV_SIZE 0x2000 70 #define CONFIG_ENV_OFFSET (512 * 1658) 71 #elif defined(CONFIG_NAND) 72 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 73 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 74 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 75 #define CONFIG_ENV_ADDR 0xffe20000 76 #define CONFIG_ENV_SIZE 0x2000 77 #elif defined(CONFIG_ENV_IS_NOWHERE) 78 #define CONFIG_ENV_SIZE 0x2000 79 #else 80 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 81 #define CONFIG_ENV_SIZE 0x2000 82 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 83 #endif 84 85 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 86 87 /* 88 * These can be toggled for performance analysis, otherwise use default. 89 */ 90 #define CONFIG_SYS_CACHE_STASHING 91 #define CONFIG_BACKSIDE_L2_CACHE 92 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 93 #define CONFIG_BTB /* toggle branch predition */ 94 #define CONFIG_DDR_ECC 95 #ifdef CONFIG_DDR_ECC 96 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 97 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 98 #endif 99 100 #define CONFIG_ENABLE_36BIT_PHYS 101 102 #ifdef CONFIG_PHYS_64BIT 103 #define CONFIG_ADDR_MAP 104 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 105 #endif 106 107 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 108 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 109 #define CONFIG_SYS_MEMTEST_END 0x00400000 110 111 /* 112 * Config the L3 Cache as L3 SRAM 113 */ 114 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 115 #ifdef CONFIG_PHYS_64BIT 116 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 117 #else 118 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 119 #endif 120 #define CONFIG_SYS_L3_SIZE (1024 << 10) 121 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 122 123 #ifdef CONFIG_PHYS_64BIT 124 #define CONFIG_SYS_DCSRBAR 0xf0000000 125 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 126 #endif 127 128 /* EEPROM */ 129 #define CONFIG_ID_EEPROM 130 #define CONFIG_SYS_I2C_EEPROM_NXID 131 #define CONFIG_SYS_EEPROM_BUS_NUM 0 132 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 133 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 134 135 /* 136 * DDR Setup 137 */ 138 #define CONFIG_VERY_BIG_RAM 139 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 140 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 141 142 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 143 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 144 145 #define CONFIG_DDR_SPD 146 147 #define CONFIG_SYS_SPD_BUS_NUM 1 148 #define SPD_EEPROM_ADDRESS1 0x51 149 #define SPD_EEPROM_ADDRESS2 0x52 150 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 151 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 152 153 /* 154 * Local Bus Definitions 155 */ 156 157 /* Set the local bus clock 1/8 of platform clock */ 158 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 159 160 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 161 #ifdef CONFIG_PHYS_64BIT 162 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 163 #else 164 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 165 #endif 166 167 #define CONFIG_SYS_FLASH_BR_PRELIM \ 168 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ 169 | BR_PS_16 | BR_V) 170 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 171 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 172 173 #define CONFIG_SYS_BR1_PRELIM \ 174 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 175 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 176 177 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 178 #ifdef CONFIG_PHYS_64BIT 179 #define PIXIS_BASE_PHYS 0xfffdf0000ull 180 #else 181 #define PIXIS_BASE_PHYS PIXIS_BASE 182 #endif 183 184 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 185 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 186 187 #define PIXIS_LBMAP_SWITCH 7 188 #define PIXIS_LBMAP_MASK 0xf0 189 #define PIXIS_LBMAP_SHIFT 4 190 #define PIXIS_LBMAP_ALTBANK 0x40 191 192 #define CONFIG_SYS_FLASH_QUIET_TEST 193 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 194 195 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 196 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 197 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 198 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 199 200 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 201 202 #if defined(CONFIG_RAMBOOT_PBL) 203 #define CONFIG_SYS_RAMBOOT 204 #endif 205 206 /* Nand Flash */ 207 #ifdef CONFIG_NAND_FSL_ELBC 208 #define CONFIG_SYS_NAND_BASE 0xffa00000 209 #ifdef CONFIG_PHYS_64BIT 210 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 211 #else 212 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 213 #endif 214 215 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 216 #define CONFIG_SYS_MAX_NAND_DEVICE 1 217 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 218 219 /* NAND flash config */ 220 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 221 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 222 | BR_PS_8 /* Port Size = 8 bit */ \ 223 | BR_MS_FCM /* MSEL = FCM */ \ 224 | BR_V) /* valid */ 225 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 226 | OR_FCM_PGS /* Large Page*/ \ 227 | OR_FCM_CSCT \ 228 | OR_FCM_CST \ 229 | OR_FCM_CHT \ 230 | OR_FCM_SCY_1 \ 231 | OR_FCM_TRLX \ 232 | OR_FCM_EHTR) 233 234 #ifdef CONFIG_NAND 235 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 236 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 237 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 238 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 239 #else 240 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 241 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 242 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 243 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 244 #endif 245 #else 246 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 247 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 248 #endif /* CONFIG_NAND_FSL_ELBC */ 249 250 #define CONFIG_SYS_FLASH_EMPTY_INFO 251 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 252 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 253 254 #define CONFIG_HWCONFIG 255 256 /* define to use L1 as initial stack */ 257 #define CONFIG_L1_INIT_RAM 258 #define CONFIG_SYS_INIT_RAM_LOCK 259 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 260 #ifdef CONFIG_PHYS_64BIT 261 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 262 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 263 /* The assembler doesn't like typecast */ 264 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 265 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 266 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 267 #else 268 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 269 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 270 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 271 #endif 272 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 273 274 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 275 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 276 277 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 278 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 279 280 /* Serial Port - controlled on board with jumper J8 281 * open - index 2 282 * shorted - index 1 283 */ 284 #define CONFIG_SYS_NS16550_SERIAL 285 #define CONFIG_SYS_NS16550_REG_SIZE 1 286 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 287 288 #define CONFIG_SYS_BAUDRATE_TABLE \ 289 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 290 291 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 292 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 293 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 294 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 295 296 /* I2C */ 297 #define CONFIG_SYS_I2C 298 #define CONFIG_SYS_I2C_FSL 299 #define CONFIG_SYS_FSL_I2C_SPEED 400000 300 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 301 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 302 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 303 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 304 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 305 306 /* 307 * RapidIO 308 */ 309 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 310 #ifdef CONFIG_PHYS_64BIT 311 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 312 #else 313 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 314 #endif 315 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 316 317 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 318 #ifdef CONFIG_PHYS_64BIT 319 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 320 #else 321 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 322 #endif 323 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 324 325 /* 326 * for slave u-boot IMAGE instored in master memory space, 327 * PHYS must be aligned based on the SIZE 328 */ 329 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 330 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 331 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 332 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 333 /* 334 * for slave UCODE and ENV instored in master memory space, 335 * PHYS must be aligned based on the SIZE 336 */ 337 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 338 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 339 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 340 341 /* slave core release by master*/ 342 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 343 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 344 345 /* 346 * SRIO_PCIE_BOOT - SLAVE 347 */ 348 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 349 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 350 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 351 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 352 #endif 353 354 /* 355 * eSPI - Enhanced SPI 356 */ 357 358 /* 359 * General PCI 360 * Memory space is mapped 1-1, but I/O space must start from 0. 361 */ 362 363 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 364 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 365 #ifdef CONFIG_PHYS_64BIT 366 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 367 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 368 #else 369 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 370 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 371 #endif 372 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 373 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 374 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 375 #ifdef CONFIG_PHYS_64BIT 376 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 377 #else 378 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 379 #endif 380 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 381 382 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 383 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 384 #ifdef CONFIG_PHYS_64BIT 385 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 386 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 387 #else 388 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 389 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 390 #endif 391 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 392 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 393 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 394 #ifdef CONFIG_PHYS_64BIT 395 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 396 #else 397 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 398 #endif 399 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 400 401 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 402 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 403 #ifdef CONFIG_PHYS_64BIT 404 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 405 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 406 #else 407 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 408 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 409 #endif 410 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 411 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 412 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 413 #ifdef CONFIG_PHYS_64BIT 414 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 415 #else 416 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 417 #endif 418 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 419 420 /* controller 4, Base address 203000 */ 421 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 422 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 423 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 424 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 425 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 426 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 427 428 /* Qman/Bman */ 429 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 430 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 431 #ifdef CONFIG_PHYS_64BIT 432 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 433 #else 434 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 435 #endif 436 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 437 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 438 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 439 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 440 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 441 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 442 CONFIG_SYS_BMAN_CENA_SIZE) 443 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 444 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 445 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 446 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 447 #ifdef CONFIG_PHYS_64BIT 448 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 449 #else 450 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 451 #endif 452 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 453 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 454 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 455 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 456 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 457 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 458 CONFIG_SYS_QMAN_CENA_SIZE) 459 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 460 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 461 462 #define CONFIG_SYS_DPAA_FMAN 463 #define CONFIG_SYS_DPAA_PME 464 /* Default address of microcode for the Linux Fman driver */ 465 #if defined(CONFIG_SPIFLASH) 466 /* 467 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 468 * env, so we got 0x110000. 469 */ 470 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 471 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 472 #elif defined(CONFIG_SDCARD) 473 /* 474 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 475 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 476 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 477 */ 478 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 479 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 480 #elif defined(CONFIG_NAND) 481 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 482 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 483 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 484 /* 485 * Slave has no ucode locally, it can fetch this from remote. When implementing 486 * in two corenet boards, slave's ucode could be stored in master's memory 487 * space, the address can be mapped from slave TLB->slave LAW-> 488 * slave SRIO or PCIE outbound window->master inbound window-> 489 * master LAW->the ucode address in master's memory space. 490 */ 491 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 492 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 493 #else 494 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 495 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 496 #endif 497 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 498 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 499 500 #ifdef CONFIG_SYS_DPAA_FMAN 501 #define CONFIG_FMAN_ENET 502 #define CONFIG_PHYLIB_10G 503 #define CONFIG_PHY_VITESSE 504 #define CONFIG_PHY_TERANETICS 505 #endif 506 507 #ifdef CONFIG_PCI 508 #define CONFIG_PCI_INDIRECT_BRIDGE 509 510 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 511 #endif /* CONFIG_PCI */ 512 513 /* SATA */ 514 #ifdef CONFIG_FSL_SATA_V2 515 #define CONFIG_SYS_SATA_MAX_DEVICE 2 516 #define CONFIG_SATA1 517 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 518 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 519 #define CONFIG_SATA2 520 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 521 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 522 523 #define CONFIG_LBA48 524 #endif 525 526 #ifdef CONFIG_FMAN_ENET 527 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 528 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 529 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 530 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 531 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 532 533 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 534 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 535 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 536 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 537 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 538 539 #define CONFIG_SYS_TBIPA_VALUE 8 540 #define CONFIG_ETHPRIME "FM1@DTSEC1" 541 #endif 542 543 /* 544 * Environment 545 */ 546 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 547 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 548 549 /* 550 * USB 551 */ 552 #define CONFIG_HAS_FSL_DR_USB 553 #define CONFIG_HAS_FSL_MPH_USB 554 555 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 556 #define CONFIG_USB_EHCI_FSL 557 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 558 #endif 559 560 #ifdef CONFIG_MMC 561 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 562 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 563 #endif 564 565 /* 566 * Miscellaneous configurable options 567 */ 568 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 569 570 /* 571 * For booting Linux, the board info and command line data 572 * have to be in the first 64 MB of memory, since this is 573 * the maximum mapped by the Linux kernel during initialization. 574 */ 575 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 576 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 577 578 #ifdef CONFIG_CMD_KGDB 579 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 580 #endif 581 582 /* 583 * Environment Configuration 584 */ 585 #define CONFIG_ROOTPATH "/opt/nfsroot" 586 #define CONFIG_BOOTFILE "uImage" 587 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 588 589 /* default location for tftp and bootm */ 590 #define CONFIG_LOADADDR 1000000 591 592 #ifdef CONFIG_TARGET_P4080DS 593 #define __USB_PHY_TYPE ulpi 594 #else 595 #define __USB_PHY_TYPE utmi 596 #endif 597 598 #define CONFIG_EXTRA_ENV_SETTINGS \ 599 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 600 "bank_intlv=cs0_cs1;" \ 601 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 602 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 603 "netdev=eth0\0" \ 604 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 605 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 606 "tftpflash=tftpboot $loadaddr $uboot && " \ 607 "protect off $ubootaddr +$filesize && " \ 608 "erase $ubootaddr +$filesize && " \ 609 "cp.b $loadaddr $ubootaddr $filesize && " \ 610 "protect on $ubootaddr +$filesize && " \ 611 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 612 "consoledev=ttyS0\0" \ 613 "ramdiskaddr=2000000\0" \ 614 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 615 "fdtaddr=1e00000\0" \ 616 "fdtfile=p4080ds/p4080ds.dtb\0" \ 617 "bdev=sda3\0" 618 619 #define CONFIG_HDBOOT \ 620 "setenv bootargs root=/dev/$bdev rw " \ 621 "console=$consoledev,$baudrate $othbootargs;" \ 622 "tftp $loadaddr $bootfile;" \ 623 "tftp $fdtaddr $fdtfile;" \ 624 "bootm $loadaddr - $fdtaddr" 625 626 #define CONFIG_NFSBOOTCOMMAND \ 627 "setenv bootargs root=/dev/nfs rw " \ 628 "nfsroot=$serverip:$rootpath " \ 629 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 630 "console=$consoledev,$baudrate $othbootargs;" \ 631 "tftp $loadaddr $bootfile;" \ 632 "tftp $fdtaddr $fdtfile;" \ 633 "bootm $loadaddr - $fdtaddr" 634 635 #define CONFIG_RAMBOOTCOMMAND \ 636 "setenv bootargs root=/dev/ram rw " \ 637 "console=$consoledev,$baudrate $othbootargs;" \ 638 "tftp $ramdiskaddr $ramdiskfile;" \ 639 "tftp $loadaddr $bootfile;" \ 640 "tftp $fdtaddr $fdtfile;" \ 641 "bootm $loadaddr $ramdiskaddr $fdtaddr" 642 643 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 644 645 #include <asm/fsl_secure_boot.h> 646 647 #endif /* __CONFIG_H */ 648