1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 4 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 5 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de> 6 * Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008. 7 */ 8 9/* 10 * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards 11 */ 12 13#include <asm-offsets.h> 14#include <config.h> 15#include <mpc83xx.h> 16#include <version.h> 17 18#define CONFIG_83XX 1 /* needed for Linux kernel header files*/ 19 20#include <ppc_asm.tmpl> 21#include <ppc_defs.h> 22 23#include <asm/cache.h> 24#include <asm/mmu.h> 25#include <asm/u-boot.h> 26 27/* We don't want the MMU yet. 28 */ 29#undef MSR_KERNEL 30 31/* 32 * Floating Point enable, Machine Check and Recoverable Interr. 33 */ 34#ifdef DEBUG 35#define MSR_KERNEL (MSR_FP|MSR_RI) 36#else 37#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) 38#endif 39 40#if defined(CONFIG_NAND_SPL) || \ 41 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)) 42#define MINIMAL_SPL 43#endif 44 45#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL) && \ 46 !defined(CONFIG_SYS_RAMBOOT) 47#define CONFIG_SYS_FLASHBOOT 48#endif 49 50/* 51 * Set up GOT: Global Offset Table 52 * 53 * Use r12 to access the GOT 54 */ 55 START_GOT 56 GOT_ENTRY(_GOT2_TABLE_) 57 GOT_ENTRY(__bss_start) 58 GOT_ENTRY(__bss_end) 59 60#ifndef MINIMAL_SPL 61 GOT_ENTRY(_FIXUP_TABLE_) 62 GOT_ENTRY(_start) 63 GOT_ENTRY(_start_of_vectors) 64 GOT_ENTRY(_end_of_vectors) 65 GOT_ENTRY(transfer_to_handler) 66#endif 67 END_GOT 68 69/* 70 * The Hard Reset Configuration Word (HRCW) table is in the first 64 71 * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8 72 * times so the processor can fetch it out of flash whether the flash 73 * is 8, 16, 32, or 64 bits wide (hardware trickery). 74 */ 75 .text 76#define _HRCW_TABLE_ENTRY(w) \ 77 .fill 8,1,(((w)>>24)&0xff); \ 78 .fill 8,1,(((w)>>16)&0xff); \ 79 .fill 8,1,(((w)>> 8)&0xff); \ 80 .fill 8,1,(((w) )&0xff) 81 82 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW) 83 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH) 84 85/* 86 * Magic number and version string - put it after the HRCW since it 87 * cannot be first in flash like it is in many other processors. 88 */ 89 .long 0x27051956 /* U-Boot Magic Number */ 90 91 .globl version_string 92version_string: 93 .ascii U_BOOT_VERSION_STRING, "\0" 94 95 .align 2 96 97 .globl enable_addr_trans 98enable_addr_trans: 99 /* enable address translation */ 100 mfmsr r5 101 ori r5, r5, (MSR_IR | MSR_DR) 102 mtmsr r5 103 isync 104 blr 105 106 .globl disable_addr_trans 107disable_addr_trans: 108 /* disable address translation */ 109 mflr r4 110 mfmsr r3 111 andi. r0, r3, (MSR_IR | MSR_DR) 112 beqlr 113 andc r3, r3, r0 114 mtspr SRR0, r4 115 mtspr SRR1, r3 116 rfi 117 118 .globl ppcDWstore 119ppcDWstore: 120 lfd 1, 0(r4) 121 stfd 1, 0(r3) 122 blr 123 124 .globl ppcDWload 125ppcDWload: 126 lfd 1, 0(r3) 127 stfd 1, 0(r4) 128 blr 129 130#ifndef CONFIG_DEFAULT_IMMR 131#error CONFIG_DEFAULT_IMMR must be defined 132#endif /* CONFIG_DEFAULT_IMMR */ 133#ifndef CONFIG_SYS_IMMR 134#define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR 135#endif /* CONFIG_SYS_IMMR */ 136 137/* 138 * After configuration, a system reset exception is executed using the 139 * vector at offset 0x100 relative to the base set by MSR[IP]. If 140 * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the 141 * base address is 0xfff00000. In the case of a Power On Reset or Hard 142 * Reset, the value of MSR[IP] is determined by the CIP field in the 143 * HRCW. 144 * 145 * Other bits in the HRCW set up the Base Address and Port Size in BR0. 146 * This determines the location of the boot ROM (flash or EPROM) in the 147 * processor's address space at boot time. As long as the HRCW is set up 148 * so that we eventually end up executing the code below when the 149 * processor executes the reset exception, the actual values used should 150 * not matter. 151 * 152 * Once we have got here, the address mask in OR0 is cleared so that the 153 * bottom 32K of the boot ROM is effectively repeated all throughout the 154 * processor's address space, after which we can jump to the absolute 155 * address at which the boot ROM was linked at compile time, and proceed 156 * to initialise the memory controller without worrying if the rug will 157 * be pulled out from under us, so to speak (it will be fine as long as 158 * we configure BR0 with the same boot ROM link address). 159 */ 160 . = EXC_OFF_SYS_RESET 161 162 .globl _start 163_start: /* time t 0 */ 164 lis r4, CONFIG_DEFAULT_IMMR@h 165 nop 166 167 mfmsr r5 /* save msr contents */ 168 169 /* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */ 170 bl 1f 1711: mflr r7 172 173 lis r3, CONFIG_SYS_IMMR@h 174 ori r3, r3, CONFIG_SYS_IMMR@l 175 176 lwz r6, IMMRBAR(r4) 177 isync 178 179 stw r3, IMMRBAR(r4) 180 lwz r6, 0(r7) /* Arbitrary external load */ 181 isync 182 183 lwz r6, IMMRBAR(r3) 184 isync 185 186 /* Initialise the E300 processor core */ 187 /*------------------------------------------*/ 188 189#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MPC83XX_WAIT_FOR_NAND)) || \ 190 defined(CONFIG_NAND_SPL) 191 /* The FCM begins execution after only the first page 192 * is loaded. Wait for the rest before branching 193 * to another flash page. 194 */ 1951: lwz r6, 0x50b0(r3) 196 andi. r6, r6, 1 197 beq 1b 198#endif 199 200 bl init_e300_core 201 202#ifdef CONFIG_SYS_FLASHBOOT 203 204 /* Inflate flash location so it appears everywhere, calculate */ 205 /* the absolute address in final location of the FLASH, jump */ 206 /* there and deflate the flash size back to minimal size */ 207 /*------------------------------------------------------------*/ 208 bl map_flash_by_law1 209 lis r4, (CONFIG_SYS_MONITOR_BASE)@h 210 ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l 211 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET 212 mtlr r5 213 blr 214in_flash: 215#if 1 /* Remapping flash with LAW0. */ 216 bl remap_flash_by_law0 217#endif 218#endif /* CONFIG_SYS_FLASHBOOT */ 219 220 /* setup the bats */ 221 bl setup_bats 222 sync 223 224 /* 225 * Cache must be enabled here for stack-in-cache trick. 226 * This means we need to enable the BATS. 227 * This means: 228 * 1) for the EVB, original gt regs need to be mapped 229 * 2) need to have an IBAT for the 0xf region, 230 * we are running there! 231 * Cache should be turned on after BATs, since by default 232 * everything is write-through. 233 * The init-mem BAT can be reused after reloc. The old 234 * gt-regs BAT can be reused after board_init_f calls 235 * board_early_init_f (EVB only). 236 */ 237 /* enable address translation */ 238 bl enable_addr_trans 239 sync 240 241 /* enable the data cache */ 242 bl dcache_enable 243 sync 244#ifdef CONFIG_SYS_INIT_RAM_LOCK 245 bl lock_ram_in_cache 246 sync 247#endif 248 249 /* set up the stack pointer in our newly created 250 * cache-ram; use r3 to keep the new SP for now to 251 * avoid overiding the SP it uselessly */ 252 lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h 253 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l 254 255 /* r4 = end of GD area */ 256 addi r4, r3, GENERATED_GBL_DATA_SIZE 257 258 /* Zero GD area */ 259 li r0, 0 2601: 261 subi r4, r4, 1 262 stb r0, 0(r4) 263 cmplw r3, r4 264 bne 1b 265 266#if CONFIG_VAL(SYS_MALLOC_F_LEN) 267 268#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE 269#error "SYS_MALLOC_F_LEN too large to fit into initial RAM." 270#endif 271 272 /* r3 = new stack pointer / pre-reloc malloc area */ 273 subi r3, r3, CONFIG_VAL(SYS_MALLOC_F_LEN) 274 275 /* Set pointer to pre-reloc malloc area in GD */ 276 stw r3, GD_MALLOC_BASE(r4) 277#endif 278 li r0, 0 /* Make room for stack frame header and */ 279 stwu r0, -4(r3) /* clear final stack frame so that */ 280 stwu r0, -4(r3) /* stack backtraces terminate cleanly */ 281 282 /* Finally, actually set SP */ 283 mr r1, r3 284 285 /* let the C-code set up the rest */ 286 /* */ 287 /* Be careful to keep code relocatable & stack humble */ 288 /*------------------------------------------------------*/ 289 290 GET_GOT /* initialize GOT access */ 291 /* Needed for -msingle-pic-base */ 292 bl _GLOBAL_OFFSET_TABLE_@local-4 293 mflr r30 294 295 /* r3: IMMR */ 296 lis r3, CONFIG_SYS_IMMR@h 297 /* run low-level CPU init code (in Flash)*/ 298 bl cpu_init_f 299 300 /* run 1st part of board init code (in Flash)*/ 301 li r3, 0 /* clear boot_flag for calling board_init_f */ 302 bl board_init_f 303 304 /* NOTREACHED - board_init_f() does not return */ 305 306#ifndef MINIMAL_SPL 307/* 308 * Vector Table 309 */ 310 311 .globl _start_of_vectors 312_start_of_vectors: 313 314/* Machine check */ 315 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) 316 317/* Data Storage exception. */ 318 STD_EXCEPTION(0x300, DataStorage, UnknownException) 319 320/* Instruction Storage exception. */ 321 STD_EXCEPTION(0x400, InstStorage, UnknownException) 322 323/* External Interrupt exception. */ 324#ifndef FIXME 325 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) 326#endif 327 328/* Alignment exception. */ 329 . = 0x600 330Alignment: 331 EXCEPTION_PROLOG(SRR0, SRR1) 332 mfspr r4,DAR 333 stw r4,_DAR(r21) 334 mfspr r5,DSISR 335 stw r5,_DSISR(r21) 336 addi r3,r1,STACK_FRAME_OVERHEAD 337 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) 338 339/* Program check exception */ 340 . = 0x700 341ProgramCheck: 342 EXCEPTION_PROLOG(SRR0, SRR1) 343 addi r3,r1,STACK_FRAME_OVERHEAD 344 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, 345 MSR_KERNEL, COPY_EE) 346 347 STD_EXCEPTION(0x800, FPUnavailable, UnknownException) 348 349 /* I guess we could implement decrementer, and may have 350 * to someday for timekeeping. 351 */ 352 STD_EXCEPTION(0x900, Decrementer, timer_interrupt) 353 354 STD_EXCEPTION(0xa00, Trap_0a, UnknownException) 355 STD_EXCEPTION(0xb00, Trap_0b, UnknownException) 356 STD_EXCEPTION(0xc00, SystemCall, UnknownException) 357 STD_EXCEPTION(0xd00, SingleStep, UnknownException) 358 359 STD_EXCEPTION(0xe00, Trap_0e, UnknownException) 360 STD_EXCEPTION(0xf00, Trap_0f, UnknownException) 361 362 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) 363 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) 364 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) 365#ifdef DEBUG 366 . = 0x1300 367 /* 368 * This exception occurs when the program counter matches the 369 * Instruction Address Breakpoint Register (IABR). 370 * 371 * I want the cpu to halt if this occurs so I can hunt around 372 * with the debugger and look at things. 373 * 374 * When DEBUG is defined, both machine check enable (in the MSR) 375 * and checkstop reset enable (in the reset mode register) are 376 * turned off and so a checkstop condition will result in the cpu 377 * halting. 378 * 379 * I force the cpu into a checkstop condition by putting an illegal 380 * instruction here (at least this is the theory). 381 * 382 * well - that didnt work, so just do an infinite loop! 383 */ 3841: b 1b 385#else 386 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException) 387#endif 388 STD_EXCEPTION(0x1400, SMI, UnknownException) 389 390 STD_EXCEPTION(0x1500, Trap_15, UnknownException) 391 STD_EXCEPTION(0x1600, Trap_16, UnknownException) 392 STD_EXCEPTION(0x1700, Trap_17, UnknownException) 393 STD_EXCEPTION(0x1800, Trap_18, UnknownException) 394 STD_EXCEPTION(0x1900, Trap_19, UnknownException) 395 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException) 396 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException) 397 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException) 398 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException) 399 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException) 400 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException) 401 STD_EXCEPTION(0x2000, Trap_20, UnknownException) 402 STD_EXCEPTION(0x2100, Trap_21, UnknownException) 403 STD_EXCEPTION(0x2200, Trap_22, UnknownException) 404 STD_EXCEPTION(0x2300, Trap_23, UnknownException) 405 STD_EXCEPTION(0x2400, Trap_24, UnknownException) 406 STD_EXCEPTION(0x2500, Trap_25, UnknownException) 407 STD_EXCEPTION(0x2600, Trap_26, UnknownException) 408 STD_EXCEPTION(0x2700, Trap_27, UnknownException) 409 STD_EXCEPTION(0x2800, Trap_28, UnknownException) 410 STD_EXCEPTION(0x2900, Trap_29, UnknownException) 411 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException) 412 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException) 413 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException) 414 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException) 415 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException) 416 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException) 417 418 419 .globl _end_of_vectors 420_end_of_vectors: 421 422 . = 0x3000 423 424/* 425 * This code finishes saving the registers to the exception frame 426 * and jumps to the appropriate handler for the exception. 427 * Register r21 is pointer into trap frame, r1 has new stack pointer. 428 */ 429 .globl transfer_to_handler 430transfer_to_handler: 431 stw r22,_NIP(r21) 432 lis r22,MSR_POW@h 433 andc r23,r23,r22 434 stw r23,_MSR(r21) 435 SAVE_GPR(7, r21) 436 SAVE_4GPRS(8, r21) 437 SAVE_8GPRS(12, r21) 438 SAVE_8GPRS(24, r21) 439 mflr r23 440 andi. r24,r23,0x3f00 /* get vector offset */ 441 stw r24,TRAP(r21) 442 li r22,0 443 stw r22,RESULT(r21) 444 lwz r24,0(r23) /* virtual address of handler */ 445 lwz r23,4(r23) /* where to go when done */ 446 mtspr SRR0,r24 447 mtspr SRR1,r20 448 mtlr r23 449 SYNC 450 rfi /* jump to handler, enable MMU */ 451 452int_return: 453 mfmsr r28 /* Disable interrupts */ 454 li r4,0 455 ori r4,r4,MSR_EE 456 andc r28,r28,r4 457 SYNC /* Some chip revs need this... */ 458 mtmsr r28 459 SYNC 460 lwz r2,_CTR(r1) 461 lwz r0,_LINK(r1) 462 mtctr r2 463 mtlr r0 464 lwz r2,_XER(r1) 465 lwz r0,_CCR(r1) 466 mtspr XER,r2 467 mtcrf 0xFF,r0 468 REST_10GPRS(3, r1) 469 REST_10GPRS(13, r1) 470 REST_8GPRS(23, r1) 471 REST_GPR(31, r1) 472 lwz r2,_NIP(r1) /* Restore environment */ 473 lwz r0,_MSR(r1) 474 mtspr SRR0,r2 475 mtspr SRR1,r0 476 lwz r0,GPR0(r1) 477 lwz r2,GPR2(r1) 478 lwz r1,GPR1(r1) 479 SYNC 480 rfi 481#endif /* !MINIMAL_SPL */ 482 483/* 484 * This code initialises the E300 processor core 485 * (conforms to PowerPC 603e spec) 486 * Note: expects original MSR contents to be in r5. 487 */ 488 .globl init_e300_core 489init_e300_core: /* time t 10 */ 490 /* Initialize machine status; enable machine check interrupt */ 491 /*-----------------------------------------------------------*/ 492 493 li r3, MSR_KERNEL /* Set ME and RI flags */ 494 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */ 495#ifdef DEBUG 496 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */ 497#endif 498 SYNC /* Some chip revs need this... */ 499 mtmsr r3 500 SYNC 501 mtspr SRR1, r3 /* Make SRR1 match MSR */ 502 503 504 lis r3, CONFIG_SYS_IMMR@h 505#if defined(CONFIG_WATCHDOG) 506 /* Initialise the Watchdog values and reset it (if req) */ 507 /*------------------------------------------------------*/ 508 lis r4, CONFIG_SYS_WATCHDOG_VALUE 509 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 510 stw r4, SWCRR(r3) 511 512 /* and reset it */ 513 514 li r4, 0x556C 515 sth r4, SWSRR@l(r3) 516 li r4, -0x55C7 517 sth r4, SWSRR@l(r3) 518#else 519 /* Disable Watchdog */ 520 /*-------------------*/ 521 lwz r4, SWCRR(r3) 522 /* Check to see if its enabled for disabling 523 once disabled by SW you can't re-enable */ 524 andi. r4, r4, 0x4 525 beq 1f 526 xor r4, r4, r4 527 stw r4, SWCRR(r3) 5281: 529#endif /* CONFIG_WATCHDOG */ 530 531#if defined(CONFIG_MASK_AER_AO) 532 /* Write the Arbiter Event Enable to mask Address Only traps. */ 533 /* This prevents the dcbz instruction from being trapped when */ 534 /* HID0_ABE Address Broadcast Enable is set and the MEMORY */ 535 /* COHERENCY bit is set in the WIMG bits, which is often */ 536 /* needed for PCI operation. */ 537 lwz r4, 0x0808(r3) 538 rlwinm r0, r4, 0, ~AER_AO 539 stw r0, 0x0808(r3) 540#endif /* CONFIG_MASK_AER_AO */ 541 542 /* Initialize the Hardware Implementation-dependent Registers */ 543 /* HID0 also contains cache control */ 544 /* - force invalidation of data and instruction caches */ 545 /*------------------------------------------------------*/ 546 547 lis r3, CONFIG_SYS_HID0_INIT@h 548 ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l 549 SYNC 550 mtspr HID0, r3 551 552 lis r3, CONFIG_SYS_HID0_FINAL@h 553 ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l 554 SYNC 555 mtspr HID0, r3 556 557 lis r3, CONFIG_SYS_HID2@h 558 ori r3, r3, CONFIG_SYS_HID2@l 559 SYNC 560 mtspr HID2, r3 561 562 /* Done! */ 563 /*------------------------------*/ 564 blr 565 566 /* setup_bats - set them up to some initial state */ 567 .globl setup_bats 568setup_bats: 569 addis r0, r0, 0x0000 570 571 /* IBAT 0 */ 572 addis r4, r0, CONFIG_SYS_IBAT0L@h 573 ori r4, r4, CONFIG_SYS_IBAT0L@l 574 addis r3, r0, CONFIG_SYS_IBAT0U@h 575 ori r3, r3, CONFIG_SYS_IBAT0U@l 576 mtspr IBAT0L, r4 577 mtspr IBAT0U, r3 578 579 /* DBAT 0 */ 580 addis r4, r0, CONFIG_SYS_DBAT0L@h 581 ori r4, r4, CONFIG_SYS_DBAT0L@l 582 addis r3, r0, CONFIG_SYS_DBAT0U@h 583 ori r3, r3, CONFIG_SYS_DBAT0U@l 584 mtspr DBAT0L, r4 585 mtspr DBAT0U, r3 586 587 /* IBAT 1 */ 588 addis r4, r0, CONFIG_SYS_IBAT1L@h 589 ori r4, r4, CONFIG_SYS_IBAT1L@l 590 addis r3, r0, CONFIG_SYS_IBAT1U@h 591 ori r3, r3, CONFIG_SYS_IBAT1U@l 592 mtspr IBAT1L, r4 593 mtspr IBAT1U, r3 594 595 /* DBAT 1 */ 596 addis r4, r0, CONFIG_SYS_DBAT1L@h 597 ori r4, r4, CONFIG_SYS_DBAT1L@l 598 addis r3, r0, CONFIG_SYS_DBAT1U@h 599 ori r3, r3, CONFIG_SYS_DBAT1U@l 600 mtspr DBAT1L, r4 601 mtspr DBAT1U, r3 602 603 /* IBAT 2 */ 604 addis r4, r0, CONFIG_SYS_IBAT2L@h 605 ori r4, r4, CONFIG_SYS_IBAT2L@l 606 addis r3, r0, CONFIG_SYS_IBAT2U@h 607 ori r3, r3, CONFIG_SYS_IBAT2U@l 608 mtspr IBAT2L, r4 609 mtspr IBAT2U, r3 610 611 /* DBAT 2 */ 612 addis r4, r0, CONFIG_SYS_DBAT2L@h 613 ori r4, r4, CONFIG_SYS_DBAT2L@l 614 addis r3, r0, CONFIG_SYS_DBAT2U@h 615 ori r3, r3, CONFIG_SYS_DBAT2U@l 616 mtspr DBAT2L, r4 617 mtspr DBAT2U, r3 618 619 /* IBAT 3 */ 620 addis r4, r0, CONFIG_SYS_IBAT3L@h 621 ori r4, r4, CONFIG_SYS_IBAT3L@l 622 addis r3, r0, CONFIG_SYS_IBAT3U@h 623 ori r3, r3, CONFIG_SYS_IBAT3U@l 624 mtspr IBAT3L, r4 625 mtspr IBAT3U, r3 626 627 /* DBAT 3 */ 628 addis r4, r0, CONFIG_SYS_DBAT3L@h 629 ori r4, r4, CONFIG_SYS_DBAT3L@l 630 addis r3, r0, CONFIG_SYS_DBAT3U@h 631 ori r3, r3, CONFIG_SYS_DBAT3U@l 632 mtspr DBAT3L, r4 633 mtspr DBAT3U, r3 634 635#ifdef CONFIG_HIGH_BATS 636 /* IBAT 4 */ 637 addis r4, r0, CONFIG_SYS_IBAT4L@h 638 ori r4, r4, CONFIG_SYS_IBAT4L@l 639 addis r3, r0, CONFIG_SYS_IBAT4U@h 640 ori r3, r3, CONFIG_SYS_IBAT4U@l 641 mtspr IBAT4L, r4 642 mtspr IBAT4U, r3 643 644 /* DBAT 4 */ 645 addis r4, r0, CONFIG_SYS_DBAT4L@h 646 ori r4, r4, CONFIG_SYS_DBAT4L@l 647 addis r3, r0, CONFIG_SYS_DBAT4U@h 648 ori r3, r3, CONFIG_SYS_DBAT4U@l 649 mtspr DBAT4L, r4 650 mtspr DBAT4U, r3 651 652 /* IBAT 5 */ 653 addis r4, r0, CONFIG_SYS_IBAT5L@h 654 ori r4, r4, CONFIG_SYS_IBAT5L@l 655 addis r3, r0, CONFIG_SYS_IBAT5U@h 656 ori r3, r3, CONFIG_SYS_IBAT5U@l 657 mtspr IBAT5L, r4 658 mtspr IBAT5U, r3 659 660 /* DBAT 5 */ 661 addis r4, r0, CONFIG_SYS_DBAT5L@h 662 ori r4, r4, CONFIG_SYS_DBAT5L@l 663 addis r3, r0, CONFIG_SYS_DBAT5U@h 664 ori r3, r3, CONFIG_SYS_DBAT5U@l 665 mtspr DBAT5L, r4 666 mtspr DBAT5U, r3 667 668 /* IBAT 6 */ 669 addis r4, r0, CONFIG_SYS_IBAT6L@h 670 ori r4, r4, CONFIG_SYS_IBAT6L@l 671 addis r3, r0, CONFIG_SYS_IBAT6U@h 672 ori r3, r3, CONFIG_SYS_IBAT6U@l 673 mtspr IBAT6L, r4 674 mtspr IBAT6U, r3 675 676 /* DBAT 6 */ 677 addis r4, r0, CONFIG_SYS_DBAT6L@h 678 ori r4, r4, CONFIG_SYS_DBAT6L@l 679 addis r3, r0, CONFIG_SYS_DBAT6U@h 680 ori r3, r3, CONFIG_SYS_DBAT6U@l 681 mtspr DBAT6L, r4 682 mtspr DBAT6U, r3 683 684 /* IBAT 7 */ 685 addis r4, r0, CONFIG_SYS_IBAT7L@h 686 ori r4, r4, CONFIG_SYS_IBAT7L@l 687 addis r3, r0, CONFIG_SYS_IBAT7U@h 688 ori r3, r3, CONFIG_SYS_IBAT7U@l 689 mtspr IBAT7L, r4 690 mtspr IBAT7U, r3 691 692 /* DBAT 7 */ 693 addis r4, r0, CONFIG_SYS_DBAT7L@h 694 ori r4, r4, CONFIG_SYS_DBAT7L@l 695 addis r3, r0, CONFIG_SYS_DBAT7U@h 696 ori r3, r3, CONFIG_SYS_DBAT7U@l 697 mtspr DBAT7L, r4 698 mtspr DBAT7U, r3 699#endif 700 701 isync 702 703 /* invalidate all tlb's 704 * 705 * From the 603e User Manual: "The 603e provides the ability to 706 * invalidate a TLB entry. The TLB Invalidate Entry (tlbie) 707 * instruction invalidates the TLB entry indexed by the EA, and 708 * operates on both the instruction and data TLBs simultaneously 709 * invalidating four TLB entries (both sets in each TLB). The 710 * index corresponds to bits 15-19 of the EA. To invalidate all 711 * entries within both TLBs, 32 tlbie instructions should be 712 * issued, incrementing this field by one each time." 713 * 714 * "Note that the tlbia instruction is not implemented on the 715 * 603e." 716 * 717 * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 718 * incrementing by 0x1000 each time. The code below is sort of 719 * based on code in "flush_tlbs" from arch/powerpc/kernel/head.S 720 * 721 */ 722 lis r3, 0 723 lis r5, 2 724 7251: 726 tlbie r3 727 addi r3, r3, 0x1000 728 cmp 0, 0, r3, r5 729 blt 1b 730 731 blr 732 733/* Cache functions. 734 * 735 * Note: requires that all cache bits in 736 * HID0 are in the low half word. 737 */ 738#ifndef MINIMAL_SPL 739 .globl icache_enable 740icache_enable: 741 mfspr r3, HID0 742 ori r3, r3, HID0_ICE 743 li r4, HID0_ICFI|HID0_ILOCK 744 andc r3, r3, r4 745 ori r4, r3, HID0_ICFI 746 isync 747 mtspr HID0, r4 /* sets enable and invalidate, clears lock */ 748 isync 749 mtspr HID0, r3 /* clears invalidate */ 750 blr 751 752 .globl icache_disable 753icache_disable: 754 mfspr r3, HID0 755 lis r4, 0 756 ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK 757 andc r3, r3, r4 758 isync 759 mtspr HID0, r3 /* clears invalidate, enable and lock */ 760 blr 761 762 .globl icache_status 763icache_status: 764 mfspr r3, HID0 765 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 766 blr 767#endif /* !MINIMAL_SPL */ 768 769 .globl dcache_enable 770dcache_enable: 771 mfspr r3, HID0 772 li r5, HID0_DCFI|HID0_DLOCK 773 andc r3, r3, r5 774 ori r3, r3, HID0_DCE 775 sync 776 mtspr HID0, r3 /* enable, no invalidate */ 777 blr 778 779 .globl dcache_disable 780dcache_disable: 781 mflr r4 782 bl flush_dcache /* uses r3 and r5 */ 783 mfspr r3, HID0 784 li r5, HID0_DCE|HID0_DLOCK 785 andc r3, r3, r5 786 ori r5, r3, HID0_DCFI 787 sync 788 mtspr HID0, r5 /* sets invalidate, clears enable and lock */ 789 sync 790 mtspr HID0, r3 /* clears invalidate */ 791 mtlr r4 792 blr 793 794 .globl dcache_status 795dcache_status: 796 mfspr r3, HID0 797 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31 798 blr 799 800 .globl flush_dcache 801flush_dcache: 802 lis r3, 0 803 lis r5, CONFIG_SYS_CACHELINE_SIZE 8041: cmp 0, 1, r3, r5 805 bge 2f 806 lwz r5, 0(r3) 807 lis r5, CONFIG_SYS_CACHELINE_SIZE 808 addi r3, r3, 0x4 809 b 1b 8102: blr 811 812/*-------------------------------------------------------------------*/ 813 814/* 815 * void relocate_code (addr_sp, gd, addr_moni) 816 * 817 * This "function" does not return, instead it continues in RAM 818 * after relocating the monitor code. 819 * 820 * r3 = dest 821 * r4 = src 822 * r5 = length in bytes 823 * r6 = cachelinesize 824 */ 825 .globl relocate_code 826relocate_code: 827 mr r1, r3 /* Set new stack pointer */ 828 mr r9, r4 /* Save copy of Global Data pointer */ 829 mr r10, r5 /* Save copy of Destination Address */ 830 831 GET_GOT 832 mr r3, r5 /* Destination Address */ 833 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ 834 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l 835 lwz r5, GOT(__bss_start) 836 sub r5, r5, r4 837 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ 838 839 /* 840 * Fix GOT pointer: 841 * 842 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) 843 * + Destination Address 844 * 845 * Offset: 846 */ 847 sub r15, r10, r4 848 849 /* First our own GOT */ 850 add r12, r12, r15 851 /* then the one used by the C code */ 852 add r30, r30, r15 853 854 /* 855 * Now relocate code 856 */ 857 858 cmplw cr1,r3,r4 859 addi r0,r5,3 860 srwi. r0,r0,2 861 beq cr1,4f /* In place copy is not necessary */ 862 beq 7f /* Protect against 0 count */ 863 mtctr r0 864 bge cr1,2f 865 la r8,-4(r4) 866 la r7,-4(r3) 867 868 /* copy */ 8691: lwzu r0,4(r8) 870 stwu r0,4(r7) 871 bdnz 1b 872 873 addi r0,r5,3 874 srwi. r0,r0,2 875 mtctr r0 876 la r8,-4(r4) 877 la r7,-4(r3) 878 879 /* and compare */ 88020: lwzu r20,4(r8) 881 lwzu r21,4(r7) 882 xor. r22, r20, r21 883 bne 30f 884 bdnz 20b 885 b 4f 886 887 /* compare failed */ 88830: li r3, 0 889 blr 890 8912: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */ 892 add r8,r4,r0 893 add r7,r3,r0 8943: lwzu r0,-4(r8) 895 stwu r0,-4(r7) 896 bdnz 3b 897 898/* 899 * Now flush the cache: note that we must start from a cache aligned 900 * address. Otherwise we might miss one cache line. 901 */ 9024: cmpwi r6,0 903 add r5,r3,r5 904 beq 7f /* Always flush prefetch queue in any case */ 905 subi r0,r6,1 906 andc r3,r3,r0 907 mr r4,r3 9085: dcbst 0,r4 909 add r4,r4,r6 910 cmplw r4,r5 911 blt 5b 912 sync /* Wait for all dcbst to complete on bus */ 913 mr r4,r3 9146: icbi 0,r4 915 add r4,r4,r6 916 cmplw r4,r5 917 blt 6b 9187: sync /* Wait for all icbi to complete on bus */ 919 isync 920 921/* 922 * We are done. Do not return, instead branch to second part of board 923 * initialization, now running from RAM. 924 */ 925 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET 926 mtlr r0 927 blr 928 929in_ram: 930 931 /* 932 * Relocation Function, r12 point to got2+0x8000 933 * 934 * Adjust got2 pointers, no need to check for 0, this code 935 * already puts a few entries in the table. 936 */ 937 li r0,__got2_entries@sectoff@l 938 la r3,GOT(_GOT2_TABLE_) 939 lwz r11,GOT(_GOT2_TABLE_) 940 mtctr r0 941 sub r11,r3,r11 942 addi r3,r3,-4 9431: lwzu r0,4(r3) 944 cmpwi r0,0 945 beq- 2f 946 add r0,r0,r11 947 stw r0,0(r3) 9482: bdnz 1b 949 950#ifndef MINIMAL_SPL 951 /* 952 * Now adjust the fixups and the pointers to the fixups 953 * in case we need to move ourselves again. 954 */ 955 li r0,__fixup_entries@sectoff@l 956 lwz r3,GOT(_FIXUP_TABLE_) 957 cmpwi r0,0 958 mtctr r0 959 addi r3,r3,-4 960 beq 4f 9613: lwzu r4,4(r3) 962 lwzux r0,r4,r11 963 cmpwi r0,0 964 add r0,r0,r11 965 stw r4,0(r3) 966 beq- 5f 967 stw r0,0(r4) 9685: bdnz 3b 9694: 970#endif 971 972clear_bss: 973 /* 974 * Now clear BSS segment 975 */ 976 lwz r3,GOT(__bss_start) 977 lwz r4,GOT(__bss_end) 978 979 cmplw 0, r3, r4 980 beq 6f 981 982 li r0, 0 9835: 984 stw r0, 0(r3) 985 addi r3, r3, 4 986 cmplw 0, r3, r4 987 bne 5b 9886: 989 990 mr r3, r9 /* Global Data pointer */ 991 mr r4, r10 /* Destination Address */ 992 bl board_init_r 993 994#ifndef MINIMAL_SPL 995 /* 996 * Copy exception vector code to low memory 997 * 998 * r3: dest_addr 999 * r7: source address, r8: end address, r9: target address 1000 */ 1001 .globl trap_init 1002trap_init: 1003 mflr r4 /* save link register */ 1004 GET_GOT 1005 lwz r7, GOT(_start) 1006 lwz r8, GOT(_end_of_vectors) 1007 1008 li r9, 0x100 /* reset vector always at 0x100 */ 1009 1010 cmplw 0, r7, r8 1011 bgelr /* return if r7>=r8 - just in case */ 10121: 1013 lwz r0, 0(r7) 1014 stw r0, 0(r9) 1015 addi r7, r7, 4 1016 addi r9, r9, 4 1017 cmplw 0, r7, r8 1018 bne 1b 1019 1020 /* 1021 * relocate `hdlr' and `int_return' entries 1022 */ 1023 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET 1024 li r8, Alignment - _start + EXC_OFF_SYS_RESET 10252: 1026 bl trap_reloc 1027 addi r7, r7, 0x100 /* next exception vector */ 1028 cmplw 0, r7, r8 1029 blt 2b 1030 1031 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET 1032 bl trap_reloc 1033 1034 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET 1035 bl trap_reloc 1036 1037 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET 1038 li r8, SystemCall - _start + EXC_OFF_SYS_RESET 10393: 1040 bl trap_reloc 1041 addi r7, r7, 0x100 /* next exception vector */ 1042 cmplw 0, r7, r8 1043 blt 3b 1044 1045 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET 1046 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET 10474: 1048 bl trap_reloc 1049 addi r7, r7, 0x100 /* next exception vector */ 1050 cmplw 0, r7, r8 1051 blt 4b 1052 1053 mfmsr r3 /* now that the vectors have */ 1054 lis r7, MSR_IP@h /* relocated into low memory */ 1055 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ 1056 andc r3, r3, r7 /* (if it was on) */ 1057 SYNC /* Some chip revs need this... */ 1058 mtmsr r3 1059 SYNC 1060 1061 mtlr r4 /* restore link register */ 1062 blr 1063 1064#endif /* !MINIMAL_SPL */ 1065 1066#ifdef CONFIG_SYS_INIT_RAM_LOCK 1067lock_ram_in_cache: 1068 /* Allocate Initial RAM in data cache. 1069 */ 1070 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 1071 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 1072 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ 1073 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 1074 mtctr r4 10751: 1076 dcbz r0, r3 1077 addi r3, r3, 32 1078 bdnz 1b 1079 1080 /* Lock the data cache */ 1081 mfspr r0, HID0 1082 ori r0, r0, HID0_DLOCK 1083 sync 1084 mtspr HID0, r0 1085 sync 1086 blr 1087 1088#ifndef MINIMAL_SPL 1089.globl unlock_ram_in_cache 1090unlock_ram_in_cache: 1091 /* invalidate the INIT_RAM section */ 1092 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 1093 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 1094 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ 1095 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 1096 mtctr r4 10971: icbi r0, r3 1098 dcbi r0, r3 1099 addi r3, r3, 32 1100 bdnz 1b 1101 sync /* Wait for all icbi to complete on bus */ 1102 isync 1103 1104 /* Unlock the data cache and invalidate it */ 1105 mfspr r3, HID0 1106 li r5, HID0_DLOCK|HID0_DCFI 1107 andc r3, r3, r5 /* no invalidate, unlock */ 1108 ori r5, r3, HID0_DCFI /* invalidate, unlock */ 1109 sync 1110 mtspr HID0, r5 /* invalidate, unlock */ 1111 sync 1112 mtspr HID0, r3 /* no invalidate, unlock */ 1113 blr 1114#endif /* !MINIMAL_SPL */ 1115#endif /* CONFIG_SYS_INIT_RAM_LOCK */ 1116 1117#ifdef CONFIG_SYS_FLASHBOOT 1118map_flash_by_law1: 1119 /* When booting from ROM (Flash or EPROM), clear the */ 1120 /* Address Mask in OR0 so ROM appears everywhere */ 1121 /*----------------------------------------------------*/ 1122 lis r3, (CONFIG_SYS_IMMR)@h /* r3 <= CONFIG_SYS_IMMR */ 1123 lwz r4, OR0@l(r3) 1124 li r5, 0x7fff /* r5 <= 0x00007FFFF */ 1125 and r4, r4, r5 1126 stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */ 1127 1128 /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0, 1129 * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR] 1130 * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot 1131 * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is 1132 * 0xFF800. From the hard resetting to here, the processor fetched and 1133 * executed the instructions one by one. There is not absolutely 1134 * jumping happened. Laterly, the u-boot code has to do an absolutely 1135 * jumping to tell the CPU instruction fetching component what the 1136 * u-boot TEXT base address is. Because the TEXT base resides in the 1137 * boot ROM memory space, to garantee the code can run smoothly after 1138 * that jumping, we must map in the entire boot ROM by Local Access 1139 * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting 1140 * address for boot ROM, such as 0xFE000000. In this case, the default 1141 * LBIU Local Access Widow 0 will not cover this memory space. So, we 1142 * need another window to map in it. 1143 */ 1144 lis r4, (CONFIG_SYS_FLASH_BASE)@h 1145 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l 1146 stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */ 1147 1148 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */ 1149 lis r4, (0x80000012)@h 1150 ori r4, r4, (0x80000012)@l 1151 li r5, CONFIG_SYS_FLASH_SIZE 11521: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ 1153 addi r4, r4, 1 1154 bne 1b 1155 1156 stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */ 1157 /* Wait for HW to catch up */ 1158 lwz r4, LBLAWAR1(r3) 1159 twi 0,r4,0 1160 isync 1161 blr 1162 1163 /* Though all the LBIU Local Access Windows and LBC Banks will be 1164 * initialized in the C code, we'd better configure boot ROM's 1165 * window 0 and bank 0 correctly at here. 1166 */ 1167remap_flash_by_law0: 1168 /* Initialize the BR0 with the boot ROM starting address. */ 1169 lwz r4, BR0(r3) 1170 li r5, 0x7FFF 1171 and r4, r4, r5 1172 lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h 1173 ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l 1174 or r5, r5, r4 1175 stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */ 1176 1177 lwz r4, OR0(r3) 1178 lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1) 1179 or r4, r4, r5 1180 stw r4, OR0(r3) 1181 1182 lis r4, (CONFIG_SYS_FLASH_BASE)@h 1183 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l 1184 stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */ 1185 1186 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */ 1187 lis r4, (0x80000012)@h 1188 ori r4, r4, (0x80000012)@l 1189 li r5, CONFIG_SYS_FLASH_SIZE 11901: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ 1191 addi r4, r4, 1 1192 bne 1b 1193 stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */ 1194 1195 1196 xor r4, r4, r4 1197 stw r4, LBLAWBAR1(r3) 1198 stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */ 1199 /* Wait for HW to catch up */ 1200 lwz r4, LBLAWAR1(r3) 1201 twi 0,r4,0 1202 isync 1203 blr 1204#endif /* CONFIG_SYS_FLASHBOOT */ 1205