1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * T2080 RDB/PCIe board configuration file 8 */ 9 10 #ifndef __T2080RDB_H 11 #define __T2080RDB_H 12 13 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 14 #define CONFIG_FSL_SATA_V2 15 16 /* High Level Configuration Options */ 17 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 18 #define CONFIG_ENABLE_36BIT_PHYS 19 20 #ifdef CONFIG_PHYS_64BIT 21 #define CONFIG_ADDR_MAP 1 22 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 23 #endif 24 25 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 26 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 27 #define CONFIG_ENV_OVERWRITE 28 29 #ifdef CONFIG_RAMBOOT_PBL 30 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg 31 32 #define CONFIG_SPL_FLUSH_IMAGE 33 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 34 #define CONFIG_SPL_PAD_TO 0x40000 35 #define CONFIG_SPL_MAX_SIZE 0x28000 36 #define RESET_VECTOR_OFFSET 0x27FFC 37 #define BOOT_PAGE_OFFSET 0x27000 38 #ifdef CONFIG_SPL_BUILD 39 #define CONFIG_SPL_SKIP_RELOCATE 40 #define CONFIG_SPL_COMMON_INIT_DDR 41 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 42 #endif 43 44 #ifdef CONFIG_NAND 45 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 46 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 47 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 48 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 49 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 50 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg 51 #define CONFIG_SPL_NAND_BOOT 52 #endif 53 54 #ifdef CONFIG_SPIFLASH 55 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 56 #define CONFIG_SPL_SPI_FLASH_MINIMAL 57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 61 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 62 #ifndef CONFIG_SPL_BUILD 63 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 64 #endif 65 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg 66 #define CONFIG_SPL_SPI_BOOT 67 #endif 68 69 #ifdef CONFIG_SDCARD 70 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 71 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 72 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 73 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 74 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 75 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 76 #ifndef CONFIG_SPL_BUILD 77 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 78 #endif 79 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg 80 #define CONFIG_SPL_MMC_BOOT 81 #endif 82 83 #endif /* CONFIG_RAMBOOT_PBL */ 84 85 #define CONFIG_SRIO_PCIE_BOOT_MASTER 86 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 87 /* Set 1M boot space */ 88 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 89 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 90 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 91 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 92 #endif 93 94 #ifndef CONFIG_RESET_VECTOR_ADDRESS 95 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 96 #endif 97 98 /* 99 * These can be toggled for performance analysis, otherwise use default. 100 */ 101 #define CONFIG_SYS_CACHE_STASHING 102 #define CONFIG_BTB /* toggle branch predition */ 103 #define CONFIG_DDR_ECC 104 #ifdef CONFIG_DDR_ECC 105 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 106 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 107 #endif 108 109 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 110 #define CONFIG_SYS_MEMTEST_END 0x00400000 111 112 #if defined(CONFIG_SPIFLASH) 113 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 114 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 115 #define CONFIG_ENV_SECT_SIZE 0x10000 116 #elif defined(CONFIG_SDCARD) 117 #define CONFIG_SYS_MMC_ENV_DEV 0 118 #define CONFIG_ENV_SIZE 0x2000 119 #define CONFIG_ENV_OFFSET (512 * 0x800) 120 #elif defined(CONFIG_NAND) 121 #define CONFIG_ENV_SIZE 0x2000 122 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 123 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 124 #define CONFIG_ENV_ADDR 0xffe20000 125 #define CONFIG_ENV_SIZE 0x2000 126 #elif defined(CONFIG_ENV_IS_NOWHERE) 127 #define CONFIG_ENV_SIZE 0x2000 128 #else 129 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 130 #define CONFIG_ENV_SIZE 0x2000 131 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 132 #endif 133 134 #ifndef __ASSEMBLY__ 135 unsigned long get_board_sys_clk(void); 136 unsigned long get_board_ddr_clk(void); 137 #endif 138 139 #define CONFIG_SYS_CLK_FREQ 66660000 140 #define CONFIG_DDR_CLK_FREQ 133330000 141 142 /* 143 * Config the L3 Cache as L3 SRAM 144 */ 145 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 146 #define CONFIG_SYS_L3_SIZE (512 << 10) 147 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 148 #ifdef CONFIG_RAMBOOT_PBL 149 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 150 #endif 151 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 152 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 153 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 154 155 #define CONFIG_SYS_DCSRBAR 0xf0000000 156 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 157 158 /* EEPROM */ 159 #define CONFIG_ID_EEPROM 160 #define CONFIG_SYS_I2C_EEPROM_NXID 161 #define CONFIG_SYS_EEPROM_BUS_NUM 0 162 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 163 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 164 165 /* 166 * DDR Setup 167 */ 168 #define CONFIG_VERY_BIG_RAM 169 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 170 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 171 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 172 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 173 #define CONFIG_DDR_SPD 174 #define CONFIG_SYS_SPD_BUS_NUM 0 175 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 176 #define SPD_EEPROM_ADDRESS1 0x51 177 #define SPD_EEPROM_ADDRESS2 0x52 178 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 179 #define CTRL_INTLV_PREFERED cacheline 180 181 /* 182 * IFC Definitions 183 */ 184 #define CONFIG_SYS_FLASH_BASE 0xe8000000 185 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 186 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 187 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 188 CSPR_PORT_SIZE_16 | \ 189 CSPR_MSEL_NOR | \ 190 CSPR_V) 191 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 192 193 /* NOR Flash Timing Params */ 194 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 195 196 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 197 FTIM0_NOR_TEADC(0x5) | \ 198 FTIM0_NOR_TEAHC(0x5)) 199 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 200 FTIM1_NOR_TRAD_NOR(0x1A) |\ 201 FTIM1_NOR_TSEQRAD_NOR(0x13)) 202 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 203 FTIM2_NOR_TCH(0x4) | \ 204 FTIM2_NOR_TWPH(0x0E) | \ 205 FTIM2_NOR_TWP(0x1c)) 206 #define CONFIG_SYS_NOR_FTIM3 0x0 207 208 #define CONFIG_SYS_FLASH_QUIET_TEST 209 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 210 211 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 212 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 213 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 214 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 215 #define CONFIG_SYS_FLASH_EMPTY_INFO 216 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } 217 218 /* CPLD on IFC */ 219 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 220 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 221 #define CONFIG_SYS_CSPR2_EXT (0xf) 222 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 223 | CSPR_PORT_SIZE_8 \ 224 | CSPR_MSEL_GPCM \ 225 | CSPR_V) 226 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 227 #define CONFIG_SYS_CSOR2 0x0 228 229 /* CPLD Timing parameters for IFC CS2 */ 230 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 231 FTIM0_GPCM_TEADC(0x0e) | \ 232 FTIM0_GPCM_TEAHC(0x0e)) 233 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 234 FTIM1_GPCM_TRAD(0x1f)) 235 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 236 FTIM2_GPCM_TCH(0x8) | \ 237 FTIM2_GPCM_TWP(0x1f)) 238 #define CONFIG_SYS_CS2_FTIM3 0x0 239 240 /* NAND Flash on IFC */ 241 #define CONFIG_NAND_FSL_IFC 242 #define CONFIG_SYS_NAND_BASE 0xff800000 243 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 244 245 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 246 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 247 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 248 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 249 | CSPR_V) 250 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 251 252 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 253 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 254 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 255 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 256 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 257 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 258 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 259 260 #define CONFIG_SYS_NAND_ONFI_DETECTION 261 262 /* ONFI NAND Flash mode0 Timing Params */ 263 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 264 FTIM0_NAND_TWP(0x18) | \ 265 FTIM0_NAND_TWCHT(0x07) | \ 266 FTIM0_NAND_TWH(0x0a)) 267 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 268 FTIM1_NAND_TWBE(0x39) | \ 269 FTIM1_NAND_TRR(0x0e) | \ 270 FTIM1_NAND_TRP(0x18)) 271 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 272 FTIM2_NAND_TREH(0x0a) | \ 273 FTIM2_NAND_TWHRE(0x1e)) 274 #define CONFIG_SYS_NAND_FTIM3 0x0 275 276 #define CONFIG_SYS_NAND_DDR_LAW 11 277 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 278 #define CONFIG_SYS_MAX_NAND_DEVICE 1 279 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 280 281 #if defined(CONFIG_NAND) 282 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 283 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 284 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 285 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 286 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 287 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 288 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 289 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 290 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 291 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 292 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 293 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 294 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 295 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 296 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 297 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 298 #else 299 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 300 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 301 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 302 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 303 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 304 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 305 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 306 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 307 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 308 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 309 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 310 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 311 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 312 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 313 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 314 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 315 #endif 316 317 #if defined(CONFIG_RAMBOOT_PBL) 318 #define CONFIG_SYS_RAMBOOT 319 #endif 320 321 #ifdef CONFIG_SPL_BUILD 322 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 323 #else 324 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 325 #endif 326 327 #define CONFIG_HWCONFIG 328 329 /* define to use L1 as initial stack */ 330 #define CONFIG_L1_INIT_RAM 331 #define CONFIG_SYS_INIT_RAM_LOCK 332 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 333 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 334 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 335 /* The assembler doesn't like typecast */ 336 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 337 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 338 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 339 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 340 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 341 GENERATED_GBL_DATA_SIZE) 342 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 343 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 344 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 345 346 /* 347 * Serial Port 348 */ 349 #define CONFIG_SYS_NS16550_SERIAL 350 #define CONFIG_SYS_NS16550_REG_SIZE 1 351 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 352 #define CONFIG_SYS_BAUDRATE_TABLE \ 353 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 354 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 355 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 356 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 357 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 358 359 /* 360 * I2C 361 */ 362 #define CONFIG_SYS_I2C 363 #define CONFIG_SYS_I2C_FSL 364 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 365 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 366 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 367 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 368 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 369 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 370 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 371 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 372 #define CONFIG_SYS_FSL_I2C_SPEED 100000 373 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 374 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 375 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 376 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 377 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 378 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 379 #define I2C_MUX_CH_DEFAULT 0x8 380 381 #define I2C_MUX_CH_VOL_MONITOR 0xa 382 383 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv" 384 #ifndef CONFIG_SPL_BUILD 385 #define CONFIG_VID 386 #endif 387 #define CONFIG_VOL_MONITOR_IR36021_SET 388 #define CONFIG_VOL_MONITOR_IR36021_READ 389 /* The lowest and highest voltage allowed for T208xRDB */ 390 #define VDD_MV_MIN 819 391 #define VDD_MV_MAX 1212 392 393 /* 394 * RapidIO 395 */ 396 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 397 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 398 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 399 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 400 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 401 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 402 /* 403 * for slave u-boot IMAGE instored in master memory space, 404 * PHYS must be aligned based on the SIZE 405 */ 406 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 407 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 408 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 409 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 410 /* 411 * for slave UCODE and ENV instored in master memory space, 412 * PHYS must be aligned based on the SIZE 413 */ 414 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 415 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 416 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 417 418 /* slave core release by master*/ 419 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 420 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 421 422 /* 423 * SRIO_PCIE_BOOT - SLAVE 424 */ 425 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 426 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 427 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 428 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 429 #endif 430 431 /* 432 * eSPI - Enhanced SPI 433 */ 434 435 /* 436 * General PCI 437 * Memory space is mapped 1-1, but I/O space must start from 0. 438 */ 439 #define CONFIG_PCIE1 /* PCIE controller 1 */ 440 #define CONFIG_PCIE2 /* PCIE controller 2 */ 441 #define CONFIG_PCIE3 /* PCIE controller 3 */ 442 #define CONFIG_PCIE4 /* PCIE controller 4 */ 443 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 444 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 445 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 446 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 447 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 448 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 449 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 450 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 451 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 452 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 453 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 454 455 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 456 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 457 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 458 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 459 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 460 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 461 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 462 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 463 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 464 465 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 466 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 467 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 468 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 469 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 470 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 471 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 472 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 473 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 474 475 /* controller 4, Base address 203000 */ 476 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 477 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 478 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 479 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 480 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 481 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 482 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 483 484 #ifdef CONFIG_PCI 485 #define CONFIG_PCI_INDIRECT_BRIDGE 486 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ 487 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 488 #endif 489 490 /* Qman/Bman */ 491 #ifndef CONFIG_NOBQFMAN 492 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 493 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 494 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 495 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 496 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 497 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 498 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 499 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 500 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 501 CONFIG_SYS_BMAN_CENA_SIZE) 502 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 503 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 504 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 505 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 506 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 507 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 508 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 509 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 510 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 511 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 512 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 513 CONFIG_SYS_QMAN_CENA_SIZE) 514 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 515 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 516 517 #define CONFIG_SYS_DPAA_FMAN 518 #define CONFIG_SYS_DPAA_PME 519 #define CONFIG_SYS_PMAN 520 #define CONFIG_SYS_DPAA_DCE 521 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 522 #define CONFIG_SYS_INTERLAKEN 523 524 /* Default address of microcode for the Linux Fman driver */ 525 #if defined(CONFIG_SPIFLASH) 526 /* 527 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 528 * env, so we got 0x110000. 529 */ 530 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 531 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH 532 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 533 #define CONFIG_CORTINA_FW_ADDR 0x120000 534 535 #elif defined(CONFIG_SDCARD) 536 /* 537 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 538 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 539 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 540 */ 541 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 542 #define CONFIG_SYS_CORTINA_FW_IN_MMC 543 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 544 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) 545 546 #elif defined(CONFIG_NAND) 547 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 548 #define CONFIG_SYS_CORTINA_FW_IN_NAND 549 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 550 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 551 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 552 /* 553 * Slave has no ucode locally, it can fetch this from remote. When implementing 554 * in two corenet boards, slave's ucode could be stored in master's memory 555 * space, the address can be mapped from slave TLB->slave LAW-> 556 * slave SRIO or PCIE outbound window->master inbound window-> 557 * master LAW->the ucode address in master's memory space. 558 */ 559 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 560 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE 561 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 562 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000 563 #else 564 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 565 #define CONFIG_SYS_CORTINA_FW_IN_NOR 566 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 567 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000 568 #endif 569 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 570 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 571 #endif /* CONFIG_NOBQFMAN */ 572 573 #ifdef CONFIG_SYS_DPAA_FMAN 574 #define CONFIG_FMAN_ENET 575 #define CONFIG_PHY_CORTINA 576 #define CONFIG_PHY_REALTEK 577 #define CONFIG_CORTINA_FW_LENGTH 0x40000 578 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ 579 #define RGMII_PHY2_ADDR 0x02 580 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ 581 #define CORTINA_PHY_ADDR2 0x0d 582 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ 583 #define FM1_10GEC4_PHY_ADDR 0x01 584 #endif 585 586 #ifdef CONFIG_FMAN_ENET 587 #define CONFIG_ETHPRIME "FM1@DTSEC3" 588 #endif 589 590 /* 591 * SATA 592 */ 593 #ifdef CONFIG_FSL_SATA_V2 594 #define CONFIG_SYS_SATA_MAX_DEVICE 2 595 #define CONFIG_SATA1 596 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 597 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 598 #define CONFIG_SATA2 599 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 600 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 601 #define CONFIG_LBA48 602 #endif 603 604 /* 605 * USB 606 */ 607 #ifdef CONFIG_USB_EHCI_HCD 608 #define CONFIG_USB_EHCI_FSL 609 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 610 #define CONFIG_HAS_FSL_DR_USB 611 #endif 612 613 /* 614 * SDHC 615 */ 616 #ifdef CONFIG_MMC 617 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 618 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 619 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 620 #endif 621 622 /* 623 * Dynamic MTD Partition support with mtdparts 624 */ 625 626 /* 627 * Environment 628 */ 629 630 /* 631 * Miscellaneous configurable options 632 */ 633 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 634 635 /* 636 * For booting Linux, the board info and command line data 637 * have to be in the first 64 MB of memory, since this is 638 * the maximum mapped by the Linux kernel during initialization. 639 */ 640 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 641 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 642 643 #ifdef CONFIG_CMD_KGDB 644 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 645 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 646 #endif 647 648 /* 649 * Environment Configuration 650 */ 651 #define CONFIG_ROOTPATH "/opt/nfsroot" 652 #define CONFIG_BOOTFILE "uImage" 653 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 654 655 /* default location for tftp and bootm */ 656 #define CONFIG_LOADADDR 1000000 657 #define __USB_PHY_TYPE utmi 658 659 #define CONFIG_EXTRA_ENV_SETTINGS \ 660 "hwconfig=fsl_ddr:" \ 661 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 662 "bank_intlv=auto;" \ 663 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 664 "netdev=eth0\0" \ 665 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 666 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 667 "tftpflash=tftpboot $loadaddr $uboot && " \ 668 "protect off $ubootaddr +$filesize && " \ 669 "erase $ubootaddr +$filesize && " \ 670 "cp.b $loadaddr $ubootaddr $filesize && " \ 671 "protect on $ubootaddr +$filesize && " \ 672 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 673 "consoledev=ttyS0\0" \ 674 "ramdiskaddr=2000000\0" \ 675 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ 676 "fdtaddr=1e00000\0" \ 677 "fdtfile=t2080rdb/t2080rdb.dtb\0" \ 678 "bdev=sda3\0" 679 680 /* 681 * For emulation this causes u-boot to jump to the start of the 682 * proof point app code automatically 683 */ 684 #define CONFIG_PROOF_POINTS \ 685 "setenv bootargs root=/dev/$bdev rw " \ 686 "console=$consoledev,$baudrate $othbootargs;" \ 687 "cpu 1 release 0x29000000 - - -;" \ 688 "cpu 2 release 0x29000000 - - -;" \ 689 "cpu 3 release 0x29000000 - - -;" \ 690 "cpu 4 release 0x29000000 - - -;" \ 691 "cpu 5 release 0x29000000 - - -;" \ 692 "cpu 6 release 0x29000000 - - -;" \ 693 "cpu 7 release 0x29000000 - - -;" \ 694 "go 0x29000000" 695 696 #define CONFIG_HVBOOT \ 697 "setenv bootargs config-addr=0x60000000; " \ 698 "bootm 0x01000000 - 0x00f00000" 699 700 #define CONFIG_ALU \ 701 "setenv bootargs root=/dev/$bdev rw " \ 702 "console=$consoledev,$baudrate $othbootargs;" \ 703 "cpu 1 release 0x01000000 - - -;" \ 704 "cpu 2 release 0x01000000 - - -;" \ 705 "cpu 3 release 0x01000000 - - -;" \ 706 "cpu 4 release 0x01000000 - - -;" \ 707 "cpu 5 release 0x01000000 - - -;" \ 708 "cpu 6 release 0x01000000 - - -;" \ 709 "cpu 7 release 0x01000000 - - -;" \ 710 "go 0x01000000" 711 712 #define CONFIG_LINUX \ 713 "setenv bootargs root=/dev/ram rw " \ 714 "console=$consoledev,$baudrate $othbootargs;" \ 715 "setenv ramdiskaddr 0x02000000;" \ 716 "setenv fdtaddr 0x00c00000;" \ 717 "setenv loadaddr 0x1000000;" \ 718 "bootm $loadaddr $ramdiskaddr $fdtaddr" 719 720 #define CONFIG_HDBOOT \ 721 "setenv bootargs root=/dev/$bdev rw " \ 722 "console=$consoledev,$baudrate $othbootargs;" \ 723 "tftp $loadaddr $bootfile;" \ 724 "tftp $fdtaddr $fdtfile;" \ 725 "bootm $loadaddr - $fdtaddr" 726 727 #define CONFIG_NFSBOOTCOMMAND \ 728 "setenv bootargs root=/dev/nfs rw " \ 729 "nfsroot=$serverip:$rootpath " \ 730 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 731 "console=$consoledev,$baudrate $othbootargs;" \ 732 "tftp $loadaddr $bootfile;" \ 733 "tftp $fdtaddr $fdtfile;" \ 734 "bootm $loadaddr - $fdtaddr" 735 736 #define CONFIG_RAMBOOTCOMMAND \ 737 "setenv bootargs root=/dev/ram rw " \ 738 "console=$consoledev,$baudrate $othbootargs;" \ 739 "tftp $ramdiskaddr $ramdiskfile;" \ 740 "tftp $loadaddr $bootfile;" \ 741 "tftp $fdtaddr $fdtfile;" \ 742 "bootm $loadaddr $ramdiskaddr $fdtaddr" 743 744 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 745 746 #include <asm/fsl_secure_boot.h> 747 748 #endif /* __T2080RDB_H */ 749