xref: /openbmc/linux/drivers/reset/Kconfig (revision aead1076) 
1# SPDX-License-Identifier: GPL-2.0-only
2config ARCH_HAS_RESET_CONTROLLER
3	bool
4
5menuconfig RESET_CONTROLLER
6	bool "Reset Controller Support"
7	default y if ARCH_HAS_RESET_CONTROLLER
8	help
9	  Generic Reset Controller support.
10
11	  This framework is designed to abstract reset handling of devices
12	  via GPIOs or SoC-internal reset controller modules.
13
14	  If unsure, say no.
15
16if RESET_CONTROLLER
17
18config RESET_A10SR
19	tristate "Altera Arria10 System Resource Reset"
20	depends on MFD_ALTERA_A10SR || COMPILE_TEST
21	help
22	  This option enables support for the external reset functions for
23	  peripheral PHYs on the Altera Arria10 System Resource Chip.
24
25config RESET_ATH79
26	bool "AR71xx Reset Driver" if COMPILE_TEST
27	default ATH79
28	help
29	  This enables the ATH79 reset controller driver that supports the
30	  AR71xx SoC reset controller.
31
32config RESET_AXS10X
33	bool "AXS10x Reset Driver" if COMPILE_TEST
34	default ARC_PLAT_AXS10X
35	help
36	  This enables the reset controller driver for AXS10x.
37
38config RESET_BCM6345
39	bool "BCM6345 Reset Controller"
40	depends on BMIPS_GENERIC || COMPILE_TEST
41	default BMIPS_GENERIC
42	help
43	  This enables the reset controller driver for BCM6345 SoCs.
44
45config RESET_BERLIN
46	tristate "Berlin Reset Driver"
47	depends on ARCH_BERLIN || COMPILE_TEST
48	default m if ARCH_BERLIN
49	help
50	  This enables the reset controller driver for Marvell Berlin SoCs.
51
52config RESET_BRCMSTB
53	tristate "Broadcom STB reset controller"
54	depends on ARCH_BRCMSTB || COMPILE_TEST
55	default ARCH_BRCMSTB
56	help
57	  This enables the reset controller driver for Broadcom STB SoCs using
58	  a SUN_TOP_CTRL_SW_INIT style controller.
59
60config RESET_BRCMSTB_RESCAL
61	tristate "Broadcom STB RESCAL reset controller"
62	depends on HAS_IOMEM
63	depends on ARCH_BRCMSTB || COMPILE_TEST
64	default ARCH_BRCMSTB
65	help
66	  This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
67	  BCM7216.
68
69config RESET_HSDK
70	bool "Synopsys HSDK Reset Driver"
71	depends on HAS_IOMEM
72	depends on ARC_SOC_HSDK || COMPILE_TEST
73	help
74	  This enables the reset controller driver for HSDK board.
75
76config RESET_IMX7
77	tristate "i.MX7/8 Reset Driver"
78	depends on HAS_IOMEM
79	depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST
80	default y if SOC_IMX7D
81	select MFD_SYSCON
82	help
83	  This enables the reset controller driver for i.MX7 SoCs.
84
85config RESET_INTEL_GW
86	bool "Intel Reset Controller Driver"
87	depends on X86 || COMPILE_TEST
88	depends on OF && HAS_IOMEM
89	select REGMAP_MMIO
90	help
91	  This enables the reset controller driver for Intel Gateway SoCs.
92	  Say Y to control the reset signals provided by reset controller.
93	  Otherwise, say N.
94
95config RESET_K210
96	bool "Reset controller driver for Canaan Kendryte K210 SoC"
97	depends on (SOC_CANAAN || COMPILE_TEST) && OF
98	select MFD_SYSCON
99	default SOC_CANAAN
100	help
101	  Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
102	  Say Y if you want to control reset signals provided by this
103	  controller.
104
105config RESET_LANTIQ
106	bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
107	default SOC_TYPE_XWAY
108	help
109	  This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
110
111config RESET_LPC18XX
112	bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
113	default ARCH_LPC18XX
114	help
115	  This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
116
117config RESET_MCHP_SPARX5
118	bool "Microchip Sparx5 reset driver"
119	depends on ARCH_SPARX5 || SOC_LAN966 || COMPILE_TEST
120	default y if SPARX5_SWITCH
121	select MFD_SYSCON
122	help
123	  This driver supports switch core reset for the Microchip Sparx5 SoC.
124
125config RESET_MESON
126	tristate "Meson Reset Driver"
127	depends on ARCH_MESON || COMPILE_TEST
128	default ARCH_MESON
129	help
130	  This enables the reset driver for Amlogic Meson SoCs.
131
132config RESET_MESON_AUDIO_ARB
133	tristate "Meson Audio Memory Arbiter Reset Driver"
134	depends on ARCH_MESON || COMPILE_TEST
135	help
136	  This enables the reset driver for Audio Memory Arbiter of
137	  Amlogic's A113 based SoCs
138
139config RESET_NPCM
140	bool "NPCM BMC Reset Driver" if COMPILE_TEST
141	default ARCH_NPCM
142	help
143	  This enables the reset controller driver for Nuvoton NPCM
144	  BMC SoCs.
145
146config RESET_NUVOTON_MA35D1
147	bool "Nuvoton MA35D1 Reset Driver"
148	depends on ARCH_MA35 || COMPILE_TEST
149	default ARCH_MA35
150	help
151	  This enables the reset controller driver for Nuvoton MA35D1 SoC.
152
153config RESET_PISTACHIO
154	bool "Pistachio Reset Driver"
155	depends on MIPS || COMPILE_TEST
156	help
157	  This enables the reset driver for ImgTec Pistachio SoCs.
158
159config RESET_POLARFIRE_SOC
160	bool "Microchip PolarFire SoC (MPFS) Reset Driver"
161	depends on MCHP_CLK_MPFS
162	select AUXILIARY_BUS
163	default MCHP_CLK_MPFS
164	help
165	  This driver supports peripheral reset for the Microchip PolarFire SoC
166
167config RESET_QCOM_AOSS
168	tristate "Qcom AOSS Reset Driver"
169	depends on ARCH_QCOM || COMPILE_TEST
170	help
171	  This enables the AOSS (always on subsystem) reset driver
172	  for Qualcomm SDM845 SoCs. Say Y if you want to control
173	  reset signals provided by AOSS for Modem, Venus, ADSP,
174	  GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
175
176config RESET_QCOM_PDC
177	tristate "Qualcomm PDC Reset Driver"
178	depends on ARCH_QCOM || COMPILE_TEST
179	help
180	  This enables the PDC (Power Domain Controller) reset driver
181	  for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
182	  to control reset signals provided by PDC for Modem, Compute,
183	  Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
184
185config RESET_RASPBERRYPI
186	tristate "Raspberry Pi 4 Firmware Reset Driver"
187	depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST)
188	default USB_XHCI_PCI
189	help
190	  Raspberry Pi 4's co-processor controls some of the board's HW
191	  initialization process, but it's up to Linux to trigger it when
192	  relevant. This driver provides a reset controller capable of
193	  interfacing with RPi4's co-processor and model these firmware
194	  initialization routines as reset lines.
195
196config RESET_RZG2L_USBPHY_CTRL
197	tristate "Renesas RZ/G2L USBPHY control driver"
198	depends on ARCH_RZG2L || COMPILE_TEST
199	help
200	  Support for USBPHY Control found on RZ/G2L family. It mainly
201	  controls reset and power down of the USB/PHY.
202
203config RESET_SCMI
204	tristate "Reset driver controlled via ARM SCMI interface"
205	depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
206	default ARM_SCMI_PROTOCOL
207	help
208	  This driver provides support for reset signal/domains that are
209	  controlled by firmware that implements the SCMI interface.
210
211	  This driver uses SCMI Message Protocol to interact with the
212	  firmware controlling all the reset signals.
213
214config RESET_SIMPLE
215	bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT
216	default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC
217	depends on HAS_IOMEM
218	help
219	  This enables a simple reset controller driver for reset lines that
220	  that can be asserted and deasserted by toggling bits in a contiguous,
221	  exclusive register space.
222
223	  Currently this driver supports:
224	   - Altera SoCFPGAs
225	   - ASPEED BMC SoCs
226	   - Bitmain BM1880 SoC
227	   - Realtek SoCs
228	   - RCC reset controller in STM32 MCUs
229	   - Allwinner SoCs
230	   - SiFive FU740 SoCs
231
232config RESET_SOCFPGA
233	bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA)
234	default ARM && ARCH_INTEL_SOCFPGA
235	select RESET_SIMPLE
236	help
237	  This enables the reset driver for the SoCFPGA ARMv7 platforms. This
238	  driver gets initialized early during platform init calls.
239
240config RESET_SUNPLUS
241	bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
242	default ARCH_SUNPLUS
243	help
244	  This enables the reset driver support for Sunplus SoCs.
245	  The reset lines that can be asserted and deasserted by toggling bits
246	  in a contiguous, exclusive register space. The register is HIWORD_MASKED,
247	  which means each register holds 16 reset lines.
248
249config RESET_SUNXI
250	bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
251	default ARCH_SUNXI
252	select RESET_SIMPLE
253	help
254	  This enables the reset driver for Allwinner SoCs.
255
256config RESET_TI_SCI
257	tristate "TI System Control Interface (TI-SCI) reset driver"
258	depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n)
259	help
260	  This enables the reset driver support over TI System Control Interface
261	  available on some new TI's SoCs. If you wish to use reset resources
262	  managed by the TI System Controller, say Y here. Otherwise, say N.
263
264config RESET_TI_SYSCON
265	tristate "TI SYSCON Reset Driver"
266	depends on HAS_IOMEM
267	select MFD_SYSCON
268	help
269	  This enables the reset driver support for TI devices with
270	  memory-mapped reset registers as part of a syscon device node. If
271	  you wish to use the reset framework for such memory-mapped devices,
272	  say Y here. Otherwise, say N.
273
274config RESET_TI_TPS380X
275	tristate "TI TPS380x Reset Driver"
276	select GPIOLIB
277	help
278	  This enables the reset driver support for TI TPS380x devices. If
279	  you wish to use the reset framework for such devices, say Y here.
280	  Otherwise, say N.
281
282config RESET_TN48M_CPLD
283	tristate "Delta Networks TN48M switch CPLD reset controller"
284	depends on MFD_TN48M_CPLD || COMPILE_TEST
285	default MFD_TN48M_CPLD
286	help
287	  This enables the reset controller driver for the Delta TN48M CPLD.
288	  It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X
289	  switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and
290	  Microchip PD69200 PoE PSE controller.
291
292	  This driver can also be built as a module. If so, the module will be
293	  called reset-tn48m.
294
295config RESET_UNIPHIER
296	tristate "Reset controller driver for UniPhier SoCs"
297	depends on ARCH_UNIPHIER || COMPILE_TEST
298	depends on OF && MFD_SYSCON
299	default ARCH_UNIPHIER
300	help
301	  Support for reset controllers on UniPhier SoCs.
302	  Say Y if you want to control reset signals provided by System Control
303	  block, Media I/O block, Peripheral Block.
304
305config RESET_UNIPHIER_GLUE
306	tristate "Reset driver in glue layer for UniPhier SoCs"
307	depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
308	default ARCH_UNIPHIER
309	select RESET_SIMPLE
310	help
311	  Support for peripheral core reset included in its own glue layer
312	  on UniPhier SoCs. Say Y if you want to control reset signals
313	  provided by the glue layer.
314
315config RESET_ZYNQ
316	bool "ZYNQ Reset Driver" if COMPILE_TEST
317	default ARCH_ZYNQ
318	help
319	  This enables the reset controller driver for Xilinx Zynq SoCs.
320
321source "drivers/reset/starfive/Kconfig"
322source "drivers/reset/sti/Kconfig"
323source "drivers/reset/hisilicon/Kconfig"
324source "drivers/reset/tegra/Kconfig"
325
326endif
327