xref: /openbmc/linux/drivers/reset/Kconfig (revision cd3c50d8) 
1# SPDX-License-Identifier: GPL-2.0-only
2config ARCH_HAS_RESET_CONTROLLER
3	bool
4
5menuconfig RESET_CONTROLLER
6	bool "Reset Controller Support"
7	default y if ARCH_HAS_RESET_CONTROLLER
8	help
9	  Generic Reset Controller support.
10
11	  This framework is designed to abstract reset handling of devices
12	  via GPIOs or SoC-internal reset controller modules.
13
14	  If unsure, say no.
15
16if RESET_CONTROLLER
17
18config RESET_A10SR
19	tristate "Altera Arria10 System Resource Reset"
20	depends on MFD_ALTERA_A10SR || COMPILE_TEST
21	help
22	  This option enables support for the external reset functions for
23	  peripheral PHYs on the Altera Arria10 System Resource Chip.
24
25config RESET_ATH79
26	bool "AR71xx Reset Driver" if COMPILE_TEST
27	default ATH79
28	help
29	  This enables the ATH79 reset controller driver that supports the
30	  AR71xx SoC reset controller.
31
32config RESET_AXS10X
33	bool "AXS10x Reset Driver" if COMPILE_TEST
34	default ARC_PLAT_AXS10X
35	help
36	  This enables the reset controller driver for AXS10x.
37
38config RESET_BCM6345
39	bool "BCM6345 Reset Controller"
40	depends on BMIPS_GENERIC || COMPILE_TEST
41	default BMIPS_GENERIC
42	help
43	  This enables the reset controller driver for BCM6345 SoCs.
44
45config RESET_BERLIN
46	tristate "Berlin Reset Driver"
47	depends on ARCH_BERLIN || COMPILE_TEST
48	default m if ARCH_BERLIN
49	help
50	  This enables the reset controller driver for Marvell Berlin SoCs.
51
52config RESET_BRCMSTB
53	tristate "Broadcom STB reset controller"
54	depends on ARCH_BRCMSTB || COMPILE_TEST
55	default ARCH_BRCMSTB
56	help
57	  This enables the reset controller driver for Broadcom STB SoCs using
58	  a SUN_TOP_CTRL_SW_INIT style controller.
59
60config RESET_BRCMSTB_RESCAL
61	tristate "Broadcom STB RESCAL reset controller"
62	depends on HAS_IOMEM
63	depends on ARCH_BRCMSTB || COMPILE_TEST
64	default ARCH_BRCMSTB
65	help
66	  This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
67	  BCM7216.
68
69config RESET_HSDK
70	bool "Synopsys HSDK Reset Driver"
71	depends on HAS_IOMEM
72	depends on ARC_SOC_HSDK || COMPILE_TEST
73	help
74	  This enables the reset controller driver for HSDK board.
75
76config RESET_IMX7
77	tristate "i.MX7/8 Reset Driver"
78	depends on HAS_IOMEM
79	depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST
80	default y if SOC_IMX7D
81	select MFD_SYSCON
82	help
83	  This enables the reset controller driver for i.MX7 SoCs.
84
85config RESET_INTEL_GW
86	bool "Intel Reset Controller Driver"
87	depends on X86 || COMPILE_TEST
88	depends on OF && HAS_IOMEM
89	select REGMAP_MMIO
90	help
91	  This enables the reset controller driver for Intel Gateway SoCs.
92	  Say Y to control the reset signals provided by reset controller.
93	  Otherwise, say N.
94
95config RESET_K210
96	bool "Reset controller driver for Canaan Kendryte K210 SoC"
97	depends on (SOC_CANAAN || COMPILE_TEST) && OF
98	select MFD_SYSCON
99	default SOC_CANAAN
100	help
101	  Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
102	  Say Y if you want to control reset signals provided by this
103	  controller.
104
105config RESET_LANTIQ
106	bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
107	default SOC_TYPE_XWAY
108	help
109	  This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
110
111config RESET_LPC18XX
112	bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
113	default ARCH_LPC18XX
114	help
115	  This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
116
117config RESET_MCHP_SPARX5
118	bool "Microchip Sparx5 reset driver"
119	depends on ARCH_SPARX5 || SOC_LAN966 || COMPILE_TEST
120	default y if SPARX5_SWITCH
121	select MFD_SYSCON
122	help
123	  This driver supports switch core reset for the Microchip Sparx5 SoC.
124
125config RESET_MESON
126	tristate "Meson Reset Driver"
127	depends on ARCH_MESON || COMPILE_TEST
128	default ARCH_MESON
129	help
130	  This enables the reset driver for Amlogic Meson SoCs.
131
132config RESET_MESON_AUDIO_ARB
133	tristate "Meson Audio Memory Arbiter Reset Driver"
134	depends on ARCH_MESON || COMPILE_TEST
135	help
136	  This enables the reset driver for Audio Memory Arbiter of
137	  Amlogic's A113 based SoCs
138
139config RESET_NPCM
140	bool "NPCM BMC Reset Driver" if COMPILE_TEST
141	default ARCH_NPCM
142	select AUXILIARY_BUS
143	help
144	  This enables the reset controller driver for Nuvoton NPCM
145	  BMC SoCs.
146
147config RESET_NUVOTON_MA35D1
148	bool "Nuvoton MA35D1 Reset Driver"
149	depends on ARCH_MA35 || COMPILE_TEST
150	default ARCH_MA35
151	help
152	  This enables the reset controller driver for Nuvoton MA35D1 SoC.
153
154config RESET_PISTACHIO
155	bool "Pistachio Reset Driver"
156	depends on MIPS || COMPILE_TEST
157	help
158	  This enables the reset driver for ImgTec Pistachio SoCs.
159
160config RESET_POLARFIRE_SOC
161	bool "Microchip PolarFire SoC (MPFS) Reset Driver"
162	depends on MCHP_CLK_MPFS
163	select AUXILIARY_BUS
164	default MCHP_CLK_MPFS
165	help
166	  This driver supports peripheral reset for the Microchip PolarFire SoC
167
168config RESET_QCOM_AOSS
169	tristate "Qcom AOSS Reset Driver"
170	depends on ARCH_QCOM || COMPILE_TEST
171	help
172	  This enables the AOSS (always on subsystem) reset driver
173	  for Qualcomm SDM845 SoCs. Say Y if you want to control
174	  reset signals provided by AOSS for Modem, Venus, ADSP,
175	  GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
176
177config RESET_QCOM_PDC
178	tristate "Qualcomm PDC Reset Driver"
179	depends on ARCH_QCOM || COMPILE_TEST
180	help
181	  This enables the PDC (Power Domain Controller) reset driver
182	  for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
183	  to control reset signals provided by PDC for Modem, Compute,
184	  Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
185
186config RESET_RASPBERRYPI
187	tristate "Raspberry Pi 4 Firmware Reset Driver"
188	depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST)
189	default USB_XHCI_PCI
190	help
191	  Raspberry Pi 4's co-processor controls some of the board's HW
192	  initialization process, but it's up to Linux to trigger it when
193	  relevant. This driver provides a reset controller capable of
194	  interfacing with RPi4's co-processor and model these firmware
195	  initialization routines as reset lines.
196
197config RESET_RZG2L_USBPHY_CTRL
198	tristate "Renesas RZ/G2L USBPHY control driver"
199	depends on ARCH_RZG2L || COMPILE_TEST
200	help
201	  Support for USBPHY Control found on RZ/G2L family. It mainly
202	  controls reset and power down of the USB/PHY.
203
204config RESET_SCMI
205	tristate "Reset driver controlled via ARM SCMI interface"
206	depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
207	default ARM_SCMI_PROTOCOL
208	help
209	  This driver provides support for reset signal/domains that are
210	  controlled by firmware that implements the SCMI interface.
211
212	  This driver uses SCMI Message Protocol to interact with the
213	  firmware controlling all the reset signals.
214
215config RESET_SIMPLE
216	bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT
217	default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC
218	depends on HAS_IOMEM
219	help
220	  This enables a simple reset controller driver for reset lines that
221	  that can be asserted and deasserted by toggling bits in a contiguous,
222	  exclusive register space.
223
224	  Currently this driver supports:
225	   - Altera SoCFPGAs
226	   - ASPEED BMC SoCs
227	   - Bitmain BM1880 SoC
228	   - Realtek SoCs
229	   - RCC reset controller in STM32 MCUs
230	   - Allwinner SoCs
231	   - SiFive FU740 SoCs
232
233config RESET_SOCFPGA
234	bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA)
235	default ARM && ARCH_INTEL_SOCFPGA
236	select RESET_SIMPLE
237	help
238	  This enables the reset driver for the SoCFPGA ARMv7 platforms. This
239	  driver gets initialized early during platform init calls.
240
241config RESET_SUNPLUS
242	bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
243	default ARCH_SUNPLUS
244	help
245	  This enables the reset driver support for Sunplus SoCs.
246	  The reset lines that can be asserted and deasserted by toggling bits
247	  in a contiguous, exclusive register space. The register is HIWORD_MASKED,
248	  which means each register holds 16 reset lines.
249
250config RESET_SUNXI
251	bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
252	default ARCH_SUNXI
253	select RESET_SIMPLE
254	help
255	  This enables the reset driver for Allwinner SoCs.
256
257config RESET_TI_SCI
258	tristate "TI System Control Interface (TI-SCI) reset driver"
259	depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n)
260	help
261	  This enables the reset driver support over TI System Control Interface
262	  available on some new TI's SoCs. If you wish to use reset resources
263	  managed by the TI System Controller, say Y here. Otherwise, say N.
264
265config RESET_TI_SYSCON
266	tristate "TI SYSCON Reset Driver"
267	depends on HAS_IOMEM
268	select MFD_SYSCON
269	help
270	  This enables the reset driver support for TI devices with
271	  memory-mapped reset registers as part of a syscon device node. If
272	  you wish to use the reset framework for such memory-mapped devices,
273	  say Y here. Otherwise, say N.
274
275config RESET_TI_TPS380X
276	tristate "TI TPS380x Reset Driver"
277	select GPIOLIB
278	help
279	  This enables the reset driver support for TI TPS380x devices. If
280	  you wish to use the reset framework for such devices, say Y here.
281	  Otherwise, say N.
282
283config RESET_TN48M_CPLD
284	tristate "Delta Networks TN48M switch CPLD reset controller"
285	depends on MFD_TN48M_CPLD || COMPILE_TEST
286	default MFD_TN48M_CPLD
287	help
288	  This enables the reset controller driver for the Delta TN48M CPLD.
289	  It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X
290	  switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and
291	  Microchip PD69200 PoE PSE controller.
292
293	  This driver can also be built as a module. If so, the module will be
294	  called reset-tn48m.
295
296config RESET_UNIPHIER
297	tristate "Reset controller driver for UniPhier SoCs"
298	depends on ARCH_UNIPHIER || COMPILE_TEST
299	depends on OF && MFD_SYSCON
300	default ARCH_UNIPHIER
301	help
302	  Support for reset controllers on UniPhier SoCs.
303	  Say Y if you want to control reset signals provided by System Control
304	  block, Media I/O block, Peripheral Block.
305
306config RESET_UNIPHIER_GLUE
307	tristate "Reset driver in glue layer for UniPhier SoCs"
308	depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
309	default ARCH_UNIPHIER
310	select RESET_SIMPLE
311	help
312	  Support for peripheral core reset included in its own glue layer
313	  on UniPhier SoCs. Say Y if you want to control reset signals
314	  provided by the glue layer.
315
316config RESET_ZYNQ
317	bool "ZYNQ Reset Driver" if COMPILE_TEST
318	default ARCH_ZYNQ
319	help
320	  This enables the reset controller driver for Xilinx Zynq SoCs.
321
322source "drivers/reset/starfive/Kconfig"
323source "drivers/reset/sti/Kconfig"
324source "drivers/reset/hisilicon/Kconfig"
325source "drivers/reset/tegra/Kconfig"
326
327endif
328