1# 2# Multifunction miscellaneous devices 3# 4 5menu "Multifunction device drivers" 6 7config MISC 8 bool "Enable Driver Model for Misc drivers" 9 depends on DM 10 help 11 Enable driver model for miscellaneous devices. This class is 12 used only for those do not fit other more general classes. A 13 set of generic read, write and ioctl methods may be used to 14 access the device. 15 16config ASPEED_AHBC 17 bool "Aspeed AHBC support" 18 depends on ARCH_ASPEED 19 help 20 Select this to enable ahbc driver for Aspeed SoC. 21 22config ASPEED_DP 23 bool "Aspeed Display Port firmware driver" 24 depends on ARCH_ASPEED 25 help 26 Select this to enable Diplay Port firmware driver 27 28config ASPEED_FSI 29 bool "Enable ASPEED FSI driver" 30 depends on ARCH_ASPEED 31 help 32 Support the FSI master present in the ASPEED system on chips. 33 34config ALTERA_SYSID 35 bool "Altera Sysid support" 36 depends on MISC 37 help 38 Select this to enable a sysid for Altera devices. Please find 39 details on the "Embedded Peripherals IP User Guide" of Altera. 40 41config ATSHA204A 42 bool "Support for Atmel ATSHA204A module" 43 depends on MISC 44 help 45 Enable support for I2C connected Atmel's ATSHA204A 46 CryptoAuthentication module found for example on the Turris Omnia 47 board. 48 49config ROCKCHIP_EFUSE 50 bool "Rockchip e-fuse support" 51 depends on MISC 52 help 53 Enable (read-only) access for the e-fuse block found in Rockchip 54 SoCs: accesses can either be made using byte addressing and a length 55 or through child-nodes that are generated based on the e-fuse map 56 retrieved from the DTS. 57 58 This driver currently supports the RK3399 only, but can easily be 59 extended (by porting the read function from the Linux kernel sources) 60 to support other recent Rockchip devices. 61 62config VEXPRESS_CONFIG 63 bool "Enable support for Arm Versatile Express config bus" 64 depends on MISC 65 help 66 If you say Y here, you will get support for accessing the 67 configuration bus on the Arm Versatile Express boards via 68 a sysreg driver. 69 70config CMD_CROS_EC 71 bool "Enable crosec command" 72 depends on CROS_EC 73 help 74 Enable command-line access to the Chrome OS EC (Embedded 75 Controller). This provides the 'crosec' command which has 76 a number of sub-commands for performing EC tasks such as 77 updating its flash, accessing a small saved context area 78 and talking to the I2C bus behind the EC (if there is one). 79 80config CROS_EC 81 bool "Enable Chrome OS EC" 82 help 83 Enable access to the Chrome OS EC. This is a separate 84 microcontroller typically available on a SPI bus on Chromebooks. It 85 provides access to the keyboard, some internal storage and may 86 control access to the battery and main PMIC depending on the 87 device. You can use the 'crosec' command to access it. 88 89config CROS_EC_I2C 90 bool "Enable Chrome OS EC I2C driver" 91 depends on CROS_EC 92 help 93 Enable I2C access to the Chrome OS EC. This is used on older 94 ARM Chromebooks such as snow and spring before the standard bus 95 changed to SPI. The EC will accept commands across the I2C using 96 a special message protocol, and provide responses. 97 98config CROS_EC_LPC 99 bool "Enable Chrome OS EC LPC driver" 100 depends on CROS_EC 101 help 102 Enable I2C access to the Chrome OS EC. This is used on x86 103 Chromebooks such as link and falco. The keyboard is provided 104 through a legacy port interface, so on x86 machines the main 105 function of the EC is power and thermal management. 106 107config CROS_EC_SANDBOX 108 bool "Enable Chrome OS EC sandbox driver" 109 depends on CROS_EC && SANDBOX 110 help 111 Enable a sandbox emulation of the Chrome OS EC. This supports 112 keyboard (use the -l flag to enable the LCD), verified boot context, 113 EC flash read/write/erase support and a few other things. It is 114 enough to perform a Chrome OS verified boot on sandbox. 115 116config CROS_EC_SPI 117 bool "Enable Chrome OS EC SPI driver" 118 depends on CROS_EC 119 help 120 Enable SPI access to the Chrome OS EC. This is used on newer 121 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface 122 provides a faster and more robust interface than I2C but the bugs 123 are less interesting. 124 125config DS4510 126 bool "Enable support for DS4510 CPU supervisor" 127 help 128 Enable support for the Maxim DS4510 CPU supervisor. It has an 129 integrated 64-byte EEPROM, four programmable non-volatile I/O pins 130 and a configurable timer for the supervisor function. The device is 131 connected over I2C. 132 133config FSL_SEC_MON 134 bool "Enable FSL SEC_MON Driver" 135 help 136 Freescale Security Monitor block is responsible for monitoring 137 system states. 138 Security Monitor can be transitioned on any security failures, 139 like software violations or hardware security violations. 140 141config JZ4780_EFUSE 142 bool "Ingenic JZ4780 eFUSE support" 143 depends on ARCH_JZ47XX 144 help 145 This selects support for the eFUSE on Ingenic JZ4780 SoCs. 146 147config MXC_OCOTP 148 bool "Enable MXC OCOTP Driver" 149 help 150 If you say Y here, you will get support for the One Time 151 Programmable memory pages that are stored on the some 152 Freescale i.MX processors. 153 154config NUVOTON_NCT6102D 155 bool "Enable Nuvoton NCT6102D Super I/O driver" 156 help 157 If you say Y here, you will get support for the Nuvoton 158 NCT6102D Super I/O driver. This can be used to enable or 159 disable the legacy UART, the watchdog or other devices 160 in the Nuvoton Super IO chips on X86 platforms. 161 162config PWRSEQ 163 bool "Enable power-sequencing drivers" 164 depends on DM 165 help 166 Power-sequencing drivers provide support for controlling power for 167 devices. They are typically referenced by a phandle from another 168 device. When the device is started up, its power sequence can be 169 initiated. 170 171config SPL_PWRSEQ 172 bool "Enable power-sequencing drivers for SPL" 173 depends on PWRSEQ 174 help 175 Power-sequencing drivers provide support for controlling power for 176 devices. They are typically referenced by a phandle from another 177 device. When the device is started up, its power sequence can be 178 initiated. 179 180config PCA9551_LED 181 bool "Enable PCA9551 LED driver" 182 help 183 Enable driver for PCA9551 LED controller. This controller 184 is connected via I2C. So I2C needs to be enabled. 185 186config PCA9551_I2C_ADDR 187 hex "I2C address of PCA9551 LED controller" 188 depends on PCA9551_LED 189 default 0x60 190 help 191 The I2C address of the PCA9551 LED controller. 192 193config STM32MP_FUSE 194 bool "Enable STM32MP fuse wrapper providing the fuse API" 195 depends on ARCH_STM32MP && MISC 196 default y if CMD_FUSE 197 help 198 If you say Y here, you will get support for the fuse API (OTP) 199 for STM32MP architecture. 200 This API is needed for CMD_FUSE. 201 202config STM32_RCC 203 bool "Enable RCC driver for the STM32 SoC's family" 204 depends on (STM32 || ARCH_STM32MP) && MISC 205 help 206 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control 207 block) is responsible of the management of the clock and reset 208 generation. 209 This driver is similar to an MFD driver in the Linux kernel. 210 211config TEGRA_CAR 212 bool "Enable support for the Tegra CAR driver" 213 depends on TEGRA_NO_BPMP 214 help 215 The Tegra CAR (Clock and Reset Controller) is a HW module that 216 controls almost all clocks and resets in a Tegra SoC. 217 218config TEGRA186_BPMP 219 bool "Enable support for the Tegra186 BPMP driver" 220 depends on TEGRA186 221 help 222 The Tegra BPMP (Boot and Power Management Processor) is a separate 223 auxiliary CPU embedded into Tegra to perform power management work, 224 and controls related features such as clocks, resets, power domains, 225 PMIC I2C bus, etc. This driver provides the core low-level 226 communication path by which feature-specific drivers (such as clock) 227 can make requests to the BPMP. This driver is similar to an MFD 228 driver in the Linux kernel. 229 230config TWL4030_LED 231 bool "Enable TWL4030 LED controller" 232 help 233 Enable this to add support for the TWL4030 LED controller. 234 235config WINBOND_W83627 236 bool "Enable Winbond Super I/O driver" 237 help 238 If you say Y here, you will get support for the Winbond 239 W83627 Super I/O driver. This can be used to enable the 240 legacy UART or other devices in the Winbond Super IO chips 241 on X86 platforms. 242 243config QFW 244 bool 245 help 246 Hidden option to enable QEMU fw_cfg interface. This will be selected by 247 either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. 248 249config I2C_EEPROM 250 bool "Enable driver for generic I2C-attached EEPROMs" 251 depends on MISC 252 help 253 Enable a generic driver for EEPROMs attached via I2C. 254 255 256config SPL_I2C_EEPROM 257 bool "Enable driver for generic I2C-attached EEPROMs for SPL" 258 depends on MISC && SPL && SPL_DM 259 help 260 This option is an SPL-variant of the I2C_EEPROM option. 261 See the help of I2C_EEPROM for details. 262 263config ZYNQ_GEM_I2C_MAC_OFFSET 264 hex "Set the I2C MAC offset" 265 default 0x0 266 depends on DM_I2C 267 help 268 Set the MAC offset for i2C. 269 270if I2C_EEPROM 271 272config SYS_I2C_EEPROM_ADDR 273 hex "Chip address of the EEPROM device" 274 default 0 275 276config SYS_I2C_EEPROM_BUS 277 int "I2C bus of the EEPROM device." 278 default 0 279 280config SYS_EEPROM_SIZE 281 int "Size in bytes of the EEPROM device" 282 default 256 283 284config SYS_EEPROM_PAGE_WRITE_BITS 285 int "Number of bits used to address bytes in a single page" 286 default 0 287 help 288 The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. 289 A 64 byte page, for example would require six bits. 290 291config SYS_EEPROM_PAGE_WRITE_DELAY_MS 292 int "Number of milliseconds to delay between page writes" 293 default 0 294 295config SYS_I2C_EEPROM_ADDR_LEN 296 int "Length in bytes of the EEPROM memory array address" 297 default 1 298 help 299 Note: This is NOT the chip address length! 300 301config SYS_I2C_EEPROM_ADDR_OVERFLOW 302 hex "EEPROM Address Overflow" 303 default 0 304 help 305 EEPROM chips that implement "address overflow" are ones 306 like Catalyst 24WC04/08/16 which has 9/10/11 bits of 307 address and the extra bits end up in the "chip address" bit 308 slots. This makes a 24WC08 (1Kbyte) chip look like four 256 309 byte chips. 310 311endif 312 313config GDSYS_RXAUI_CTRL 314 bool "Enable gdsys RXAUI control driver" 315 depends on MISC 316 help 317 Support gdsys FPGA's RXAUI control. 318 319config GDSYS_IOEP 320 bool "Enable gdsys IOEP driver" 321 depends on MISC 322 help 323 Support gdsys FPGA's IO endpoint driver. 324 325config MPC83XX_SERDES 326 bool "Enable MPC83xx serdes driver" 327 depends on MISC 328 help 329 Support for serdes found on MPC83xx SoCs. 330 331config FS_LOADER 332 bool "Enable loader driver for file system" 333 help 334 This is file system generic loader which can be used to load 335 the file image from the storage into target such as memory. 336 337 The consumer driver would then use this loader to program whatever, 338 ie. the FPGA device. 339 340config GDSYS_SOC 341 bool "Enable gdsys SOC driver" 342 depends on MISC 343 help 344 Support for gdsys IHS SOC, a simple bus associated with each gdsys 345 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose 346 register maps are contained within the FPGA's register map. 347 348config IHS_FPGA 349 bool "Enable IHS FPGA driver" 350 depends on MISC 351 help 352 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on 353 gdsys devices, which supply the majority of the functionality offered 354 by the devices. This driver supports both CON and CPU variants of the 355 devices, depending on the device tree entry. 356 357endmenu 358