1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2010-2012 Freescale Semiconductor, Inc.
4 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
5 * Timur Tabi <timur@freescale.com>
6 */
7
8 #include <common.h>
9 #include <command.h>
10 #include <pci.h>
11 #include <asm/processor.h>
12 #include <asm/mmu.h>
13 #include <asm/cache.h>
14 #include <asm/immap_85xx.h>
15 #include <asm/fsl_pci.h>
16 #include <fsl_ddr_sdram.h>
17 #include <asm/fsl_serdes.h>
18 #include <asm/io.h>
19 #include <linux/libfdt.h>
20 #include <fdt_support.h>
21 #include <fsl_mdio.h>
22 #include <tsec.h>
23 #include <asm/fsl_law.h>
24 #include <netdev.h>
25 #include <i2c.h>
26 #include <hwconfig.h>
27
28 #include "../common/ngpixis.h"
29
board_early_init_f(void)30 int board_early_init_f(void)
31 {
32 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
33
34 /* Set pmuxcr to allow both i2c1 and i2c2 */
35 setbits_be32(&gur->pmuxcr, 0x1000);
36 #ifdef CONFIG_SYS_RAMBOOT
37 setbits_be32(&gur->pmuxcr,
38 in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
39 #endif
40
41 /* Read back the register to synchronize the write. */
42 in_be32(&gur->pmuxcr);
43
44 /* Set the pin muxing to enable ETSEC2. */
45 clrbits_be32(&gur->pmuxcr2, 0x001F8000);
46
47 /* Enable the SPI */
48 clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI);
49
50 return 0;
51 }
52
checkboard(void)53 int checkboard(void)
54 {
55 u8 sw;
56
57 printf("Board: P1022DS Sys ID: 0x%02x, "
58 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
59 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
60
61 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
62
63 switch ((sw & PIXIS_LBMAP_MASK) >> 6) {
64 case 0:
65 printf ("vBank: %u\n", ((sw & 0x30) >> 4));
66 break;
67 case 1:
68 printf ("NAND\n");
69 break;
70 case 2:
71 case 3:
72 puts ("Promjet\n");
73 break;
74 }
75
76 return 0;
77 }
78
79 #define CONFIG_TFP410_I2C_ADDR 0x38
80
81 /* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */
82 #define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK 0x0c
83 #define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK 0x03
84
85 /* Route the I2C1 pins to the SSI port instead. */
86 #define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI 0x08
87
88 /* Choose the 12.288Mhz codec reference clock */
89 #define CONFIG_PIXIS_BRDCFG1_AUDCLK_12 0x02
90
91 /* Choose the 11.2896Mhz codec reference clock */
92 #define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01
93
94 /* Connect to USB2 */
95 #define CONFIG_PIXIS_BRDCFG0_USB2 0x10
96 /* Connect to TFM bus */
97 #define CONFIG_PIXIS_BRDCFG1_TDM 0x0c
98 /* Connect to SPI */
99 #define CONFIG_PIXIS_BRDCFG0_SPI 0x80
100
misc_init_r(void)101 int misc_init_r(void)
102 {
103 u8 temp;
104 const char *audclk;
105 size_t arglen;
106 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
107
108 /* For DVI, enable the TFP410 Encoder. */
109
110 temp = 0xBF;
111 if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
112 return -1;
113 if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
114 return -1;
115 debug("DVI Encoder Read: 0x%02x\n", temp);
116
117 temp = 0x10;
118 if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
119 return -1;
120 if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
121 return -1;
122 debug("DVI Encoder Read: 0x%02x\n",temp);
123
124 /* Enable the USB2 in PMUXCR2 and FGPA */
125 if (hwconfig("usb2")) {
126 clrsetbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_ETSECUSB_MASK,
127 MPC85xx_PMUXCR2_USB);
128 setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_USB2);
129 }
130
131 /* tdm and audio can not enable simultaneous*/
132 if (hwconfig("tdm") && hwconfig("audclk")){
133 printf("WARNING: TDM and AUDIO can not be enabled simultaneous !\n");
134 return -1;
135 }
136
137 /* Enable the TDM in PMUXCR and FGPA */
138 if (hwconfig("tdm")) {
139 clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_MASK,
140 MPC85xx_PMUXCR_TDM);
141 setbits_8(&pixis->brdcfg1, CONFIG_PIXIS_BRDCFG1_TDM);
142 /* TDM need some configration option by SPI */
143 clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SPI_MASK,
144 MPC85xx_PMUXCR_SPI);
145 setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_SPI);
146 }
147
148 /*
149 * Enable the reference clock for the WM8776 codec, and route the MUX
150 * pins for SSI. The default is the 12.288 MHz clock
151 */
152
153 if (hwconfig("audclk")) {
154 temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
155 CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
156 temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
157
158 audclk = hwconfig_arg("audclk", &arglen);
159 /* Check the first two chars only */
160 if (audclk && (strncmp(audclk, "11", 2) == 0))
161 temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
162 else
163 temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
164 setbits_8(&pixis->brdcfg1, temp);
165 }
166
167 return 0;
168 }
169
170 /*
171 * A list of PCI and SATA slots
172 */
173 enum slot_id {
174 SLOT_PCIE1 = 1,
175 SLOT_PCIE2,
176 SLOT_PCIE3,
177 SLOT_PCIE4,
178 SLOT_PCIE5,
179 SLOT_SATA1,
180 SLOT_SATA2
181 };
182
183 /*
184 * This array maps the slot identifiers to their names on the P1022DS board.
185 */
186 static const char *slot_names[] = {
187 [SLOT_PCIE1] = "Slot 1",
188 [SLOT_PCIE2] = "Slot 2",
189 [SLOT_PCIE3] = "Slot 3",
190 [SLOT_PCIE4] = "Slot 4",
191 [SLOT_PCIE5] = "Mini-PCIe",
192 [SLOT_SATA1] = "SATA 1",
193 [SLOT_SATA2] = "SATA 2",
194 };
195
196 /*
197 * This array maps a given SERDES configuration and SERDES device to the PCI or
198 * SATA slot that it connects to. This mapping is hard-coded in the FPGA.
199 */
200 static u8 serdes_dev_slot[][SATA2 + 1] = {
201 [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
202 [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
203 [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
204 [PCIE2] = SLOT_PCIE5 },
205 [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
206 [PCIE2] = SLOT_PCIE3,
207 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
208 [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
209 [PCIE2] = SLOT_PCIE3 },
210 [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
211 [PCIE2] = SLOT_PCIE3,
212 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
213 [0x1c] = { [PCIE1] = SLOT_PCIE1,
214 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
215 [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
216 [0x1f] = { [PCIE1] = SLOT_PCIE1 },
217 };
218
219
220 /*
221 * Returns the name of the slot to which the PCIe or SATA controller is
222 * connected
223 */
board_serdes_name(enum srds_prtcl device)224 const char *board_serdes_name(enum srds_prtcl device)
225 {
226 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
227 u32 pordevsr = in_be32(&gur->pordevsr);
228 unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
229 MPC85xx_PORDEVSR_IO_SEL_SHIFT;
230 enum slot_id slot = serdes_dev_slot[srds_cfg][device];
231 const char *name = slot_names[slot];
232
233 if (name)
234 return name;
235 else
236 return "Nothing";
237 }
238
239 #ifdef CONFIG_PCI
pci_init_board(void)240 void pci_init_board(void)
241 {
242 fsl_pcie_init_board(0);
243 }
244 #endif
245
board_early_init_r(void)246 int board_early_init_r(void)
247 {
248 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
249 int flash_esel = find_tlb_idx((void *)flashbase, 1);
250
251 /*
252 * Remap Boot flash + PROMJET region to caching-inhibited
253 * so that flash can be erased properly.
254 */
255
256 /* Flush d-cache and invalidate i-cache of any FLASH data */
257 flush_dcache();
258 invalidate_icache();
259
260 if (flash_esel == -1) {
261 /* very unlikely unless something is messed up */
262 puts("Error: Could not find TLB for FLASH BASE\n");
263 flash_esel = 2; /* give our best effort to continue */
264 } else {
265 /* invalidate existing TLB entry for flash + promjet */
266 disable_tlb(flash_esel);
267 }
268
269 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
270 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
271 0, flash_esel, BOOKE_PAGESZ_256M, 1);
272
273 return 0;
274 }
275
276 /*
277 * Initialize on-board and/or PCI Ethernet devices
278 *
279 * Returns:
280 * <0, error
281 * 0, no ethernet devices found
282 * >0, number of ethernet devices initialized
283 */
board_eth_init(bd_t * bis)284 int board_eth_init(bd_t *bis)
285 {
286 struct fsl_pq_mdio_info mdio_info;
287 struct tsec_info_struct tsec_info[2];
288 unsigned int num = 0;
289
290 #ifdef CONFIG_TSEC1
291 SET_STD_TSEC_INFO(tsec_info[num], 1);
292 num++;
293 #endif
294 #ifdef CONFIG_TSEC2
295 SET_STD_TSEC_INFO(tsec_info[num], 2);
296 num++;
297 #endif
298
299 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
300 mdio_info.name = DEFAULT_MII_NAME;
301 fsl_pq_mdio_init(bis, &mdio_info);
302
303 return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
304 }
305
306 #ifdef CONFIG_OF_BOARD_SETUP
307 /**
308 * ft_codec_setup - fix up the clock-frequency property of the codec node
309 *
310 * Update the clock-frequency property based on the value of the 'audclk'
311 * hwconfig option. If audclk is not specified, then don't write anything
312 * to the device tree, because it means that the codec clock is disabled.
313 */
ft_codec_setup(void * blob,const char * compatible)314 static void ft_codec_setup(void *blob, const char *compatible)
315 {
316 const char *audclk;
317 size_t arglen;
318 u32 freq;
319
320 audclk = hwconfig_arg("audclk", &arglen);
321 if (audclk) {
322 if (strncmp(audclk, "11", 2) == 0)
323 freq = 11289600;
324 else
325 freq = 12288000;
326
327 do_fixup_by_compat_u32(blob, compatible, "clock-frequency",
328 freq, 1);
329 }
330 }
331
ft_board_setup(void * blob,bd_t * bd)332 int ft_board_setup(void *blob, bd_t *bd)
333 {
334 phys_addr_t base;
335 phys_size_t size;
336
337 ft_cpu_setup(blob, bd);
338
339 base = env_get_bootm_low();
340 size = env_get_bootm_size();
341
342 fdt_fixup_memory(blob, (u64)base, (u64)size);
343
344 #ifdef CONFIG_HAS_FSL_DR_USB
345 fsl_fdt_fixup_dr_usb(blob, bd);
346 #endif
347
348 FT_FSL_PCI_SETUP;
349
350 #ifdef CONFIG_FSL_SGMII_RISER
351 fsl_sgmii_riser_fdt_fixup(blob);
352 #endif
353
354 /* Update the WM8776 node's clock frequency property */
355 ft_codec_setup(blob, "wlf,wm8776");
356
357 return 0;
358 }
359 #endif
360