1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License version 2 as published 6 * by the Free Software Foundation. 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_QE 1 /* Has QE */ 17 #define CONFIG_MPC832x 1 /* MPC832x CPU specific */ 18 19 /* 20 * System Clock Setup 21 */ 22 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 23 24 #ifndef CONFIG_SYS_CLK_FREQ 25 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 26 #endif 27 28 /* 29 * Hardware Reset Configuration Word 30 */ 31 #define CONFIG_SYS_HRCW_LOW (\ 32 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 33 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 34 HRCWL_VCO_1X2 |\ 35 HRCWL_CSB_TO_CLKIN_2X1 |\ 36 HRCWL_CORE_TO_CSB_2_5X1 |\ 37 HRCWL_CE_PLL_VCO_DIV_2 |\ 38 HRCWL_CE_PLL_DIV_1X1 |\ 39 HRCWL_CE_TO_PLL_1X3) 40 41 #define CONFIG_SYS_HRCW_HIGH (\ 42 HRCWH_PCI_HOST |\ 43 HRCWH_PCI1_ARBITER_ENABLE |\ 44 HRCWH_CORE_ENABLE |\ 45 HRCWH_FROM_0X00000100 |\ 46 HRCWH_BOOTSEQ_DISABLE |\ 47 HRCWH_SW_WATCHDOG_DISABLE |\ 48 HRCWH_ROM_LOC_LOCAL_16BIT |\ 49 HRCWH_BIG_ENDIAN |\ 50 HRCWH_LALE_NORMAL) 51 52 /* 53 * System IO Config 54 */ 55 #define CONFIG_SYS_SICRL 0x00000000 56 57 /* 58 * IMMR new address 59 */ 60 #define CONFIG_SYS_IMMR 0xE0000000 61 62 /* 63 * System performance 64 */ 65 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 66 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 67 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */ 68 #define CONFIG_SYS_SPCR_OPT 1 69 70 /* 71 * DDR Setup 72 */ 73 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 74 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 75 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 76 77 #undef CONFIG_SPD_EEPROM 78 #if defined(CONFIG_SPD_EEPROM) 79 /* Determine DDR configuration from I2C interface 80 */ 81 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ 82 #else 83 /* Manually set up DDR parameters 84 */ 85 #define CONFIG_SYS_DDR_SIZE 64 /* MB */ 86 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 87 | CSCONFIG_ROW_BIT_13 \ 88 | CSCONFIG_COL_BIT_9) 89 /* 0x80010101 */ 90 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 91 | (0 << TIMING_CFG0_WRT_SHIFT) \ 92 | (0 << TIMING_CFG0_RRT_SHIFT) \ 93 | (0 << TIMING_CFG0_WWT_SHIFT) \ 94 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 95 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 96 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 97 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 98 /* 0x00220802 */ 99 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 100 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 101 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 102 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 103 | (3 << TIMING_CFG1_REFREC_SHIFT) \ 104 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 105 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 106 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 107 /* 0x26253222 */ 108 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 109 | (31 << TIMING_CFG2_CPO_SHIFT) \ 110 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 111 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 112 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 113 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 114 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT)) 115 /* 0x1f9048c7 */ 116 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 117 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 118 /* 0x02000000 */ 119 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ 120 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 121 /* 0x44480232 */ 122 #define CONFIG_SYS_DDR_MODE2 0x8000c000 123 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \ 124 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 125 /* 0x03200064 */ 126 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003 127 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 128 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 129 | SDRAM_CFG_32_BE) 130 /* 0x43080000 */ 131 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 132 #endif 133 134 /* 135 * Memory test 136 */ 137 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 138 #define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */ 139 #define CONFIG_SYS_MEMTEST_END 0x03f00000 140 141 /* 142 * The reserved memory 143 */ 144 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 145 146 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 147 #define CONFIG_SYS_RAMBOOT 148 #else 149 #undef CONFIG_SYS_RAMBOOT 150 #endif 151 152 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 153 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 154 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 155 156 /* 157 * Initial RAM Base Address Setup 158 */ 159 #define CONFIG_SYS_INIT_RAM_LOCK 1 160 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 161 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 162 #define CONFIG_SYS_GBL_DATA_OFFSET \ 163 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 164 165 /* 166 * Local Bus Configuration & Clock Setup 167 */ 168 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 169 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 170 #define CONFIG_SYS_LBC_LBCR 0x00000000 171 172 /* 173 * FLASH on the Local Bus 174 */ 175 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 176 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ 177 178 /* Window base at flash base */ 179 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 180 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) 181 182 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 183 | BR_PS_16 /* 16 bit port */ \ 184 | BR_MS_GPCM /* MSEL = GPCM */ \ 185 | BR_V) /* valid */ 186 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 187 | OR_GPCM_XAM \ 188 | OR_GPCM_CSNT \ 189 | OR_GPCM_ACS_DIV2 \ 190 | OR_GPCM_XACS \ 191 | OR_GPCM_SCY_15 \ 192 | OR_GPCM_TRLX_SET \ 193 | OR_GPCM_EHTR_SET \ 194 | OR_GPCM_EAD) 195 /* 0xFE006FF7 */ 196 197 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 198 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 199 200 #undef CONFIG_SYS_FLASH_CHECKSUM 201 202 /* 203 * Serial Port 204 */ 205 #define CONFIG_SYS_NS16550_SERIAL 206 #define CONFIG_SYS_NS16550_REG_SIZE 1 207 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 208 209 #define CONFIG_SYS_BAUDRATE_TABLE \ 210 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 211 212 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 213 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 214 215 /* I2C */ 216 #define CONFIG_SYS_I2C 217 #define CONFIG_SYS_I2C_FSL 218 #define CONFIG_SYS_FSL_I2C_SPEED 400000 219 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 220 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 221 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 222 223 /* 224 * Config on-board EEPROM 225 */ 226 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 227 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 228 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 229 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 230 231 /* 232 * General PCI 233 * Addresses are mapped 1-1. 234 */ 235 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 236 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 237 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 238 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 239 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 240 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 241 #define CONFIG_SYS_PCI1_IO_BASE 0xd0000000 242 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE 243 #define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */ 244 245 #ifdef CONFIG_PCI 246 #define CONFIG_PCI_INDIRECT_BRIDGE 247 #define CONFIG_PCI_SKIP_HOST_BRIDGE 248 249 #undef CONFIG_EEPRO100 250 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 251 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 252 253 #endif /* CONFIG_PCI */ 254 255 /* 256 * QE UEC ethernet configuration 257 */ 258 #define CONFIG_UEC_ETH 259 #define CONFIG_ETHPRIME "UEC0" 260 261 #define CONFIG_UEC_ETH1 /* ETH3 */ 262 263 #ifdef CONFIG_UEC_ETH1 264 #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */ 265 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9 266 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 267 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 268 #define CONFIG_SYS_UEC1_PHY_ADDR 4 269 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 270 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 271 #endif 272 273 #define CONFIG_UEC_ETH2 /* ETH4 */ 274 275 #ifdef CONFIG_UEC_ETH2 276 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 277 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK16 278 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK3 279 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH 280 #define CONFIG_SYS_UEC2_PHY_ADDR 0 281 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 282 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 283 #endif 284 285 /* 286 * Environment 287 */ 288 #ifndef CONFIG_SYS_RAMBOOT 289 #define CONFIG_ENV_ADDR \ 290 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 291 #define CONFIG_ENV_SECT_SIZE 0x20000 292 #define CONFIG_ENV_SIZE 0x2000 293 #else 294 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 295 #define CONFIG_ENV_SIZE 0x2000 296 #endif 297 298 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 299 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 300 301 /* 302 * BOOTP options 303 */ 304 #define CONFIG_BOOTP_BOOTFILESIZE 305 306 /* 307 * Command line configuration. 308 */ 309 310 #undef CONFIG_WATCHDOG /* watchdog disabled */ 311 312 /* 313 * Miscellaneous configurable options 314 */ 315 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 316 317 /* 318 * For booting Linux, the board info and command line data 319 * have to be in the first 256 MB of memory, since this is 320 * the maximum mapped by the Linux kernel during initialization. 321 */ 322 /* Initial Memory map for Linux */ 323 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 324 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 325 326 /* 327 * Core HID Setup 328 */ 329 #define CONFIG_SYS_HID0_INIT 0x000000000 330 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 331 HID0_ENABLE_INSTRUCTION_CACHE) 332 #define CONFIG_SYS_HID2 HID2_HBE 333 334 /* 335 * MMU Setup 336 */ 337 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 338 339 /* DDR: cache cacheable */ 340 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 341 | BATL_PP_RW \ 342 | BATL_MEMCOHERENCE) 343 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 344 | BATU_BL_256M \ 345 | BATU_VS \ 346 | BATU_VP) 347 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 348 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 349 350 /* IMMRBAR & PCI IO: cache-inhibit and guarded */ 351 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ 352 | BATL_PP_RW \ 353 | BATL_CACHEINHIBIT \ 354 | BATL_GUARDEDSTORAGE) 355 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ 356 | BATU_BL_4M \ 357 | BATU_VS \ 358 | BATU_VP) 359 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 360 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 361 362 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 363 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \ 364 | BATL_PP_RW \ 365 | BATL_MEMCOHERENCE) 366 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \ 367 | BATU_BL_32M \ 368 | BATU_VS \ 369 | BATU_VP) 370 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \ 371 | BATL_PP_RW \ 372 | BATL_CACHEINHIBIT \ 373 | BATL_GUARDEDSTORAGE) 374 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 375 376 #define CONFIG_SYS_IBAT3L (0) 377 #define CONFIG_SYS_IBAT3U (0) 378 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 379 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 380 381 /* Stack in dcache: cacheable, no memory coherence */ 382 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 383 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \ 384 | BATU_BL_128K \ 385 | BATU_VS \ 386 | BATU_VP) 387 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 388 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 389 390 #ifdef CONFIG_PCI 391 /* PCI MEM space: cacheable */ 392 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS \ 393 | BATL_PP_RW \ 394 | BATL_MEMCOHERENCE) 395 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS \ 396 | BATU_BL_256M \ 397 | BATU_VS \ 398 | BATU_VP) 399 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 400 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 401 /* PCI MMIO space: cache-inhibit and guarded */ 402 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS \ 403 | BATL_PP_RW \ 404 | BATL_CACHEINHIBIT \ 405 | BATL_GUARDEDSTORAGE) 406 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS \ 407 | BATU_BL_256M \ 408 | BATU_VS \ 409 | BATU_VP) 410 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 411 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 412 #else 413 #define CONFIG_SYS_IBAT5L (0) 414 #define CONFIG_SYS_IBAT5U (0) 415 #define CONFIG_SYS_IBAT6L (0) 416 #define CONFIG_SYS_IBAT6U (0) 417 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 418 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 419 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 420 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 421 #endif 422 423 /* Nothing in BAT7 */ 424 #define CONFIG_SYS_IBAT7L (0) 425 #define CONFIG_SYS_IBAT7U (0) 426 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 427 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 428 429 #if (CONFIG_CMD_KGDB) 430 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 431 #endif 432 433 /* 434 * Environment Configuration 435 */ 436 #define CONFIG_ENV_OVERWRITE 437 438 #define CONFIG_HAS_ETH0 /* add support for "ethaddr" */ 439 #define CONFIG_HAS_ETH1 /* add support for "eth1addr" */ 440 441 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM 442 * (see CONFIG_SYS_I2C_EEPROM) */ 443 /* MAC address offset in I2C EEPROM */ 444 #define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00 445 446 #define CONFIG_NETDEV "eth1" 447 448 #define CONFIG_HOSTNAME "mpc8323erdb" 449 #define CONFIG_ROOTPATH "/nfsroot" 450 #define CONFIG_BOOTFILE "uImage" 451 /* U-Boot image on TFTP server */ 452 #define CONFIG_UBOOTPATH "u-boot.bin" 453 #define CONFIG_FDTFILE "mpc832x_rdb.dtb" 454 #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot" 455 456 /* default location for tftp and bootm */ 457 #define CONFIG_LOADADDR 800000 458 459 #define CONFIG_EXTRA_ENV_SETTINGS \ 460 "netdev=" CONFIG_NETDEV "\0" \ 461 "uboot=" CONFIG_UBOOTPATH "\0" \ 462 "tftpflash=tftp $loadaddr $uboot;" \ 463 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 464 " +$filesize; " \ 465 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 466 " +$filesize; " \ 467 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 468 " $filesize; " \ 469 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 470 " +$filesize; " \ 471 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 472 " $filesize\0" \ 473 "fdtaddr=780000\0" \ 474 "fdtfile=" CONFIG_FDTFILE "\0" \ 475 "ramdiskaddr=1000000\0" \ 476 "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \ 477 "console=ttyS0\0" \ 478 "setbootargs=setenv bootargs " \ 479 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\ 480 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 481 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ 482 "$netdev:off "\ 483 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 484 485 #define CONFIG_NFSBOOTCOMMAND \ 486 "setenv rootdev /dev/nfs;" \ 487 "run setbootargs;" \ 488 "run setipargs;" \ 489 "tftp $loadaddr $bootfile;" \ 490 "tftp $fdtaddr $fdtfile;" \ 491 "bootm $loadaddr - $fdtaddr" 492 493 #define CONFIG_RAMBOOTCOMMAND \ 494 "setenv rootdev /dev/ram;" \ 495 "run setbootargs;" \ 496 "tftp $ramdiskaddr $ramdiskfile;" \ 497 "tftp $loadaddr $bootfile;" \ 498 "tftp $fdtaddr $fdtfile;" \ 499 "bootm $loadaddr $ramdiskaddr $fdtaddr" 500 501 #endif /* __CONFIG_H */ 502