1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2012 Keymile AG 4 * Gerlando Falauto <gerlando.falauto@keymile.com> 5 * 6 * Based on km8321-common.h, see respective copyright notice for credits 7 */ 8 9 #ifndef __CONFIG_KM8309_COMMON_H 10 #define __CONFIG_KM8309_COMMON_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_QE 1 /* Has QE */ 17 #define CONFIG_MPC830x 1 /* MPC830x family */ 18 #define CONFIG_MPC8309 1 /* MPC8309 CPU specific */ 19 20 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" 21 22 /* include common defines/options for all 83xx Keymile boards */ 23 #include "km83xx-common.h" 24 25 /* QE microcode/firmware address */ 26 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 27 /* between the u-boot partition and env */ 28 #ifndef CONFIG_SYS_QE_FW_ADDR 29 #define CONFIG_SYS_QE_FW_ADDR 0xF00C0000 30 #endif 31 32 /* 33 * System IO Config 34 */ 35 /* 0x14000180 SICR_1 */ 36 #define CONFIG_SYS_SICRL (0 \ 37 | SICR_1_UART1_UART1RTS \ 38 | SICR_1_I2C_CKSTOP \ 39 | SICR_1_IRQ_A_IRQ \ 40 | SICR_1_IRQ_B_IRQ \ 41 | SICR_1_GPIO_A_GPIO \ 42 | SICR_1_GPIO_B_GPIO \ 43 | SICR_1_GPIO_C_GPIO \ 44 | SICR_1_GPIO_D_GPIO \ 45 | SICR_1_GPIO_E_GPIO \ 46 | SICR_1_GPIO_F_GPIO \ 47 | SICR_1_USB_A_UART2S \ 48 | SICR_1_USB_B_UART2RTS \ 49 | SICR_1_FEC1_FEC1 \ 50 | SICR_1_FEC2_FEC2 \ 51 ) 52 53 /* 0x00080400 SICR_2 */ 54 #define CONFIG_SYS_SICRH (0 \ 55 | SICR_2_FEC3_FEC3 \ 56 | SICR_2_HDLC1_A_HDLC1 \ 57 | SICR_2_ELBC_A_LA \ 58 | SICR_2_ELBC_B_LCLK \ 59 | SICR_2_HDLC2_A_HDLC2 \ 60 | SICR_2_USB_D_GPIO \ 61 | SICR_2_PCI_PCI \ 62 | SICR_2_HDLC1_B_HDLC1 \ 63 | SICR_2_HDLC1_C_HDLC1 \ 64 | SICR_2_HDLC2_B_GPIO \ 65 | SICR_2_HDLC2_C_HDLC2 \ 66 | SICR_2_QUIESCE_B \ 67 ) 68 69 /* GPR_1 */ 70 #define CONFIG_SYS_GPR1 0x50008060 71 72 #define CONFIG_SYS_GP1DIR 0x00000000 73 #define CONFIG_SYS_GP1ODR 0x00000000 74 #define CONFIG_SYS_GP2DIR 0xFF000000 75 #define CONFIG_SYS_GP2ODR 0x00000000 76 77 /* 78 * Hardware Reset Configuration Word 79 */ 80 #define CONFIG_SYS_HRCW_LOW (\ 81 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ 82 HRCWL_DDR_TO_SCB_CLK_2X1 | \ 83 HRCWL_CSB_TO_CLKIN_2X1 | \ 84 HRCWL_CORE_TO_CSB_2X1 | \ 85 HRCWL_CE_PLL_VCO_DIV_2 | \ 86 HRCWL_CE_TO_PLL_1X3) 87 88 #define CONFIG_SYS_HRCW_HIGH (\ 89 HRCWH_PCI_AGENT | \ 90 HRCWH_PCI_ARBITER_DISABLE | \ 91 HRCWH_CORE_ENABLE | \ 92 HRCWH_FROM_0X00000100 | \ 93 HRCWH_BOOTSEQ_DISABLE | \ 94 HRCWH_SW_WATCHDOG_DISABLE | \ 95 HRCWH_ROM_LOC_LOCAL_16BIT | \ 96 HRCWH_BIG_ENDIAN | \ 97 HRCWH_LALE_NORMAL) 98 99 #define CONFIG_SYS_DDRCDR (\ 100 DDRCDR_EN | \ 101 DDRCDR_PZ_MAXZ | \ 102 DDRCDR_NZ_MAXZ | \ 103 DDRCDR_M_ODR) 104 105 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f 106 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ 107 SDRAM_CFG_32_BE | \ 108 SDRAM_CFG_SREN | \ 109 SDRAM_CFG_HSE) 110 111 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 112 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 113 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ 114 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) 115 116 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ 117 CSCONFIG_ODT_RD_NEVER | \ 118 CSCONFIG_ODT_WR_ONLY_CURRENT | \ 119 CSCONFIG_ROW_BIT_13 | \ 120 CSCONFIG_COL_BIT_10) 121 122 #define CONFIG_SYS_DDR_MODE 0x47860242 123 #define CONFIG_SYS_DDR_MODE2 0x8080c000 124 125 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ 126 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ 127 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ 128 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ 129 (0 << TIMING_CFG0_WWT_SHIFT) | \ 130 (0 << TIMING_CFG0_RRT_SHIFT) | \ 131 (0 << TIMING_CFG0_WRT_SHIFT) | \ 132 (0 << TIMING_CFG0_RWT_SHIFT)) 133 134 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ 135 (2 << TIMING_CFG1_WRTORD_SHIFT) | \ 136 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ 137 (3 << TIMING_CFG1_WRREC_SHIFT) | \ 138 (7 << TIMING_CFG1_REFREC_SHIFT) | \ 139 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ 140 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ 141 (3 << TIMING_CFG1_PRETOACT_SHIFT)) 142 143 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ 144 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ 145 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ 146 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ 147 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ 148 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ 149 (5 << TIMING_CFG2_CPO_SHIFT)) 150 151 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 152 153 #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 154 #define CONFIG_SYS_KMBEC_FPGA_SIZE 128 155 156 /* EEprom support */ 157 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 158 159 /* 160 * Local Bus Configuration & Clock Setup 161 */ 162 #define CONFIG_SYS_LCRR_DBYP 0x80000000 163 #define CONFIG_SYS_LCRR_EADC 0x00010000 164 #define CONFIG_SYS_LCRR_CLKDIV 0x00000002 165 166 #define CONFIG_SYS_LBC_LBCR 0x00000000 167 168 /* 169 * MMU Setup 170 */ 171 #define CONFIG_SYS_IBAT7L (0) 172 #define CONFIG_SYS_IBAT7U (0) 173 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 174 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 175 176 #endif /* __CONFIG_KM8309_COMMON_H */ 177