xref: /openbmc/u-boot/arch/arm/mach-sunxi/Kconfig (revision 85c3d463)
1if ARCH_SUNXI
2
3config SPL_LDSCRIPT
4	default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
5
6config IDENT_STRING
7	default " Allwinner Technology"
8
9config DRAM_SUN4I
10	bool
11	help
12	  Select this dram controller driver for Sun4/5/7i platforms,
13	  like A10/A13/A20.
14
15config DRAM_SUN6I
16	bool
17	help
18	  Select this dram controller driver for Sun6i platforms,
19	  like A31/A31s.
20
21config DRAM_SUN8I_A23
22	bool
23	help
24	  Select this dram controller driver for Sun8i platforms,
25	  for A23 SOC.
26
27config DRAM_SUN8I_A33
28	bool
29	help
30	  Select this dram controller driver for Sun8i platforms,
31	  for A33 SOC.
32
33config DRAM_SUN8I_A83T
34	bool
35	help
36	  Select this dram controller driver for Sun8i platforms,
37	  for A83T SOC.
38
39config DRAM_SUN9I
40	bool
41	help
42	  Select this dram controller driver for Sun9i platforms,
43	  like A80.
44
45config DRAM_SUN50I_H6
46	bool
47	help
48	  Select this dram controller driver for some sun50i platforms,
49	  like H6.
50
51config SUN6I_P2WI
52	bool "Allwinner sun6i internal P2WI controller"
53	help
54	  If you say yes to this option, support will be included for the
55	  P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
56	  SOCs.
57	  The P2WI looks like an SMBus controller (which supports only byte
58	  accesses), except that it only supports one slave device.
59	  This interface is used to connect to specific PMIC devices (like the
60	  AXP221).
61
62config SUN6I_PRCM
63	bool
64	help
65	  Support for the PRCM (Power/Reset/Clock Management) unit available
66	  in A31 SoC.
67
68config AXP_PMIC_BUS
69	bool "Sunxi AXP PMIC bus access helpers"
70	help
71	  Select this PMIC bus access helpers for Sunxi platform PRCM or other
72	  AXP family PMIC devices.
73
74config SUN8I_RSB
75	bool "Allwinner sunXi Reduced Serial Bus Driver"
76	help
77	  Say y here to enable support for Allwinner's Reduced Serial Bus
78	  (RSB) support. This controller is responsible for communicating
79	  with various RSB based devices, such as AXP223, AXP8XX PMICs,
80	  and AC100/AC200 ICs.
81
82config SUNXI_SRAM_ADDRESS
83	hex
84	default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
85	default 0x20000 if MACH_SUN50I_H6
86	default 0x0
87	---help---
88	Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
89	with the first SRAM region being located at address 0.
90	Some newer SoCs map the boot ROM at address 0 instead and move the
91	SRAM to a different address.
92
93config SUNXI_A64_TIMER_ERRATUM
94	bool
95
96# Note only one of these may be selected at a time! But hidden choices are
97# not supported by Kconfig
98config SUNXI_GEN_SUN4I
99	bool
100	---help---
101	Select this for sunxi SoCs which have resets and clocks set up
102	as the original A10 (mach-sun4i).
103
104config SUNXI_GEN_SUN6I
105	bool
106	---help---
107	Select this for sunxi SoCs which have sun6i like periphery, like
108	separate ahb reset control registers, custom pmic bus, new style
109	watchdog, etc.
110
111config SUNXI_DRAM_DW
112	bool
113	---help---
114	Select this for sunxi SoCs which uses a DRAM controller like the
115	DesignWare controller used in H3, mainly SoCs after H3, which do
116	not have official open-source DRAM initialization code, but can
117	use modified H3 DRAM initialization code.
118
119if SUNXI_DRAM_DW
120config SUNXI_DRAM_DW_16BIT
121	bool
122	---help---
123	Select this for sunxi SoCs with DesignWare DRAM controller and
124	have only 16-bit memory buswidth.
125
126config SUNXI_DRAM_DW_32BIT
127	bool
128	---help---
129	Select this for sunxi SoCs with DesignWare DRAM controller with
130	32-bit memory buswidth.
131endif
132
133config MACH_SUNXI_H3_H5
134	bool
135	select DM_I2C
136	select PHY_SUN4I_USB
137	select SUNXI_DE2
138	select SUNXI_DRAM_DW
139	select SUNXI_DRAM_DW_32BIT
140	select SUNXI_GEN_SUN6I
141	select SUPPORT_SPL
142
143# TODO: try out A80's 8GiB DRAM space
144config SUNXI_DRAM_MAX_SIZE
145	hex
146	default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
147	default 0x80000000
148
149choice
150	prompt "Sunxi SoC Variant"
151	optional
152
153config MACH_SUN4I
154	bool "sun4i (Allwinner A10)"
155	select CPU_V7A
156	select ARM_CORTEX_CPU_IS_UP
157	select DM_MMC if MMC
158	select DM_SCSI if SCSI
159	select PHY_SUN4I_USB
160	select DRAM_SUN4I
161	select SUNXI_GEN_SUN4I
162	select SUPPORT_SPL
163
164config MACH_SUN5I
165	bool "sun5i (Allwinner A13)"
166	select CPU_V7A
167	select ARM_CORTEX_CPU_IS_UP
168	select DM_MMC if MMC
169	select DRAM_SUN4I
170	select PHY_SUN4I_USB
171	select SUNXI_GEN_SUN4I
172	select SUPPORT_SPL
173	imply CONS_INDEX_2 if !DM_SERIAL
174
175config MACH_SUN6I
176	bool "sun6i (Allwinner A31)"
177	select CPU_V7A
178	select CPU_V7_HAS_NONSEC
179	select CPU_V7_HAS_VIRT
180	select ARCH_SUPPORT_PSCI
181	select DM_MMC if MMC
182	select DRAM_SUN6I
183	select PHY_SUN4I_USB
184	select SUN6I_P2WI
185	select SUN6I_PRCM
186	select SUNXI_GEN_SUN6I
187	select SUPPORT_SPL
188	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
189
190config MACH_SUN7I
191	bool "sun7i (Allwinner A20)"
192	select CPU_V7A
193	select CPU_V7_HAS_NONSEC
194	select CPU_V7_HAS_VIRT
195	select ARCH_SUPPORT_PSCI
196	select DRAM_SUN4I
197	select PHY_SUN4I_USB
198	select SUNXI_GEN_SUN4I
199	select SUPPORT_SPL
200	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
201
202config MACH_SUN8I_A23
203	bool "sun8i (Allwinner A23)"
204	select CPU_V7A
205	select CPU_V7_HAS_NONSEC
206	select CPU_V7_HAS_VIRT
207	select ARCH_SUPPORT_PSCI
208	select DM_MMC if MMC
209	select DRAM_SUN8I_A23
210	select PHY_SUN4I_USB
211	select SUNXI_GEN_SUN6I
212	select SUPPORT_SPL
213	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
214	imply CONS_INDEX_5 if !DM_SERIAL
215
216config MACH_SUN8I_A33
217	bool "sun8i (Allwinner A33)"
218	select CPU_V7A
219	select CPU_V7_HAS_NONSEC
220	select CPU_V7_HAS_VIRT
221	select ARCH_SUPPORT_PSCI
222	select DM_MMC if MMC
223	select DRAM_SUN8I_A33
224	select PHY_SUN4I_USB
225	select SUNXI_GEN_SUN6I
226	select SUPPORT_SPL
227	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
228	imply CONS_INDEX_5 if !DM_SERIAL
229
230config MACH_SUN8I_A83T
231	bool "sun8i (Allwinner A83T)"
232	select CPU_V7A
233	select DM_MMC if MMC
234	select DRAM_SUN8I_A83T
235	select PHY_SUN4I_USB
236	select SUNXI_GEN_SUN6I
237	select MMC_SUNXI_HAS_NEW_MODE
238	select MMC_SUNXI_HAS_MODE_SWITCH
239	select SUPPORT_SPL
240
241config MACH_SUN8I_H3
242	bool "sun8i (Allwinner H3)"
243	select CPU_V7A
244	select CPU_V7_HAS_NONSEC
245	select CPU_V7_HAS_VIRT
246	select ARCH_SUPPORT_PSCI
247	select MACH_SUNXI_H3_H5
248	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
249	select DM_MMC if MMC
250
251config MACH_SUN8I_R40
252	bool "sun8i (Allwinner R40)"
253	select CPU_V7A
254	select CPU_V7_HAS_NONSEC
255	select CPU_V7_HAS_VIRT
256	select ARCH_SUPPORT_PSCI
257	select SUNXI_GEN_SUN6I
258	select SUPPORT_SPL
259	select SUNXI_DRAM_DW
260	select SUNXI_DRAM_DW_32BIT
261
262config MACH_SUN8I_V3S
263	bool "sun8i (Allwinner V3s)"
264	select CPU_V7A
265	select CPU_V7_HAS_NONSEC
266	select CPU_V7_HAS_VIRT
267	select ARCH_SUPPORT_PSCI
268	select DM_MMC if MMC
269	select SUNXI_GEN_SUN6I
270	select SUNXI_DRAM_DW
271	select SUNXI_DRAM_DW_16BIT
272	select SUPPORT_SPL
273	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
274
275config MACH_SUN9I
276	bool "sun9i (Allwinner A80)"
277	select CPU_V7A
278	select DRAM_SUN9I
279	select SUN6I_PRCM
280	select SUNXI_GEN_SUN6I
281	select SUN8I_RSB
282	select SUPPORT_SPL
283	select DM_MMC if MMC
284
285config MACH_SUN50I
286	bool "sun50i (Allwinner A64)"
287	select ARM64
288	select DM_I2C
289	select DM_MMC if MMC
290	select PHY_SUN4I_USB
291	select SUN6I_PRCM
292	select SUNXI_DE2
293	select SUNXI_GEN_SUN6I
294	select MMC_SUNXI_HAS_NEW_MODE
295	select SUPPORT_SPL
296	select SUNXI_DRAM_DW
297	select SUNXI_DRAM_DW_32BIT
298	select FIT
299	select SPL_LOAD_FIT
300	select SUNXI_A64_TIMER_ERRATUM
301
302config MACH_SUN50I_H5
303	bool "sun50i (Allwinner H5)"
304	select ARM64
305	select MACH_SUNXI_H3_H5
306	select DM_MMC if MMC
307	select FIT
308	select SPL_LOAD_FIT
309
310config MACH_SUN50I_H6
311	bool "sun50i (Allwinner H6)"
312	select ARM64
313	select SUPPORT_SPL
314	select DM_MMC if MMC
315	select FIT
316	select SPL_LOAD_FIT
317	select DRAM_SUN50I_H6
318
319endchoice
320
321# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
322config MACH_SUN8I
323	bool
324	select SUN8I_RSB
325	select SUN6I_PRCM
326	default y if MACH_SUN8I_A23
327	default y if MACH_SUN8I_A33
328	default y if MACH_SUN8I_A83T
329	default y if MACH_SUNXI_H3_H5
330	default y if MACH_SUN8I_R40
331	default y if MACH_SUN8I_V3S
332
333config RESERVE_ALLWINNER_BOOT0_HEADER
334	bool "reserve space for Allwinner boot0 header"
335	select ENABLE_ARM_SOC_BOOT0_HOOK
336	---help---
337	Prepend a 1536 byte (empty) header to the U-Boot image file, to be
338	filled with magic values post build. The Allwinner provided boot0
339	blob relies on this information to load and execute U-Boot.
340	Only needed on 64-bit Allwinner boards so far when using boot0.
341
342config ARM_BOOT_HOOK_RMR
343	bool
344	depends on ARM64
345	default y
346	select ENABLE_ARM_SOC_BOOT0_HOOK
347	---help---
348	Insert some ARM32 code at the very beginning of the U-Boot binary
349	which uses an RMR register write to bring the core into AArch64 mode.
350	The very first instruction acts as a switch, since it's carefully
351	chosen to be a NOP in one mode and a branch in the other, so the
352	code would only be executed if not already in AArch64.
353	This allows both the SPL and the U-Boot proper to be entered in
354	either mode and switch to AArch64 if needed.
355
356if SUNXI_DRAM_DW
357config SUNXI_DRAM_DDR3
358	bool
359
360config SUNXI_DRAM_DDR2
361	bool
362
363config SUNXI_DRAM_LPDDR3
364	bool
365
366choice
367	prompt "DRAM Type and Timing"
368	default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
369	default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
370
371config SUNXI_DRAM_DDR3_1333
372	bool "DDR3 1333"
373	select SUNXI_DRAM_DDR3
374	depends on !MACH_SUN8I_V3S
375	---help---
376	This option is the original only supported memory type, which suits
377	many H3/H5/A64 boards available now.
378
379config SUNXI_DRAM_LPDDR3_STOCK
380	bool "LPDDR3 with Allwinner stock configuration"
381	select SUNXI_DRAM_LPDDR3
382	---help---
383	This option is the LPDDR3 timing used by the stock boot0 by
384	Allwinner.
385
386config SUNXI_DRAM_DDR2_V3S
387	bool "DDR2 found in V3s chip"
388	select SUNXI_DRAM_DDR2
389	depends on MACH_SUN8I_V3S
390	---help---
391	This option is only for the DDR2 memory chip which is co-packaged in
392	Allwinner V3s SoC.
393
394endchoice
395endif
396
397config DRAM_TYPE
398	int "sunxi dram type"
399	depends on MACH_SUN8I_A83T
400	default 3
401	---help---
402	Set the dram type, 3: DDR3, 7: LPDDR3
403
404config DRAM_CLK
405	int "sunxi dram clock speed"
406	default 792 if MACH_SUN9I
407	default 648 if MACH_SUN8I_R40
408	default 312 if MACH_SUN6I || MACH_SUN8I
409	default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
410		       MACH_SUN8I_V3S
411	default 672 if MACH_SUN50I
412	default 744 if MACH_SUN50I_H6
413	---help---
414	Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
415	must be a multiple of 24. For the sun9i (A80), the tested values
416	(for DDR3-1600) are 312 to 792.
417
418if MACH_SUN5I || MACH_SUN7I
419config DRAM_MBUS_CLK
420	int "sunxi mbus clock speed"
421	default 300
422	---help---
423	Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
424
425endif
426
427config DRAM_ZQ
428	int "sunxi dram zq value"
429	default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
430	default 127 if MACH_SUN7I
431	default 14779 if MACH_SUN8I_V3S
432	default 3881979 if MACH_SUN8I_R40 || MACH_SUN50I_H6
433	default 4145117 if MACH_SUN9I
434	default 3881915 if MACH_SUN50I
435	---help---
436	Set the dram zq value.
437
438config DRAM_ODT_EN
439	bool "sunxi dram odt enable"
440	default y if MACH_SUN8I_A23
441	default y if MACH_SUN8I_R40
442	default y if MACH_SUN50I
443	default y if MACH_SUN50I_H6
444	---help---
445	Select this to enable dram odt (on die termination).
446
447if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
448config DRAM_EMR1
449	int "sunxi dram emr1 value"
450	default 0 if MACH_SUN4I
451	default 4 if MACH_SUN5I || MACH_SUN7I
452	---help---
453	Set the dram controller emr1 value.
454
455config DRAM_TPR3
456	hex "sunxi dram tpr3 value"
457	default 0
458	---help---
459	Set the dram controller tpr3 parameter. This parameter configures
460	the delay on the command lane and also phase shifts, which are
461	applied for sampling incoming read data. The default value 0
462	means that no phase/delay adjustments are necessary. Properly
463	configuring this parameter increases reliability at high DRAM
464	clock speeds.
465
466config DRAM_DQS_GATING_DELAY
467	hex "sunxi dram dqs_gating_delay value"
468	default 0
469	---help---
470	Set the dram controller dqs_gating_delay parmeter. Each byte
471	encodes the DQS gating delay for each byte lane. The delay
472	granularity is 1/4 cycle. For example, the value 0x05060606
473	means that the delay is 5 quarter-cycles for one lane (1.25
474	cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
475	The default value 0 means autodetection. The results of hardware
476	autodetection are not very reliable and depend on the chip
477	temperature (sometimes producing different results on cold start
478	and warm reboot). But the accuracy of hardware autodetection
479	is usually good enough, unless running at really high DRAM
480	clocks speeds (up to 600MHz). If unsure, keep as 0.
481
482choice
483	prompt "sunxi dram timings"
484	default DRAM_TIMINGS_VENDOR_MAGIC
485	---help---
486	Select the timings of the DDR3 chips.
487
488config DRAM_TIMINGS_VENDOR_MAGIC
489	bool "Magic vendor timings from Android"
490	---help---
491	The same DRAM timings as in the Allwinner boot0 bootloader.
492
493config DRAM_TIMINGS_DDR3_1066F_1333H
494	bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
495	---help---
496	Use the timings of the standard JEDEC DDR3-1066F speed bin for
497	DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
498	for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
499	used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
500	or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
501	that down binning to DDR3-1066F is supported (because DDR3-1066F
502	uses a bit faster timings than DDR3-1333H).
503
504config DRAM_TIMINGS_DDR3_800E_1066G_1333J
505	bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
506	---help---
507	Use the timings of the slowest possible JEDEC speed bin for the
508	selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
509	DDR3-800E, DDR3-1066G or DDR3-1333J.
510
511endchoice
512
513endif
514
515if MACH_SUN8I_A23
516config DRAM_ODT_CORRECTION
517	int "sunxi dram odt correction value"
518	default 0
519	---help---
520	Set the dram odt correction value (range -255 - 255). In allwinner
521	fex files, this option is found in bits 8-15 of the u32 odt_en variable
522	in the [dram] section. When bit 31 of the odt_en variable is set
523	then the correction is negative. Usually the value for this is 0.
524endif
525
526config SYS_CLK_FREQ
527	default 1008000000 if MACH_SUN4I
528	default 1008000000 if MACH_SUN5I
529	default 1008000000 if MACH_SUN6I
530	default 912000000 if MACH_SUN7I
531	default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
532	default 1008000000 if MACH_SUN8I
533	default 1008000000 if MACH_SUN9I
534	default 888000000 if MACH_SUN50I_H6
535
536config SYS_CONFIG_NAME
537	default "sun4i" if MACH_SUN4I
538	default "sun5i" if MACH_SUN5I
539	default "sun6i" if MACH_SUN6I
540	default "sun7i" if MACH_SUN7I
541	default "sun8i" if MACH_SUN8I
542	default "sun9i" if MACH_SUN9I
543	default "sun50i" if MACH_SUN50I
544	default "sun50i" if MACH_SUN50I_H6
545
546config SYS_BOARD
547	default "sunxi"
548
549config SYS_SOC
550	default "sunxi"
551
552config UART0_PORT_F
553	bool "UART0 on MicroSD breakout board"
554	default n
555	---help---
556	Repurpose the SD card slot for getting access to the UART0 serial
557	console. Primarily useful only for low level u-boot debugging on
558	tablets, where normal UART0 is difficult to access and requires
559	device disassembly and/or soldering. As the SD card can't be used
560	at the same time, the system can be only booted in the FEL mode.
561	Only enable this if you really know what you are doing.
562
563config OLD_SUNXI_KERNEL_COMPAT
564	bool "Enable workarounds for booting old kernels"
565	default n
566	---help---
567	Set this to enable various workarounds for old kernels, this results in
568	sub-optimal settings for newer kernels, only enable if needed.
569
570config MACPWR
571	string "MAC power pin"
572	default ""
573	help
574	  Set the pin used to power the MAC. This takes a string in the format
575	  understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
576
577config MMC0_CD_PIN
578	string "Card detect pin for mmc0"
579	default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
580	default ""
581	---help---
582	Set the card detect pin for mmc0, leave empty to not use cd. This
583	takes a string in the format understood by sunxi_name_to_gpio, e.g.
584	PH1 for pin 1 of port H.
585
586config MMC1_CD_PIN
587	string "Card detect pin for mmc1"
588	default ""
589	---help---
590	See MMC0_CD_PIN help text.
591
592config MMC2_CD_PIN
593	string "Card detect pin for mmc2"
594	default ""
595	---help---
596	See MMC0_CD_PIN help text.
597
598config MMC3_CD_PIN
599	string "Card detect pin for mmc3"
600	default ""
601	---help---
602	See MMC0_CD_PIN help text.
603
604config MMC1_PINS
605	string "Pins for mmc1"
606	default ""
607	---help---
608	Set the pins used for mmc1, when applicable. This takes a string in the
609	format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
610
611config MMC2_PINS
612	string "Pins for mmc2"
613	default ""
614	---help---
615	See MMC1_PINS help text.
616
617config MMC3_PINS
618	string "Pins for mmc3"
619	default ""
620	---help---
621	See MMC1_PINS help text.
622
623config MMC_SUNXI_SLOT_EXTRA
624	int "mmc extra slot number"
625	default -1
626	---help---
627	sunxi builds always enable mmc0, some boards also have a second sdcard
628	slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
629	support for this.
630
631config INITIAL_USB_SCAN_DELAY
632	int "delay initial usb scan by x ms to allow builtin devices to init"
633	default 0
634	---help---
635	Some boards have on board usb devices which need longer than the
636	USB spec's 1 second to connect from board powerup. Set this config
637	option to a non 0 value to add an extra delay before the first usb
638	bus scan.
639
640config USB0_VBUS_PIN
641	string "Vbus enable pin for usb0 (otg)"
642	default ""
643	---help---
644	Set the Vbus enable pin for usb0 (otg). This takes a string in the
645	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
646
647config USB0_VBUS_DET
648	string "Vbus detect pin for usb0 (otg)"
649	default ""
650	---help---
651	Set the Vbus detect pin for usb0 (otg). This takes a string in the
652	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
653
654config USB0_ID_DET
655	string "ID detect pin for usb0 (otg)"
656	default ""
657	---help---
658	Set the ID detect pin for usb0 (otg). This takes a string in the
659	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
660
661config USB1_VBUS_PIN
662	string "Vbus enable pin for usb1 (ehci0)"
663	default "PH6" if MACH_SUN4I || MACH_SUN7I
664	default "PH27" if MACH_SUN6I
665	---help---
666	Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
667	a string in the format understood by sunxi_name_to_gpio, e.g.
668	PH1 for pin 1 of port H.
669
670config USB2_VBUS_PIN
671	string "Vbus enable pin for usb2 (ehci1)"
672	default "PH3" if MACH_SUN4I || MACH_SUN7I
673	default "PH24" if MACH_SUN6I
674	---help---
675	See USB1_VBUS_PIN help text.
676
677config USB3_VBUS_PIN
678	string "Vbus enable pin for usb3 (ehci2)"
679	default ""
680	---help---
681	See USB1_VBUS_PIN help text.
682
683config I2C0_ENABLE
684	bool "Enable I2C/TWI controller 0"
685	default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
686	default n if MACH_SUN6I || MACH_SUN8I
687	select CMD_I2C
688	---help---
689	This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
690	its clock and setting up the bus. This is especially useful on devices
691	with slaves connected to the bus or with pins exposed through e.g. an
692	expansion port/header.
693
694config I2C1_ENABLE
695	bool "Enable I2C/TWI controller 1"
696	default n
697	select CMD_I2C
698	---help---
699	See I2C0_ENABLE help text.
700
701config I2C2_ENABLE
702	bool "Enable I2C/TWI controller 2"
703	default n
704	select CMD_I2C
705	---help---
706	See I2C0_ENABLE help text.
707
708if MACH_SUN6I || MACH_SUN7I
709config I2C3_ENABLE
710	bool "Enable I2C/TWI controller 3"
711	default n
712	select CMD_I2C
713	---help---
714	See I2C0_ENABLE help text.
715endif
716
717if SUNXI_GEN_SUN6I
718config R_I2C_ENABLE
719	bool "Enable the PRCM I2C/TWI controller"
720	# This is used for the pmic on H3
721	default y if SY8106A_POWER
722	select CMD_I2C
723	---help---
724	Set this to y to enable the I2C controller which is part of the PRCM.
725endif
726
727if MACH_SUN7I
728config I2C4_ENABLE
729	bool "Enable I2C/TWI controller 4"
730	default n
731	select CMD_I2C
732	---help---
733	See I2C0_ENABLE help text.
734endif
735
736config AXP_GPIO
737	bool "Enable support for gpio-s on axp PMICs"
738	default n
739	---help---
740	Say Y here to enable support for the gpio pins of the axp PMIC ICs.
741
742config VIDEO_SUNXI
743	bool "Enable graphical uboot console on HDMI, LCD or VGA"
744	depends on !MACH_SUN8I_A83T
745	depends on !MACH_SUNXI_H3_H5
746	depends on !MACH_SUN8I_R40
747	depends on !MACH_SUN8I_V3S
748	depends on !MACH_SUN9I
749	depends on !MACH_SUN50I
750	depends on !MACH_SUN50I_H6
751	select VIDEO
752	imply VIDEO_DT_SIMPLEFB
753	default y
754	---help---
755	Say Y here to add support for using a cfb console on the HDMI, LCD
756	or VGA output found on most sunxi devices. See doc/README.video for
757	info on how to select the video output and mode.
758
759config VIDEO_HDMI
760	bool "HDMI output support"
761	depends on VIDEO_SUNXI && !MACH_SUN8I
762	default y
763	---help---
764	Say Y here to add support for outputting video over HDMI.
765
766config VIDEO_VGA
767	bool "VGA output support"
768	depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
769	default n
770	---help---
771	Say Y here to add support for outputting video over VGA.
772
773config VIDEO_VGA_VIA_LCD
774	bool "VGA via LCD controller support"
775	depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
776	default n
777	---help---
778	Say Y here to add support for external DACs connected to the parallel
779	LCD interface driving a VGA connector, such as found on the
780	Olimex A13 boards.
781
782config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
783	bool "Force sync active high for VGA via LCD controller support"
784	depends on VIDEO_VGA_VIA_LCD
785	default n
786	---help---
787	Say Y here if you've a board which uses opendrain drivers for the vga
788	hsync and vsync signals. Opendrain drivers cannot generate steep enough
789	positive edges for a stable video output, so on boards with opendrain
790	drivers the sync signals must always be active high.
791
792config VIDEO_VGA_EXTERNAL_DAC_EN
793	string "LCD panel power enable pin"
794	depends on VIDEO_VGA_VIA_LCD
795	default ""
796	---help---
797	Set the enable pin for the external VGA DAC. This takes a string in the
798	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
799
800config VIDEO_COMPOSITE
801	bool "Composite video output support"
802	depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
803	default n
804	---help---
805	Say Y here to add support for outputting composite video.
806
807config VIDEO_LCD_MODE
808	string "LCD panel timing details"
809	depends on VIDEO_SUNXI
810	default ""
811	---help---
812	LCD panel timing details string, leave empty if there is no LCD panel.
813	This is in drivers/video/videomodes.c: video_get_params() format, e.g.
814	x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
815	Also see: http://linux-sunxi.org/LCD
816
817config VIDEO_LCD_DCLK_PHASE
818	int "LCD panel display clock phase"
819	depends on VIDEO_SUNXI || DM_VIDEO
820	default 1
821	---help---
822	Select LCD panel display clock phase shift, range 0-3.
823
824config VIDEO_LCD_POWER
825	string "LCD panel power enable pin"
826	depends on VIDEO_SUNXI
827	default ""
828	---help---
829	Set the power enable pin for the LCD panel. This takes a string in the
830	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
831
832config VIDEO_LCD_RESET
833	string "LCD panel reset pin"
834	depends on VIDEO_SUNXI
835	default ""
836	---help---
837	Set the reset pin for the LCD panel. This takes a string in the format
838	understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
839
840config VIDEO_LCD_BL_EN
841	string "LCD panel backlight enable pin"
842	depends on VIDEO_SUNXI
843	default ""
844	---help---
845	Set the backlight enable pin for the LCD panel. This takes a string in the
846	the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
847	port H.
848
849config VIDEO_LCD_BL_PWM
850	string "LCD panel backlight pwm pin"
851	depends on VIDEO_SUNXI
852	default ""
853	---help---
854	Set the backlight pwm pin for the LCD panel. This takes a string in the
855	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
856
857config VIDEO_LCD_BL_PWM_ACTIVE_LOW
858	bool "LCD panel backlight pwm is inverted"
859	depends on VIDEO_SUNXI
860	default y
861	---help---
862	Set this if the backlight pwm output is active low.
863
864config VIDEO_LCD_PANEL_I2C
865	bool "LCD panel needs to be configured via i2c"
866	depends on VIDEO_SUNXI
867	default n
868	select CMD_I2C
869	---help---
870	Say y here if the LCD panel needs to be configured via i2c. This
871	will add a bitbang i2c controller using gpios to talk to the LCD.
872
873config VIDEO_LCD_PANEL_I2C_SDA
874	string "LCD panel i2c interface SDA pin"
875	depends on VIDEO_LCD_PANEL_I2C
876	default "PG12"
877	---help---
878	Set the SDA pin for the LCD i2c interface. This takes a string in the
879	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
880
881config VIDEO_LCD_PANEL_I2C_SCL
882	string "LCD panel i2c interface SCL pin"
883	depends on VIDEO_LCD_PANEL_I2C
884	default "PG10"
885	---help---
886	Set the SCL pin for the LCD i2c interface. This takes a string in the
887	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
888
889
890# Note only one of these may be selected at a time! But hidden choices are
891# not supported by Kconfig
892config VIDEO_LCD_IF_PARALLEL
893	bool
894
895config VIDEO_LCD_IF_LVDS
896	bool
897
898config SUNXI_DE2
899	bool
900	default n
901
902config VIDEO_DE2
903	bool "Display Engine 2 video driver"
904	depends on SUNXI_DE2
905	select DM_VIDEO
906	select DISPLAY
907	imply VIDEO_DT_SIMPLEFB
908	default y
909	---help---
910	Say y here if you want to build DE2 video driver which is present on
911	newer SoCs. Currently only HDMI output is supported.
912
913
914choice
915	prompt "LCD panel support"
916	depends on VIDEO_SUNXI
917	---help---
918	Select which type of LCD panel to support.
919
920config VIDEO_LCD_PANEL_PARALLEL
921	bool "Generic parallel interface LCD panel"
922	select VIDEO_LCD_IF_PARALLEL
923
924config VIDEO_LCD_PANEL_LVDS
925	bool "Generic lvds interface LCD panel"
926	select VIDEO_LCD_IF_LVDS
927
928config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
929	bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
930	select VIDEO_LCD_SSD2828
931	select VIDEO_LCD_IF_PARALLEL
932	---help---
933	7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
934
935config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
936	bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
937	select VIDEO_LCD_ANX9804
938	select VIDEO_LCD_IF_PARALLEL
939	select VIDEO_LCD_PANEL_I2C
940	---help---
941	Select this for eDP LCD panels with 4 lanes running at 1.62G,
942	connected via an ANX9804 bridge chip.
943
944config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
945	bool "Hitachi tx18d42vm LCD panel"
946	select VIDEO_LCD_HITACHI_TX18D42VM
947	select VIDEO_LCD_IF_LVDS
948	---help---
949	7.85" 1024x768 Hitachi tx18d42vm LCD panel support
950
951config VIDEO_LCD_TL059WV5C0
952	bool "tl059wv5c0 LCD panel"
953	select VIDEO_LCD_PANEL_I2C
954	select VIDEO_LCD_IF_PARALLEL
955	---help---
956	6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
957	Aigo M60/M608/M606 tablets.
958
959endchoice
960
961config SATAPWR
962	string "SATA power pin"
963	default ""
964	help
965	  Set the pins used to power the SATA. This takes a string in the
966	  format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
967	  port H.
968
969config GMAC_TX_DELAY
970	int "GMAC Transmit Clock Delay Chain"
971	default 0
972	---help---
973	Set the GMAC Transmit Clock Delay Chain value.
974
975config SPL_STACK_R_ADDR
976	default 0x4fe00000 if MACH_SUN4I
977	default 0x4fe00000 if MACH_SUN5I
978	default 0x4fe00000 if MACH_SUN6I
979	default 0x4fe00000 if MACH_SUN7I
980	default 0x4fe00000 if MACH_SUN8I
981	default 0x2fe00000 if MACH_SUN9I
982	default 0x4fe00000 if MACH_SUN50I
983	default 0x4fe00000 if MACH_SUN50I_H6
984
985config SPL_SPI_SUNXI
986	bool "Support for SPI Flash on Allwinner SoCs in SPL"
987	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
988	help
989	  Enable support for SPI Flash. This option allows SPL to read from
990	  sunxi SPI Flash. It uses the same method as the boot ROM, so does
991	  not need any extra configuration.
992
993config PINE64_DT_SELECTION
994	bool "Enable Pine64 device tree selection code"
995	depends on MACH_SUN50I
996	help
997	  The original Pine A64 and Pine A64+ are similar but different
998	  boards and can be differed by the DRAM size. Pine A64 has
999	  512MiB DRAM, and Pine A64+ has 1GiB or 2GiB. By selecting this
1000	  option, the device tree selection code specific to Pine64 which
1001	  utilizes the DRAM size will be enabled.
1002
1003endif
1004