1config ARCH_LS1012A 2 bool 3 select ARMV8_SET_SMPEN 4 select ARM_ERRATA_855873 if !TFABOOT 5 select FSL_LAYERSCAPE 6 select FSL_LSCH2 7 select SYS_FSL_SRDS_1 8 select SYS_HAS_SERDES 9 select SYS_FSL_DDR_BE 10 select SYS_FSL_MMDC 11 select SYS_FSL_ERRATUM_A010315 12 select SYS_FSL_ERRATUM_A009798 13 select SYS_FSL_ERRATUM_A008997 14 select SYS_FSL_ERRATUM_A009007 15 select SYS_FSL_ERRATUM_A009008 16 select ARCH_EARLY_INIT_R 17 select BOARD_EARLY_INIT_F 18 select SYS_I2C_MXC 19 select SYS_I2C_MXC_I2C1 20 select SYS_I2C_MXC_I2C2 21 imply PANIC_HANG 22 23config ARCH_LS1043A 24 bool 25 select ARMV8_SET_SMPEN 26 select ARM_ERRATA_855873 if !TFABOOT 27 select FSL_LAYERSCAPE 28 select FSL_LSCH2 29 select SYS_FSL_SRDS_1 30 select SYS_HAS_SERDES 31 select SYS_FSL_DDR 32 select SYS_FSL_DDR_BE 33 select SYS_FSL_DDR_VER_50 34 select SYS_FSL_ERRATUM_A008850 if !TFABOOT 35 select SYS_FSL_ERRATUM_A008997 36 select SYS_FSL_ERRATUM_A009007 37 select SYS_FSL_ERRATUM_A009008 38 select SYS_FSL_ERRATUM_A009660 if !TFABOOT 39 select SYS_FSL_ERRATUM_A009663 if !TFABOOT 40 select SYS_FSL_ERRATUM_A009798 41 select SYS_FSL_ERRATUM_A009929 42 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 43 select SYS_FSL_ERRATUM_A010315 44 select SYS_FSL_ERRATUM_A010539 45 select SYS_FSL_HAS_DDR3 46 select SYS_FSL_HAS_DDR4 47 select ARCH_EARLY_INIT_R 48 select BOARD_EARLY_INIT_F 49 select SYS_I2C_MXC 50 select SYS_I2C_MXC_I2C1 51 select SYS_I2C_MXC_I2C2 52 select SYS_I2C_MXC_I2C3 53 select SYS_I2C_MXC_I2C4 54 imply CMD_PCI 55 56config ARCH_LS1046A 57 bool 58 select ARMV8_SET_SMPEN 59 select FSL_LAYERSCAPE 60 select FSL_LSCH2 61 select SYS_FSL_SRDS_1 62 select SYS_HAS_SERDES 63 select SYS_FSL_DDR 64 select SYS_FSL_DDR_BE 65 select SYS_FSL_DDR_VER_50 66 select SYS_FSL_ERRATUM_A008336 if !TFABOOT 67 select SYS_FSL_ERRATUM_A008511 if !TFABOOT 68 select SYS_FSL_ERRATUM_A008850 if !TFABOOT 69 select SYS_FSL_ERRATUM_A008997 70 select SYS_FSL_ERRATUM_A009007 71 select SYS_FSL_ERRATUM_A009008 72 select SYS_FSL_ERRATUM_A009798 73 select SYS_FSL_ERRATUM_A009801 74 select SYS_FSL_ERRATUM_A009803 if !TFABOOT 75 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 76 select SYS_FSL_ERRATUM_A010165 if !TFABOOT 77 select SYS_FSL_ERRATUM_A010539 78 select SYS_FSL_HAS_DDR4 79 select SYS_FSL_SRDS_2 80 select ARCH_EARLY_INIT_R 81 select BOARD_EARLY_INIT_F 82 select SYS_I2C_MXC 83 select SYS_I2C_MXC_I2C1 84 select SYS_I2C_MXC_I2C2 85 select SYS_I2C_MXC_I2C3 86 select SYS_I2C_MXC_I2C4 87 imply SCSI 88 imply SCSI_AHCI 89 90config ARCH_LS1088A 91 bool 92 select ARMV8_SET_SMPEN 93 select ARM_ERRATA_855873 if !TFABOOT 94 select FSL_LAYERSCAPE 95 select FSL_LSCH3 96 select SYS_FSL_SRDS_1 97 select SYS_HAS_SERDES 98 select SYS_FSL_DDR 99 select SYS_FSL_DDR_LE 100 select SYS_FSL_DDR_VER_50 101 select SYS_FSL_EC1 102 select SYS_FSL_EC2 103 select SYS_FSL_ERRATUM_A009803 if !TFABOOT 104 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 105 select SYS_FSL_ERRATUM_A010165 if !TFABOOT 106 select SYS_FSL_ERRATUM_A008511 if !TFABOOT 107 select SYS_FSL_ERRATUM_A008850 if !TFABOOT 108 select SYS_FSL_ERRATUM_A009007 109 select SYS_FSL_HAS_CCI400 110 select SYS_FSL_HAS_DDR4 111 select SYS_FSL_HAS_RGMII 112 select SYS_FSL_HAS_SEC 113 select SYS_FSL_SEC_COMPAT_5 114 select SYS_FSL_SEC_LE 115 select SYS_FSL_SRDS_1 116 select SYS_FSL_SRDS_2 117 select FSL_TZASC_1 118 select FSL_TZASC_400 119 select FSL_TZPC_BP147 120 select ARCH_EARLY_INIT_R 121 select BOARD_EARLY_INIT_F 122 select SYS_I2C_MXC 123 select SYS_I2C_MXC_I2C1 124 select SYS_I2C_MXC_I2C2 125 select SYS_I2C_MXC_I2C3 126 select SYS_I2C_MXC_I2C4 127 imply SCSI 128 imply PANIC_HANG 129 130config ARCH_LS2080A 131 bool 132 select ARMV8_SET_SMPEN 133 select ARM_ERRATA_826974 134 select ARM_ERRATA_828024 135 select ARM_ERRATA_829520 136 select ARM_ERRATA_833471 137 select FSL_LAYERSCAPE 138 select FSL_LSCH3 139 select SYS_FSL_SRDS_1 140 select SYS_HAS_SERDES 141 select SYS_FSL_DDR 142 select SYS_FSL_DDR_LE 143 select SYS_FSL_DDR_VER_50 144 select SYS_FSL_HAS_CCN504 145 select SYS_FSL_HAS_DP_DDR 146 select SYS_FSL_HAS_SEC 147 select SYS_FSL_HAS_DDR4 148 select SYS_FSL_SEC_COMPAT_5 149 select SYS_FSL_SEC_LE 150 select SYS_FSL_SRDS_2 151 select FSL_TZASC_1 152 select FSL_TZASC_2 153 select FSL_TZASC_400 154 select FSL_TZPC_BP147 155 select SYS_FSL_ERRATUM_A008336 if !TFABOOT 156 select SYS_FSL_ERRATUM_A008511 if !TFABOOT 157 select SYS_FSL_ERRATUM_A008514 if !TFABOOT 158 select SYS_FSL_ERRATUM_A008585 159 select SYS_FSL_ERRATUM_A008997 160 select SYS_FSL_ERRATUM_A009007 161 select SYS_FSL_ERRATUM_A009008 162 select SYS_FSL_ERRATUM_A009635 163 select SYS_FSL_ERRATUM_A009663 if !TFABOOT 164 select SYS_FSL_ERRATUM_A009798 165 select SYS_FSL_ERRATUM_A009801 166 select SYS_FSL_ERRATUM_A009803 if !TFABOOT 167 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 168 select SYS_FSL_ERRATUM_A010165 if !TFABOOT 169 select SYS_FSL_ERRATUM_A009203 170 select ARCH_EARLY_INIT_R 171 select BOARD_EARLY_INIT_F 172 select SYS_I2C_MXC 173 select SYS_I2C_MXC_I2C1 174 select SYS_I2C_MXC_I2C2 175 select SYS_I2C_MXC_I2C3 176 select SYS_I2C_MXC_I2C4 177 imply DISTRO_DEFAULTS 178 imply PANIC_HANG 179 180config ARCH_LX2160A 181 bool 182 select ARMV8_SET_SMPEN 183 select FSL_LSCH3 184 select NXP_LSCH3_2 185 select SYS_HAS_SERDES 186 select SYS_FSL_SRDS_1 187 select SYS_FSL_SRDS_2 188 select SYS_NXP_SRDS_3 189 select SYS_FSL_DDR 190 select SYS_FSL_DDR_LE 191 select SYS_FSL_DDR_VER_50 192 select SYS_FSL_EC1 193 select SYS_FSL_EC2 194 select SYS_FSL_HAS_RGMII 195 select SYS_FSL_HAS_SEC 196 select SYS_FSL_HAS_CCN508 197 select SYS_FSL_HAS_DDR4 198 select SYS_FSL_SEC_COMPAT_5 199 select SYS_FSL_SEC_LE 200 select ARCH_EARLY_INIT_R 201 select BOARD_EARLY_INIT_F 202 select SYS_I2C_MXC 203 select SYS_I2C_MXC_I2C1 204 select SYS_I2C_MXC_I2C2 205 select SYS_I2C_MXC_I2C3 206 select SYS_I2C_MXC_I2C4 207 select SYS_I2C_MXC_I2C5 208 select SYS_I2C_MXC_I2C6 209 select SYS_I2C_MXC_I2C7 210 select SYS_I2C_MXC_I2C8 211 imply DISTRO_DEFAULTS 212 imply PANIC_HANG 213 imply SCSI 214 imply SCSI_AHCI 215 216config FSL_LSCH2 217 bool 218 select SYS_FSL_HAS_CCI400 219 select SYS_FSL_HAS_SEC 220 select SYS_FSL_SEC_COMPAT_5 221 select SYS_FSL_SEC_BE 222 223config FSL_LSCH3 224 bool 225 226config NXP_LSCH3_2 227 bool 228 229config FSL_MC_ENET 230 bool "Management Complex network" 231 depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A 232 default y 233 select RESV_RAM 234 help 235 Enable Management Complex (MC) network 236 237menu "Layerscape architecture" 238 depends on FSL_LSCH2 || FSL_LSCH3 239 240config FSL_LAYERSCAPE 241 bool 242 243config FSL_PCIE_COMPAT 244 string "PCIe compatible of Kernel DT" 245 depends on PCIE_LAYERSCAPE 246 default "fsl,ls1012a-pcie" if ARCH_LS1012A 247 default "fsl,ls1043a-pcie" if ARCH_LS1043A 248 default "fsl,ls1046a-pcie" if ARCH_LS1046A 249 default "fsl,ls2080a-pcie" if ARCH_LS2080A 250 default "fsl,ls1088a-pcie" if ARCH_LS1088A 251 default "fsl,lx2160a-pcie" if ARCH_LX2160A 252 help 253 This compatible is used to find pci controller node in Kernel DT 254 to complete fixup. 255 256config HAS_FEATURE_GIC64K_ALIGN 257 bool 258 default y if ARCH_LS1043A 259 260config HAS_FEATURE_ENHANCED_MSI 261 bool 262 default y if ARCH_LS1043A 263 264menu "Layerscape PPA" 265config FSL_LS_PPA 266 bool "FSL Layerscape PPA firmware support" 267 depends on !ARMV8_PSCI 268 select ARMV8_SEC_FIRMWARE_SUPPORT 269 select SEC_FIRMWARE_ARMV8_PSCI 270 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 271 help 272 The FSL Primary Protected Application (PPA) is a software component 273 which is loaded during boot stage, and then remains resident in RAM 274 and runs in the TrustZone after boot. 275 Say y to enable it. 276 277config SPL_FSL_LS_PPA 278 bool "FSL Layerscape PPA firmware support for SPL build" 279 depends on !ARMV8_PSCI 280 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT 281 select SEC_FIRMWARE_ARMV8_PSCI 282 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 283 help 284 The FSL Primary Protected Application (PPA) is a software component 285 which is loaded during boot stage, and then remains resident in RAM 286 and runs in the TrustZone after boot. This is to load PPA during SPL 287 stage instead of the RAM version of U-Boot. Once PPA is initialized, 288 the rest of U-Boot (including RAM version) runs at EL2. 289choice 290 prompt "FSL Layerscape PPA firmware loading-media select" 291 depends on FSL_LS_PPA 292 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT 293 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT 294 default SYS_LS_PPA_FW_IN_XIP 295 296config SYS_LS_PPA_FW_IN_XIP 297 bool "XIP" 298 help 299 Say Y here if the PPA firmware locate at XIP flash, such 300 as NOR or QSPI flash. 301 302config SYS_LS_PPA_FW_IN_MMC 303 bool "eMMC or SD Card" 304 help 305 Say Y here if the PPA firmware locate at eMMC/SD card. 306 307config SYS_LS_PPA_FW_IN_NAND 308 bool "NAND" 309 help 310 Say Y here if the PPA firmware locate at NAND flash. 311 312endchoice 313 314config LS_PPA_ESBC_HDR_SIZE 315 hex "Length of PPA ESBC header" 316 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP 317 default 0x2000 318 help 319 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or 320 NAND to memory to validate PPA image. 321 322endmenu 323 324config SYS_FSL_ERRATUM_A008997 325 bool "Workaround for USB PHY erratum A008997" 326 327config SYS_FSL_ERRATUM_A009007 328 bool 329 help 330 Workaround for USB PHY erratum A009007 331 332config SYS_FSL_ERRATUM_A009008 333 bool "Workaround for USB PHY erratum A009008" 334 335config SYS_FSL_ERRATUM_A009798 336 bool "Workaround for USB PHY erratum A009798" 337 338config SYS_FSL_ERRATUM_A010315 339 bool "Workaround for PCIe erratum A010315" 340 341config SYS_FSL_ERRATUM_A010539 342 bool "Workaround for PIN MUX erratum A010539" 343 344config MAX_CPUS 345 int "Maximum number of CPUs permitted for Layerscape" 346 default 4 if ARCH_LS1043A 347 default 4 if ARCH_LS1046A 348 default 16 if ARCH_LS2080A 349 default 8 if ARCH_LS1088A 350 default 16 if ARCH_LX2160A 351 default 1 352 help 353 Set this number to the maximum number of possible CPUs in the SoC. 354 SoCs may have multiple clusters with each cluster may have multiple 355 ports. If some ports are reserved but higher ports are used for 356 cores, count the reserved ports. This will allocate enough memory 357 in spin table to properly handle all cores. 358 359config EMC2305 360 bool "Fan controller" 361 help 362 Enable the EMC2305 fan controller for configuration of fan 363 speed. 364 365config SECURE_BOOT 366 bool "Secure Boot" 367 help 368 Enable Freescale Secure Boot feature 369 370config QSPI_AHB_INIT 371 bool "Init the QSPI AHB bus" 372 help 373 The default setting for QSPI AHB bus just support 3bytes addressing. 374 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 375 bus for those flashes to support the full QSPI flash size. 376 377config SYS_CCI400_OFFSET 378 hex "Offset for CCI400 base" 379 depends on SYS_FSL_HAS_CCI400 380 default 0x3090000 if ARCH_LS1088A 381 default 0x180000 if FSL_LSCH2 382 help 383 Offset for CCI400 base 384 CCI400 base addr = CCSRBAR + CCI400_OFFSET 385 386config SYS_FSL_IFC_BANK_COUNT 387 int "Maximum banks of Integrated flash controller" 388 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A 389 default 4 if ARCH_LS1043A 390 default 4 if ARCH_LS1046A 391 default 8 if ARCH_LS2080A || ARCH_LS1088A 392 393config SYS_FSL_HAS_CCI400 394 bool 395 396config SYS_FSL_HAS_CCN504 397 bool 398 399config SYS_FSL_HAS_CCN508 400 bool 401 402config SYS_FSL_HAS_DP_DDR 403 bool 404 405config SYS_FSL_SRDS_1 406 bool 407 408config SYS_FSL_SRDS_2 409 bool 410 411config SYS_NXP_SRDS_3 412 bool 413 414config SYS_HAS_SERDES 415 bool 416 417config FSL_TZASC_1 418 bool 419 420config FSL_TZASC_2 421 bool 422 423config FSL_TZASC_400 424 bool 425 426config FSL_TZPC_BP147 427 bool 428endmenu 429 430menu "Layerscape clock tree configuration" 431 depends on FSL_LSCH2 || FSL_LSCH3 432 433config SYS_FSL_CLK 434 bool "Enable clock tree initialization" 435 default y 436 437config CLUSTER_CLK_FREQ 438 int "Reference clock of core cluster" 439 depends on ARCH_LS1012A 440 default 100000000 441 help 442 This number is the reference clock frequency of core PLL. 443 For most platforms, the core PLL and Platform PLL have the same 444 reference clock, but for some platforms, LS1012A for instance, 445 they are provided sepatately. 446 447config SYS_FSL_PCLK_DIV 448 int "Platform clock divider" 449 default 1 if ARCH_LS1043A 450 default 1 if ARCH_LS1046A 451 default 1 if ARCH_LS1088A 452 default 2 453 help 454 This is the divider that is used to derive Platform clock from 455 Platform PLL, in another word: 456 Platform_clk = Platform_PLL_freq / this_divider 457 458config SYS_FSL_DSPI_CLK_DIV 459 int "DSPI clock divider" 460 default 1 if ARCH_LS1043A 461 default 2 462 help 463 This is the divider that is used to derive DSPI clock from Platform 464 clock, in another word DSPI_clk = Platform_clk / this_divider. 465 466config SYS_FSL_DUART_CLK_DIV 467 int "DUART clock divider" 468 default 1 if ARCH_LS1043A 469 default 4 if ARCH_LX2160A 470 default 2 471 help 472 This is the divider that is used to derive DUART clock from Platform 473 clock, in another word DUART_clk = Platform_clk / this_divider. 474 475config SYS_FSL_I2C_CLK_DIV 476 int "I2C clock divider" 477 default 1 if ARCH_LS1043A 478 default 2 479 help 480 This is the divider that is used to derive I2C clock from Platform 481 clock, in another word I2C_clk = Platform_clk / this_divider. 482 483config SYS_FSL_IFC_CLK_DIV 484 int "IFC clock divider" 485 default 1 if ARCH_LS1043A 486 default 2 487 help 488 This is the divider that is used to derive IFC clock from Platform 489 clock, in another word IFC_clk = Platform_clk / this_divider. 490 491config SYS_FSL_LPUART_CLK_DIV 492 int "LPUART clock divider" 493 default 1 if ARCH_LS1043A 494 default 2 495 help 496 This is the divider that is used to derive LPUART clock from Platform 497 clock, in another word LPUART_clk = Platform_clk / this_divider. 498 499config SYS_FSL_SDHC_CLK_DIV 500 int "SDHC clock divider" 501 default 1 if ARCH_LS1043A 502 default 1 if ARCH_LS1012A 503 default 2 504 help 505 This is the divider that is used to derive SDHC clock from Platform 506 clock, in another word SDHC_clk = Platform_clk / this_divider. 507 508config SYS_FSL_QMAN_CLK_DIV 509 int "QMAN clock divider" 510 default 1 if ARCH_LS1043A 511 default 2 512 help 513 This is the divider that is used to derive QMAN clock from Platform 514 clock, in another word QMAN_clk = Platform_clk / this_divider. 515endmenu 516 517config RESV_RAM 518 bool 519 help 520 Reserve memory from the top, tracked by gd->arch.resv_ram. This 521 reserved RAM can be used by special driver that resides in memory 522 after U-Boot exits. It's up to implementation to allocate and allow 523 access to this reserved memory. For example, the reserved RAM can 524 be at the high end of physical memory. The reserve RAM may be 525 excluded from memory bank(s) passed to OS, or marked as reserved. 526 527config SYS_FSL_EC1 528 bool 529 help 530 Ethernet controller 1, this is connected to 531 MAC17 for LX2160A or to MAC3 for other SoCs 532 Provides DPAA2 capabilities 533 534config SYS_FSL_EC2 535 bool 536 help 537 Ethernet controller 2, this is connected to 538 MAC18 for LX2160A or to MAC4 for other SoCs 539 Provides DPAA2 capabilities 540 541config SYS_FSL_ERRATUM_A008336 542 bool 543 544config SYS_FSL_ERRATUM_A008514 545 bool 546 547config SYS_FSL_ERRATUM_A008585 548 bool 549 550config SYS_FSL_ERRATUM_A008850 551 bool 552 553config SYS_FSL_ERRATUM_A009203 554 bool 555 556config SYS_FSL_ERRATUM_A009635 557 bool 558 559config SYS_FSL_ERRATUM_A009660 560 bool 561 562config SYS_FSL_ERRATUM_A009929 563 bool 564 565 566config SYS_FSL_HAS_RGMII 567 bool 568 depends on SYS_FSL_EC1 || SYS_FSL_EC2 569 570 571config SYS_MC_RSV_MEM_ALIGN 572 hex "Management Complex reserved memory alignment" 573 depends on RESV_RAM 574 default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A 575 help 576 Reserved memory needs to be aligned for MC to use. Default value 577 is 512MB. 578 579config SPL_LDSCRIPT 580 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 581 582config HAS_FSL_XHCI_USB 583 bool 584 default y if ARCH_LS1043A || ARCH_LS1046A 585 help 586 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use 587 pins, select it when the pins are assigned to USB. 588 589config TFABOOT 590 bool "Support for booting from TFA" 591 default n 592 help 593 Enabling this will make a U-Boot binary that is capable of being 594 booted via TFA. 595