xref: /openbmc/u-boot/include/configs/ipam390.h (revision b71d9e8b)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
4  * Based on:
5  * U-Boot:include/configs/da850evm.h
6  *
7  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
8  *
9  * Based on davinci_dvevm.h. Original Copyrights follow:
10  *
11  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
12  */
13 
14 #ifndef __CONFIG_H
15 #define __CONFIG_H
16 
17 /*
18  * Board
19  */
20 
21 /*
22  * SoC Configuration
23  */
24 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
25 #define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
26 #define CONFIG_SYS_OSCIN_FREQ		24000000
27 #define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
28 #define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
29 
30 /*
31  * Memory Info
32  */
33 #define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
34 #define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
35 #define PHYS_SDRAM_1_SIZE	(128 << 20) /* SDRAM size 128MB */
36 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
37 
38 /* memtest start addr */
39 #define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x2000000)
40 
41 /* memtest will be run on 16MB */
42 #define CONFIG_SYS_MEMTEST_END	(CONFIG_SYS_MEMTEST_START + 16 * 1024 * 1024)
43 
44 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (	\
45 	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
46 	DAVINCI_SYSCFG_SUSPSRC_UART2 |		\
47 	DAVINCI_SYSCFG_SUSPSRC_UART0 |		\
48 	DAVINCI_SYSCFG_SUSPSRC_EMAC)
49 
50 /*
51  * PLL configuration
52  */
53 
54 #define CONFIG_SYS_DA850_PLL0_PLLM     24
55 #define CONFIG_SYS_DA850_PLL1_PLLM     24
56 
57 /*
58  * DDR2 memory configuration
59  */
60 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
61 					DV_DDR_PHY_EXT_STRBEN | \
62 					(0x2 << DV_DDR_PHY_RD_LATENCY_SHIFT))
63 #define CONFIG_SYS_DA850_DDR2_SDRCR	0x00000498
64 
65 #define CONFIG_SYS_DA850_DDR2_SDBCR2	0x00000004
66 #define CONFIG_SYS_DA850_DDR2_PBBPR	0x00000020
67 
68 #define CONFIG_SYS_DA850_DDR2_SDTIMR (		\
69 	(13 << DV_DDR_SDTMR1_RFC_SHIFT) |	\
70 	(2 << DV_DDR_SDTMR1_RP_SHIFT) |		\
71 	(2 << DV_DDR_SDTMR1_RCD_SHIFT) |	\
72 	(2 << DV_DDR_SDTMR1_WR_SHIFT) |		\
73 	(5 << DV_DDR_SDTMR1_RAS_SHIFT) |	\
74 	(8 << DV_DDR_SDTMR1_RC_SHIFT) |		\
75 	(1 << DV_DDR_SDTMR1_RRD_SHIFT) |	\
76 	(1 << DV_DDR_SDTMR1_WTR_SHIFT))
77 
78 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (		\
79 	(8 << DV_DDR_SDTMR2_RASMAX_SHIFT) |	\
80 	(2 << DV_DDR_SDTMR2_XP_SHIFT) |		\
81 	(0 << DV_DDR_SDTMR2_ODT_SHIFT) |	\
82 	(14 << DV_DDR_SDTMR2_XSNR_SHIFT) |	\
83 	(0xc7 << DV_DDR_SDTMR2_XSRD_SHIFT) |	\
84 	(1 << DV_DDR_SDTMR2_RTP_SHIFT) |	\
85 	(2 << DV_DDR_SDTMR2_CKE_SHIFT))
86 
87 #define CONFIG_SYS_DA850_DDR2_SDBCR (		\
88 	(1 << DV_DDR_SDCR_DDR2EN_SHIFT) |	\
89 	(1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) |	\
90 	(1 << DV_DDR_SDCR_DDREN_SHIFT) |	\
91 	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |	\
92 	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |	\
93 	(2 << DV_DDR_SDCR_CL_SHIFT) |	\
94 	(3 << DV_DDR_SDCR_IBANK_SHIFT) |	\
95 	(2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
96 
97 #define CONFIG_SYS_DA850_CS3CFG	(DAVINCI_ABCR_WSETUP(1)	| \
98 				DAVINCI_ABCR_WSTROBE(2)	| \
99 				DAVINCI_ABCR_WHOLD(0)	| \
100 				DAVINCI_ABCR_RSETUP(1)	| \
101 				DAVINCI_ABCR_RSTROBE(2)	| \
102 				DAVINCI_ABCR_RHOLD(1)	| \
103 				DAVINCI_ABCR_TA(0)	| \
104 				DAVINCI_ABCR_ASIZE_8BIT)
105 
106 /*
107  * Serial Driver info
108  */
109 #define CONFIG_SYS_NS16550_SERIAL
110 #define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size */
111 #define CONFIG_SYS_NS16550_COM1	DAVINCI_UART0_BASE /* Base address of UART0 */
112 #define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
113 
114 /*
115  * Flash & Environment
116  */
117 #define CONFIG_ENV_OFFSET		0x0 /* Block 0--not used by bootcode */
118 #define CONFIG_ENV_SIZE			(128 << 10)
119 #define	CONFIG_SYS_NAND_USE_FLASH_BBT
120 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
121 #define	CONFIG_SYS_NAND_PAGE_2K
122 #define CONFIG_SYS_NAND_CS		3
123 #define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
124 #define CONFIG_SYS_NAND_MASK_CLE		0x10
125 #define CONFIG_SYS_NAND_MASK_ALE		0x8
126 #undef CONFIG_SYS_NAND_HW_ECC
127 #define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
128 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
129 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
130 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
131 #define CONFIG_SYS_NAND_PAGE_SIZE	(2 << 10)
132 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)
133 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
134 #define CONFIG_SYS_NAND_U_BOOT_SIZE	0x120000
135 #define CONFIG_SYS_NAND_U_BOOT_DST	0xc1080000
136 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
137 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	(CONFIG_SYS_NAND_U_BOOT_DST - \
138 					CONFIG_SYS_NAND_U_BOOT_SIZE - \
139 					CONFIG_SYS_MALLOC_LEN -       \
140 					GENERATED_GBL_DATA_SIZE)
141 #define CONFIG_SYS_NAND_ECCPOS		{				\
142 			6,   7,  8,  9, 10,	11, 12, 13, 14, 15,	\
143 			22, 23, 24, 25, 26,	27, 28, 29, 30, 31,	\
144 			38, 39, 40, 41, 42,	43, 44, 45, 46, 47,	\
145 			54, 55, 56, 57, 58,	59, 60, 61, 62, 63}
146 #define CONFIG_SYS_NAND_PAGE_COUNT	64
147 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
148 #define CONFIG_SYS_NAND_ECCSIZE		512
149 #define CONFIG_SYS_NAND_ECCBYTES	10
150 #define CONFIG_SYS_NAND_OOBSIZE		64
151 #define CONFIG_SPL_NAND_BASE
152 #define CONFIG_SPL_NAND_DRIVERS
153 #define CONFIG_SPL_NAND_ECC
154 #define CONFIG_SPL_NAND_LOAD
155 
156 /*
157  * Network & Ethernet Configuration
158  */
159 #ifdef CONFIG_DRIVER_TI_EMAC
160 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
161 #define CONFIG_BOOTP_DEFAULT
162 #define CONFIG_BOOTP_DNS2
163 #define CONFIG_BOOTP_SEND_HOSTNAME
164 #define CONFIG_NET_RETRY_COUNT	10
165 #endif
166 
167 /*
168  * U-Boot general configuration
169  */
170 #define CONFIG_BOOTFILE		"uImage" /* Boot file name */
171 #define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
172 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
173 #define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
174 #define CONFIG_MX_CYCLIC
175 
176 /*
177  * Linux Information
178  */
179 #define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
180 #define CONFIG_HWCONFIG		/* enable hwconfig */
181 #define CONFIG_CMDLINE_TAG
182 #define CONFIG_REVISION_TAG
183 #define CONFIG_SETUP_MEMORY_TAGS
184 #define CONFIG_EXTRA_ENV_SETTINGS \
185 	"defbootargs=setenv bootargs mem=128M console=ttyS0,115200n8 " \
186 		"root=/dev/mtdblock5 rw noinitrd " \
187 		"rootfstype=jffs2 noinitrd\0" \
188 	"hwconfig=dsp:wake=yes\0" \
189 	"bootcmd=nboot kernel;run defbootargs addmtd;bootm 0xc0700000\0" \
190 	"bootfile=uImage\0" \
191 	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"	\
192 	"mtddevname=uboot-env\0" \
193 	"mtddevnum=0\0" \
194 	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0"				\
195 	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"			\
196 	"u-boot=/tftpboot/ipam390/u-boot.ais\0"			\
197 	"upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;" \
198 		"nand write c0000000 20000 ${filesize}\0"	\
199 	"setbootparms=nand read c0100000 200000 400000;"	\
200 		"run defbootargs addmtd;"			\
201 		"spl export atags c0100000;"			\
202 		"nand erase.part bootparms;"			\
203 		"nand write c0000100 180000 20000\0"		\
204 	"\0"
205 
206 #ifdef CONFIG_CMD_BDI
207 #define CONFIG_CLOCKS
208 #endif
209 
210 /* defines for SPL */
211 #define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE - \
212 						CONFIG_SYS_MALLOC_LEN)
213 #define CONFIG_SYS_SPL_MALLOC_SIZE	CONFIG_SYS_MALLOC_LEN
214 #define CONFIG_SPL_STACK	0x8001ff00
215 #define CONFIG_SPL_TEXT_BASE	0x80000000
216 #define CONFIG_SPL_MAX_SIZE	0x20000
217 #define CONFIG_SPL_MAX_FOOTPRINT	32768
218 
219 /* additions for new relocation code, must added to all boards */
220 #define CONFIG_SYS_SDRAM_BASE		0xc0000000
221 
222 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
223 					GENERATED_GBL_DATA_SIZE)
224 
225 /* add FALCON boot mode */
226 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00200000
227 #define CONFIG_SYS_SPL_ARGS_ADDR	LINUX_BOOT_PARAM_ADDR
228 
229 /* GPIO support */
230 #define CONFIG_IPAM390_GPIO_BOOTMODE	((16 * 7) + 14)
231 
232 #define CONFIG_SHOW_BOOT_PROGRESS
233 #define CONFIG_IPAM390_GPIO_LED_RED	((16 * 7) + 11)
234 #define CONFIG_IPAM390_GPIO_LED_GREEN	((16 * 7) + 12)
235 
236 #include <asm/arch/hardware.h>
237 
238 #endif /* __CONFIG_H */
239