1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2011 Andes Technology Corporation 4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5 */ 6 7 #ifndef __AG102_H 8 #define __AG102_H 9 10 /* 11 * Hardware register bases 12 */ 13 14 /* PCI Controller */ 15 #define CONFIG_FTPCI100_BASE 0x90000000 16 /* LPC Controller */ 17 #define CONFIG_LPC_IO_BASE 0x90100000 18 /* LPC Controller */ 19 #define CONFIG_LPC_BASE 0x90200000 20 21 /* NDS32 Data Local Memory 01 */ 22 #define CONFIG_NDS_DLM1_BASE 0x90300000 23 /* NDS32 Data Local Memory 02 */ 24 #define CONFIG_NDS_DLM2_BASE 0x90400000 25 26 /* Synopsys DWC DDR2/1 Controller */ 27 #define CONFIG_DWCDDR21MCTL_BASE 0x90500000 28 /* DMA Controller */ 29 #define CONFIG_FTDMAC020_BASE 0x90600000 30 /* FTIDE020_S IDE (ATA) Controller */ 31 #define CONFIG_FTIDE020S_BASE 0x90700000 32 /* USB OTG Controller */ 33 #define CONFIG_FZOTG266HD0A_BASE 0x90800000 34 /* Andes L2 Cache Controller */ 35 #define CONFIG_NCEL2C100_BASE 0x90900000 36 /* XGI XG22 GPU */ 37 #define CONFIG_XGI_XG22_BASE 0x90A00000 38 /* GMAC Ethernet Controller */ 39 #define CONFIG_FTGMAC100_BASE 0x90B00000 40 /* AHB Controller */ 41 #define CONFIG_FTAHBC020S_BASE 0x90C00000 42 /* AHB-to-APB Bridge Controller */ 43 #define CONFIG_FTAPBBRG020S_01_BASE 0x90D00000 44 /* External AHB2AHB Controller */ 45 #define CONFIG_EXT_AHB2AHB_BASE 0x90E00000 46 /* Andes Multi-core Interrupt Controller */ 47 #define CONFIG_NCEMIC100_BASE 0x90F00000 48 49 /* 50 * APB Device definitions 51 */ 52 /* Compat Flash Controller */ 53 #define CONFIG_FTCFC010_BASE 0x94000000 54 /* APB - SSP (SPI) (without AC97) Controller */ 55 #define CONFIG_FTSSP010_01_BASE 0x94100000 56 /* UART1 - APB STUART Controller (UART0 in Linux) */ 57 #define CONFIG_FTUART010_01_BASE 0x94200000 58 /* APB - SSP with HDA/AC97 Controller */ 59 #define CONFIG_FTSSP010_02_BASE 0x94500000 60 /* UART2 - APB STUART Controller (UART1 in Linux) */ 61 #define CONFIG_FTUART010_02_BASE 0x94600000 62 /* PCU Controller */ 63 #define CONFIG_ANDES_PCU_BASE 0x94800000 64 /* FTTMR010 Timer */ 65 #define CONFIG_FTTMR010_BASE 0x94900000 66 /* Watch Dog Controller */ 67 #define CONFIG_FTWDT010_BASE 0x94A00000 68 /* FTRTC010 Real Time Clock */ 69 #define CONFIG_FTRTC010_BASE 0x98B00000 70 /* GPIO Controller */ 71 #define CONFIG_FTGPIO010_BASE 0x94C00000 72 /* I2C Controller */ 73 #define CONFIG_FTIIC010_BASE 0x94E00000 74 /* PWM - Pulse Width Modulator Controller */ 75 #define CONFIG_FTPWM010_BASE 0x94F00000 76 77 /* Debug LED */ 78 #define CONFIG_DEBUG_LED 0x902FFFFC 79 /* Power Management Unit */ 80 #define CONFIG_FTPMU010_BASE 0x98100000 81 82 #endif /* __AG102_H */ 83