xref: /openbmc/u-boot/drivers/reset/Kconfig (revision 8f6d5bbb)
1menu "Reset Controller Support"
2
3config DM_RESET
4	bool "Enable reset controllers using Driver Model"
5	depends on DM && OF_CONTROL
6	help
7	  Enable support for the reset controller driver class. Many hardware
8	  modules are equipped with a reset signal, typically driven by some
9	  reset controller hardware module within the chip. In U-Boot, reset
10	  controller drivers allow control over these reset signals. In some
11	  cases this API is applicable to chips outside the CPU as well,
12	  although driving such reset isgnals using GPIOs may be more
13	  appropriate in this case.
14
15config SANDBOX_RESET
16	bool "Enable the sandbox reset test driver"
17	depends on DM_MAILBOX && SANDBOX
18	help
19	  Enable support for a test reset controller implementation, which
20	  simply accepts requests to reset various HW modules without actually
21	  doing anything beyond a little error checking.
22
23config STI_RESET
24	bool "Enable the STi reset"
25	depends on ARCH_STI
26	help
27	  Support for reset controllers on STMicroelectronics STiH407 family SoCs.
28	  Say Y if you want to control reset signals provided by system config
29	  block.
30
31config STM32_RESET
32	bool "Enable the STM32 reset"
33	depends on STM32 || ARCH_STM32MP
34	help
35	  Support for reset controllers on STMicroelectronics STM32 family SoCs.
36	  This resset driver is compatible with STM32 F4/F7 and H7 SoCs.
37
38config TEGRA_CAR_RESET
39	bool "Enable Tegra CAR-based reset driver"
40	depends on TEGRA_CAR
41	help
42	  Enable support for manipulating Tegra's on-SoC reset signals via
43	  direct register access to the Tegra CAR (Clock And Reset controller).
44
45config TEGRA186_RESET
46	bool "Enable Tegra186 BPMP-based reset driver"
47	depends on TEGRA186_BPMP
48	help
49	  Enable support for manipulating Tegra's on-SoC reset signals via IPC
50	  requests to the BPMP (Boot and Power Management Processor).
51
52config RESET_TI_SCI
53	bool "TI System Control Interface (TI SCI) reset driver"
54	depends on DM_RESET && TI_SCI_PROTOCOL
55	help
56	  This enables the reset driver support over TI System Control Interface
57	  available on some new TI's SoCs. If you wish to use reset resources
58	  managed by the TI System Controller, say Y here. Otherwise, say N.
59
60config RESET_BCM6345
61	bool "Reset controller driver for BCM6345"
62	depends on DM_RESET && ARCH_BMIPS
63	help
64	  Support reset controller on BCM6345.
65
66config RESET_UNIPHIER
67	bool "Reset controller driver for UniPhier SoCs"
68	depends on ARCH_UNIPHIER
69	default y
70	help
71	  Support for reset controllers on UniPhier SoCs.
72	  Say Y if you want to control reset signals provided by System Control
73	  block, Media I/O block, Peripheral Block.
74
75source "drivers/reset/aspeed/Kconfig"
76
77config RESET_ROCKCHIP
78	bool "Reset controller driver for Rockchip SoCs"
79	depends on DM_RESET && ARCH_ROCKCHIP && CLK
80	default y
81	help
82	  Support for reset controller on rockchip SoC. The main limitation
83	  though is that some reset signals, like I2C or MISC reset multiple
84	  devices.
85
86config RESET_MESON
87	bool "Reset controller driver for Amlogic Meson SoCs"
88	depends on DM_RESET && ARCH_MESON
89	imply REGMAP
90	default y
91	help
92	  Support for reset controller on Amlogic Meson SoC.
93
94config RESET_SOCFPGA
95	bool "Reset controller driver for SoCFPGA"
96	depends on DM_RESET && ARCH_SOCFPGA
97	default y
98	help
99	  Support for reset controller on SoCFPGA platform.
100
101config RESET_MEDIATEK
102	bool "Reset controller driver for MediaTek SoCs"
103	depends on DM_RESET && ARCH_MEDIATEK && CLK
104	default y
105	help
106	  Support for reset controller on MediaTek SoCs.
107
108config RESET_SUNXI
109	bool "RESET support for Allwinner SoCs"
110	depends on DM_RESET && ARCH_SUNXI
111	default y
112	help
113	  This enables support for common reset driver for
114	  Allwinner SoCs.
115
116endmenu
117