1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2010-2011 Freescale Semiconductor, Inc.
4  */
5 
6 /*
7  * QorIQ RDB boards configuration file
8  */
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11 
12 #if defined(CONFIG_TARGET_P1020MBG)
13 #define CONFIG_BOARDNAME "P1020MBG-PC"
14 #define CONFIG_VSC7385_ENET
15 #define CONFIG_SLIC
16 #define __SW_BOOT_MASK		0x03
17 #define __SW_BOOT_NOR		0xe4
18 #define __SW_BOOT_SD		0x54
19 #define CONFIG_SYS_L2_SIZE	(256 << 10)
20 #endif
21 
22 #if defined(CONFIG_TARGET_P1020UTM)
23 #define CONFIG_BOARDNAME "P1020UTM-PC"
24 #define __SW_BOOT_MASK		0x03
25 #define __SW_BOOT_NOR		0xe0
26 #define __SW_BOOT_SD		0x50
27 #define CONFIG_SYS_L2_SIZE	(256 << 10)
28 #endif
29 
30 #if defined(CONFIG_TARGET_P1020RDB_PC)
31 #define CONFIG_BOARDNAME "P1020RDB-PC"
32 #define CONFIG_NAND_FSL_ELBC
33 #define CONFIG_VSC7385_ENET
34 #define CONFIG_SLIC
35 #define __SW_BOOT_MASK		0x03
36 #define __SW_BOOT_NOR		0x5c
37 #define __SW_BOOT_SPI		0x1c
38 #define __SW_BOOT_SD		0x9c
39 #define __SW_BOOT_NAND		0xec
40 #define __SW_BOOT_PCIE		0x6c
41 #define CONFIG_SYS_L2_SIZE	(256 << 10)
42 #endif
43 
44 /*
45  * P1020RDB-PD board has user selectable switches for evaluating different
46  * frequency and boot options for the P1020 device. The table that
47  * follow describe the available options. The front six binary number was in
48  * accordance with SW3[1:6].
49  * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
50  * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
51  * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
52  * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
53  * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
54  * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
55  * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
56  */
57 #if defined(CONFIG_TARGET_P1020RDB_PD)
58 #define CONFIG_BOARDNAME "P1020RDB-PD"
59 #define CONFIG_NAND_FSL_ELBC
60 #define CONFIG_VSC7385_ENET
61 #define CONFIG_SLIC
62 #define __SW_BOOT_MASK		0x03
63 #define __SW_BOOT_NOR		0x64
64 #define __SW_BOOT_SPI		0x34
65 #define __SW_BOOT_SD		0x24
66 #define __SW_BOOT_NAND		0x44
67 #define __SW_BOOT_PCIE		0x74
68 #define CONFIG_SYS_L2_SIZE	(256 << 10)
69 /*
70  * Dynamic MTD Partition support with mtdparts
71  */
72 #endif
73 
74 #if defined(CONFIG_TARGET_P1021RDB)
75 #define CONFIG_BOARDNAME "P1021RDB-PC"
76 #define CONFIG_NAND_FSL_ELBC
77 #define CONFIG_QE
78 #define CONFIG_VSC7385_ENET
79 #define CONFIG_SYS_LBC_LBCR	0x00080000	/* Implement conversion of
80 						addresses in the LBC */
81 #define __SW_BOOT_MASK		0x03
82 #define __SW_BOOT_NOR		0x5c
83 #define __SW_BOOT_SPI		0x1c
84 #define __SW_BOOT_SD		0x9c
85 #define __SW_BOOT_NAND		0xec
86 #define __SW_BOOT_PCIE		0x6c
87 #define CONFIG_SYS_L2_SIZE	(256 << 10)
88 /*
89  * Dynamic MTD Partition support with mtdparts
90  */
91 #endif
92 
93 #if defined(CONFIG_TARGET_P1024RDB)
94 #define CONFIG_BOARDNAME "P1024RDB"
95 #define CONFIG_NAND_FSL_ELBC
96 #define CONFIG_SLIC
97 #define __SW_BOOT_MASK		0xf3
98 #define __SW_BOOT_NOR		0x00
99 #define __SW_BOOT_SPI		0x08
100 #define __SW_BOOT_SD		0x04
101 #define __SW_BOOT_NAND		0x0c
102 #define CONFIG_SYS_L2_SIZE	(256 << 10)
103 #endif
104 
105 #if defined(CONFIG_TARGET_P1025RDB)
106 #define CONFIG_BOARDNAME "P1025RDB"
107 #define CONFIG_NAND_FSL_ELBC
108 #define CONFIG_QE
109 #define CONFIG_SLIC
110 
111 #define CONFIG_SYS_LBC_LBCR	0x00080000	/* Implement conversion of
112 						addresses in the LBC */
113 #define __SW_BOOT_MASK		0xf3
114 #define __SW_BOOT_NOR		0x00
115 #define __SW_BOOT_SPI		0x08
116 #define __SW_BOOT_SD		0x04
117 #define __SW_BOOT_NAND		0x0c
118 #define CONFIG_SYS_L2_SIZE	(256 << 10)
119 #endif
120 
121 #if defined(CONFIG_TARGET_P2020RDB)
122 #define CONFIG_BOARDNAME "P2020RDB-PC"
123 #define CONFIG_NAND_FSL_ELBC
124 #define CONFIG_VSC7385_ENET
125 #define __SW_BOOT_MASK		0x03
126 #define __SW_BOOT_NOR		0xc8
127 #define __SW_BOOT_SPI		0x28
128 #define __SW_BOOT_SD		0x68 /* or 0x18 */
129 #define __SW_BOOT_NAND		0xe8
130 #define __SW_BOOT_PCIE		0xa8
131 #define CONFIG_SYS_L2_SIZE	(512 << 10)
132 /*
133  * Dynamic MTD Partition support with mtdparts
134  */
135 #endif
136 
137 #ifdef CONFIG_SDCARD
138 #define CONFIG_SPL_FLUSH_IMAGE
139 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
140 #define CONFIG_SPL_TEXT_BASE		0xf8f81000
141 #define CONFIG_SPL_PAD_TO		0x20000
142 #define CONFIG_SPL_MAX_SIZE		(128 * 1024)
143 #define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
144 #define CONFIG_SYS_MMC_U_BOOT_DST	(0x11000000)
145 #define CONFIG_SYS_MMC_U_BOOT_START	(0x11000000)
146 #define CONFIG_SYS_MMC_U_BOOT_OFFS	(128 << 10)
147 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
148 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
149 #define CONFIG_SPL_MMC_BOOT
150 #ifdef CONFIG_SPL_BUILD
151 #define CONFIG_SPL_COMMON_INIT_DDR
152 #endif
153 #endif
154 
155 #ifdef CONFIG_SPIFLASH
156 #define CONFIG_SPL_SPI_FLASH_MINIMAL
157 #define CONFIG_SPL_FLUSH_IMAGE
158 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
159 #define CONFIG_SPL_TEXT_BASE		0xf8f81000
160 #define CONFIG_SPL_PAD_TO		0x20000
161 #define CONFIG_SPL_MAX_SIZE		(128 * 1024)
162 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
163 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x11000000)
164 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x11000000)
165 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(128 << 10)
166 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
167 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
168 #define CONFIG_SPL_SPI_BOOT
169 #ifdef CONFIG_SPL_BUILD
170 #define CONFIG_SPL_COMMON_INIT_DDR
171 #endif
172 #endif
173 
174 #ifdef CONFIG_NAND
175 #ifdef CONFIG_TPL_BUILD
176 #define CONFIG_SPL_NAND_BOOT
177 #define CONFIG_SPL_FLUSH_IMAGE
178 #define CONFIG_SPL_NAND_INIT
179 #define CONFIG_SPL_COMMON_INIT_DDR
180 #define CONFIG_SPL_MAX_SIZE		(128 << 10)
181 #define CONFIG_TPL_TEXT_BASE		0xf8f81000
182 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
183 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(832 << 10)
184 #define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
185 #define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
186 #define CONFIG_SYS_NAND_U_BOOT_OFFS	((128 + 128) << 10)
187 #elif defined(CONFIG_SPL_BUILD)
188 #define CONFIG_SPL_INIT_MINIMAL
189 #define CONFIG_SPL_FLUSH_IMAGE
190 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
191 #define CONFIG_SPL_TEXT_BASE		0xff800000
192 #define CONFIG_SPL_MAX_SIZE		4096
193 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
194 #define CONFIG_SYS_NAND_U_BOOT_DST	0xf8f80000
195 #define CONFIG_SYS_NAND_U_BOOT_START	0xf8f80000
196 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)
197 #endif /* not CONFIG_TPL_BUILD */
198 
199 #define CONFIG_SPL_PAD_TO		0x20000
200 #define CONFIG_TPL_PAD_TO		0x20000
201 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
202 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
203 #endif
204 
205 #ifndef CONFIG_RESET_VECTOR_ADDRESS
206 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
207 #endif
208 
209 #ifndef CONFIG_SYS_MONITOR_BASE
210 #ifdef CONFIG_TPL_BUILD
211 #define CONFIG_SYS_MONITOR_BASE	CONFIG_TPL_TEXT_BASE
212 #elif defined(CONFIG_SPL_BUILD)
213 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
214 #else
215 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
216 #endif
217 #endif
218 
219 #define CONFIG_PCIE1	/* PCIE controller 1 (slot 1) */
220 #define CONFIG_PCIE2	/* PCIE controller 2 (slot 2) */
221 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
222 #define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
223 #define CONFIG_FSL_PCIE_RESET	/* need PCIe reset errata */
224 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
225 
226 #define CONFIG_ENV_OVERWRITE
227 
228 #define CONFIG_SYS_SATA_MAX_DEVICE	2
229 #define CONFIG_LBA48
230 
231 #if defined(CONFIG_TARGET_P2020RDB)
232 #define CONFIG_SYS_CLK_FREQ	100000000
233 #else
234 #define CONFIG_SYS_CLK_FREQ	66666666
235 #endif
236 #define CONFIG_DDR_CLK_FREQ	66666666
237 
238 #define CONFIG_HWCONFIG
239 /*
240  * These can be toggled for performance analysis, otherwise use default.
241  */
242 #define CONFIG_L2_CACHE
243 #define CONFIG_BTB
244 
245 #define CONFIG_ENABLE_36BIT_PHYS
246 
247 #ifdef CONFIG_PHYS_64BIT
248 #define CONFIG_ADDR_MAP			1
249 #define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
250 #endif
251 
252 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
253 #define CONFIG_SYS_MEMTEST_END		0x1fffffff
254 
255 #define CONFIG_SYS_CCSRBAR		0xffe00000
256 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
257 
258 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
259        SPL code*/
260 #ifdef CONFIG_SPL_BUILD
261 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
262 #endif
263 
264 /* DDR Setup */
265 #define CONFIG_SYS_DDR_RAW_TIMING
266 #define CONFIG_DDR_SPD
267 #define CONFIG_SYS_SPD_BUS_NUM 1
268 #define SPD_EEPROM_ADDRESS 0x52
269 
270 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
271 #define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_2G
272 #define CONFIG_CHIP_SELECTS_PER_CTRL	2
273 #else
274 #define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_1G
275 #define CONFIG_CHIP_SELECTS_PER_CTRL	1
276 #endif
277 #define CONFIG_SYS_SDRAM_SIZE		(1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
278 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
279 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
280 
281 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
282 
283 /* Default settings for DDR3 */
284 #ifndef CONFIG_TARGET_P2020RDB
285 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000003f
286 #define CONFIG_SYS_DDR_CS0_CONFIG	0x80014302
287 #define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
288 #define CONFIG_SYS_DDR_CS1_BNDS		0x0040007f
289 #define CONFIG_SYS_DDR_CS1_CONFIG	0x80014302
290 #define CONFIG_SYS_DDR_CS1_CONFIG_2	0x00000000
291 
292 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
293 #define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
294 #define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
295 #define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
296 
297 #define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
298 #define CONFIG_SYS_DDR_WRLVL_CONTROL	0x8655A608
299 #define CONFIG_SYS_DDR_SR_CNTR		0x00000000
300 #define CONFIG_SYS_DDR_RCW_1		0x00000000
301 #define CONFIG_SYS_DDR_RCW_2		0x00000000
302 #define CONFIG_SYS_DDR_CONTROL		0xC70C0000	/* Type = DDR3	*/
303 #define CONFIG_SYS_DDR_CONTROL_2	0x04401050
304 #define CONFIG_SYS_DDR_TIMING_4		0x00220001
305 #define CONFIG_SYS_DDR_TIMING_5		0x03402400
306 
307 #define CONFIG_SYS_DDR_TIMING_3		0x00020000
308 #define CONFIG_SYS_DDR_TIMING_0		0x00330004
309 #define CONFIG_SYS_DDR_TIMING_1		0x6f6B4846
310 #define CONFIG_SYS_DDR_TIMING_2		0x0FA8C8CF
311 #define CONFIG_SYS_DDR_CLK_CTRL		0x03000000
312 #define CONFIG_SYS_DDR_MODE_1		0x40461520
313 #define CONFIG_SYS_DDR_MODE_2		0x8000c000
314 #define CONFIG_SYS_DDR_INTERVAL		0x0C300000
315 #endif
316 
317 #undef CONFIG_CLOCKS_IN_MHZ
318 
319 /*
320  * Memory map
321  *
322  * 0x0000_0000 0x7fff_ffff	DDR		Up to 2GB cacheable
323  * 0x8000_0000 0xdfff_ffff	PCI Express Mem	1.5G non-cacheable(PCIe * 3)
324  * 0xec00_0000 0xefff_ffff	NOR flash	Up to 64M non-cacheable	CS0/1
325  * 0xf8f8_0000 0xf8ff_ffff	L2 SRAM		Up to 512K cacheable
326  *   (early boot only)
327  * 0xff80_0000 0xff80_7fff	NAND flash	32K non-cacheable	CS1/0
328  * 0xff98_0000 0xff98_ffff	PMC		64K non-cacheable	CS2
329  * 0xffa0_0000 0xffaf_ffff	CPLD		1M non-cacheable	CS3
330  * 0xffb0_0000 0xffbf_ffff	VSC7385 switch  1M non-cacheable	CS2
331  * 0xffc0_0000 0xffc3_ffff	PCI IO range	256k non-cacheable
332  * 0xffd0_0000 0xffd0_3fff	L1 for stack	16K cacheable
333  * 0xffe0_0000 0xffef_ffff	CCSR		1M non-cacheable
334  */
335 
336 /*
337  * Local Bus Definitions
338  */
339 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
340 #define CONFIG_SYS_MAX_FLASH_SECT	512	/* 64M */
341 #define CONFIG_SYS_FLASH_BASE		0xec000000
342 #elif defined(CONFIG_TARGET_P1020UTM)
343 #define CONFIG_SYS_MAX_FLASH_SECT	256	/* 32M */
344 #define CONFIG_SYS_FLASH_BASE		0xee000000
345 #else
346 #define CONFIG_SYS_MAX_FLASH_SECT	128	/* 16M */
347 #define CONFIG_SYS_FLASH_BASE		0xef000000
348 #endif
349 
350 #ifdef CONFIG_PHYS_64BIT
351 #define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
352 #else
353 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
354 #endif
355 
356 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
357 	| BR_PS_16 | BR_V)
358 
359 #define CONFIG_FLASH_OR_PRELIM	0xfc000ff7
360 
361 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
362 #define CONFIG_SYS_FLASH_QUIET_TEST
363 #define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
364 
365 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
366 
367 #undef CONFIG_SYS_FLASH_CHECKSUM
368 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
369 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
370 
371 #define CONFIG_SYS_FLASH_EMPTY_INFO
372 
373 /* Nand Flash */
374 #ifdef CONFIG_NAND_FSL_ELBC
375 #define CONFIG_SYS_NAND_BASE		0xff800000
376 #ifdef CONFIG_PHYS_64BIT
377 #define CONFIG_SYS_NAND_BASE_PHYS	0xfff800000ull
378 #else
379 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
380 #endif
381 
382 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
383 #define CONFIG_SYS_MAX_NAND_DEVICE	1
384 #if defined(CONFIG_TARGET_P1020RDB_PD)
385 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
386 #else
387 #define CONFIG_SYS_NAND_BLOCK_SIZE	(16 * 1024)
388 #endif
389 
390 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
391 	| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
392 	| BR_PS_8	/* Port Size = 8 bit */ \
393 	| BR_MS_FCM	/* MSEL = FCM */ \
394 	| BR_V)	/* valid */
395 #if defined(CONFIG_TARGET_P1020RDB_PD)
396 #define CONFIG_SYS_NAND_OR_PRELIM	(OR_AM_32KB \
397 	| OR_FCM_PGS	/* Large Page*/ \
398 	| OR_FCM_CSCT \
399 	| OR_FCM_CST \
400 	| OR_FCM_CHT \
401 	| OR_FCM_SCY_1 \
402 	| OR_FCM_TRLX \
403 	| OR_FCM_EHTR)
404 #else
405 #define CONFIG_SYS_NAND_OR_PRELIM	(OR_AM_32KB	/* small page */ \
406 	| OR_FCM_CSCT \
407 	| OR_FCM_CST \
408 	| OR_FCM_CHT \
409 	| OR_FCM_SCY_1 \
410 	| OR_FCM_TRLX \
411 	| OR_FCM_EHTR)
412 #endif
413 #endif /* CONFIG_NAND_FSL_ELBC */
414 
415 #define CONFIG_SYS_INIT_RAM_LOCK
416 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* stack in RAM */
417 #ifdef CONFIG_PHYS_64BIT
418 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
419 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
420 /* The assembler doesn't like typecast */
421 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
422 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
423 	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
424 #else
425 /* Initial L1 address */
426 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR
427 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
428 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
429 #endif
430 /* Size of used area in RAM */
431 #define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
432 
433 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
434 					GENERATED_GBL_DATA_SIZE)
435 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
436 
437 #define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
438 #define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)/* Reserved for malloc */
439 
440 #define CONFIG_SYS_CPLD_BASE	0xffa00000
441 #ifdef CONFIG_PHYS_64BIT
442 #define CONFIG_SYS_CPLD_BASE_PHYS	0xfffa00000ull
443 #else
444 #define CONFIG_SYS_CPLD_BASE_PHYS	CONFIG_SYS_CPLD_BASE
445 #endif
446 /* CPLD config size: 1Mb */
447 #define CONFIG_CPLD_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
448 					BR_PS_8 | BR_V)
449 #define CONFIG_CPLD_OR_PRELIM	(0xfff009f7)
450 
451 #define CONFIG_SYS_PMC_BASE	0xff980000
452 #define CONFIG_SYS_PMC_BASE_PHYS	CONFIG_SYS_PMC_BASE
453 #define CONFIG_PMC_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
454 					BR_PS_8 | BR_V)
455 #define CONFIG_PMC_OR_PRELIM	(OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
456 				 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
457 				 OR_GPCM_EAD)
458 
459 #ifdef CONFIG_NAND
460 #define CONFIG_SYS_BR0_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
461 #define CONFIG_SYS_OR0_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
462 #define CONFIG_SYS_BR1_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
463 #define CONFIG_SYS_OR1_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
464 #else
465 #define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
466 #define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
467 #ifdef CONFIG_NAND_FSL_ELBC
468 #define CONFIG_SYS_BR1_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
469 #define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
470 #endif
471 #endif
472 #define CONFIG_SYS_BR3_PRELIM	CONFIG_CPLD_BR_PRELIM	/* CPLD Base Address */
473 #define CONFIG_SYS_OR3_PRELIM	CONFIG_CPLD_OR_PRELIM	/* CPLD Options */
474 
475 /* Vsc7385 switch */
476 #ifdef CONFIG_VSC7385_ENET
477 #define CONFIG_SYS_VSC7385_BASE		0xffb00000
478 
479 #ifdef CONFIG_PHYS_64BIT
480 #define CONFIG_SYS_VSC7385_BASE_PHYS	0xfffb00000ull
481 #else
482 #define CONFIG_SYS_VSC7385_BASE_PHYS	CONFIG_SYS_VSC7385_BASE
483 #endif
484 
485 #define CONFIG_SYS_VSC7385_BR_PRELIM	\
486 	(BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
487 #define CONFIG_SYS_VSC7385_OR_PRELIM	(OR_AM_128KB | OR_GPCM_CSNT | \
488 			OR_GPCM_XACS |  OR_GPCM_SCY_15 | OR_GPCM_SETA | \
489 			OR_GPCM_TRLX |  OR_GPCM_EHTR | OR_GPCM_EAD)
490 
491 #define CONFIG_SYS_BR2_PRELIM	CONFIG_SYS_VSC7385_BR_PRELIM
492 #define CONFIG_SYS_OR2_PRELIM	CONFIG_SYS_VSC7385_OR_PRELIM
493 
494 /* The size of the VSC7385 firmware image */
495 #define CONFIG_VSC7385_IMAGE_SIZE	8192
496 #endif
497 
498 /*
499  * Config the L2 Cache as L2 SRAM
500 */
501 #if defined(CONFIG_SPL_BUILD)
502 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
503 #define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
504 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
505 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
506 #define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
507 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
508 #define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
509 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
510 #if defined(CONFIG_TARGET_P2020RDB)
511 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(364 << 10)
512 #else
513 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(108 << 10)
514 #endif
515 #elif defined(CONFIG_NAND)
516 #ifdef CONFIG_TPL_BUILD
517 #define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
518 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
519 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
520 #define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
521 #define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
522 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
523 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(48 << 10)
524 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
525 #else
526 #define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
527 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
528 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
529 #define CONFIG_SPL_RELOC_TEXT_BASE	(CONFIG_SYS_INIT_L2_END - 0x2000)
530 #define CONFIG_SPL_RELOC_STACK		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
531 #endif /* CONFIG_TPL_BUILD */
532 #endif
533 #endif
534 
535 /* Serial Port - controlled on board with jumper J8
536  * open - index 2
537  * shorted - index 1
538  */
539 #undef CONFIG_SERIAL_SOFTWARE_FIFO
540 #define CONFIG_SYS_NS16550_SERIAL
541 #define CONFIG_SYS_NS16550_REG_SIZE	1
542 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
543 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
544 #define CONFIG_NS16550_MIN_FUNCTIONS
545 #endif
546 
547 #define CONFIG_SYS_BAUDRATE_TABLE	\
548 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
549 
550 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
551 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
552 
553 /* I2C */
554 #define CONFIG_SYS_I2C
555 #define CONFIG_SYS_I2C_FSL
556 #define CONFIG_SYS_FSL_I2C_SPEED	400000
557 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
558 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
559 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
560 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
561 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
562 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
563 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x52
564 #define CONFIG_SYS_SPD_BUS_NUM		1 /* For rom_loc and flash bank */
565 
566 /*
567  * I2C2 EEPROM
568  */
569 #undef CONFIG_ID_EEPROM
570 
571 #define CONFIG_RTC_PT7C4338
572 #define CONFIG_SYS_I2C_RTC_ADDR		0x68
573 #define CONFIG_SYS_I2C_PCA9557_ADDR	0x18
574 
575 /* enable read and write access to EEPROM */
576 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
577 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
578 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
579 
580 #if defined(CONFIG_PCI)
581 /*
582  * General PCI
583  * Memory space is mapped 1-1, but I/O space must start from 0.
584  */
585 
586 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
587 #define CONFIG_SYS_PCIE2_NAME		"PCIe SLOT"
588 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
589 #ifdef CONFIG_PHYS_64BIT
590 #define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
591 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
592 #else
593 #define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
594 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
595 #endif
596 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
597 #define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
598 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
599 #ifdef CONFIG_PHYS_64BIT
600 #define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
601 #else
602 #define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
603 #endif
604 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
605 
606 /* controller 1, Slot 2, tgtid 1, Base address a000 */
607 #define CONFIG_SYS_PCIE1_NAME		"mini PCIe SLOT"
608 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
609 #ifdef CONFIG_PHYS_64BIT
610 #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
611 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
612 #else
613 #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
614 #define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
615 #endif
616 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
617 #define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
618 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
619 #ifdef CONFIG_PHYS_64BIT
620 #define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc00000ull
621 #else
622 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc00000
623 #endif
624 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
625 
626 #define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
627 #endif /* CONFIG_PCI */
628 
629 #if defined(CONFIG_TSEC_ENET)
630 #define CONFIG_TSEC1
631 #define CONFIG_TSEC1_NAME	"eTSEC1"
632 #define CONFIG_TSEC2
633 #define CONFIG_TSEC2_NAME	"eTSEC2"
634 #define CONFIG_TSEC3
635 #define CONFIG_TSEC3_NAME	"eTSEC3"
636 
637 #define TSEC1_PHY_ADDR	2
638 #define TSEC2_PHY_ADDR	0
639 #define TSEC3_PHY_ADDR	1
640 
641 #define TSEC1_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
642 #define TSEC2_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
643 #define TSEC3_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
644 
645 #define TSEC1_PHYIDX	0
646 #define TSEC2_PHYIDX	0
647 #define TSEC3_PHYIDX	0
648 
649 #define CONFIG_ETHPRIME	"eTSEC1"
650 
651 #define CONFIG_HAS_ETH0
652 #define CONFIG_HAS_ETH1
653 #define CONFIG_HAS_ETH2
654 #endif /* CONFIG_TSEC_ENET */
655 
656 #ifdef CONFIG_QE
657 /* QE microcode/firmware address */
658 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
659 #define CONFIG_SYS_QE_FW_ADDR	0xefec0000
660 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
661 #endif /* CONFIG_QE */
662 
663 #ifdef CONFIG_TARGET_P1025RDB
664 /*
665  * QE UEC ethernet configuration
666  */
667 #define CONFIG_MIIM_ADDRESS	(CONFIG_SYS_CCSRBAR + 0x82120)
668 
669 #undef CONFIG_UEC_ETH
670 #define CONFIG_PHY_MODE_NEED_CHANGE
671 
672 #define CONFIG_UEC_ETH1	/* ETH1 */
673 #define CONFIG_HAS_ETH0
674 
675 #ifdef CONFIG_UEC_ETH1
676 #define CONFIG_SYS_UEC1_UCC_NUM	0	/* UCC1 */
677 #define CONFIG_SYS_UEC1_RX_CLK	QE_CLK12 /* CLK12 for MII */
678 #define CONFIG_SYS_UEC1_TX_CLK	QE_CLK9 /* CLK9 for MII */
679 #define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
680 #define CONFIG_SYS_UEC1_PHY_ADDR	0x0	/* 0x0 for MII */
681 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
682 #define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
683 #endif /* CONFIG_UEC_ETH1 */
684 
685 #define CONFIG_UEC_ETH5	/* ETH5 */
686 #define CONFIG_HAS_ETH1
687 
688 #ifdef CONFIG_UEC_ETH5
689 #define CONFIG_SYS_UEC5_UCC_NUM	4	/* UCC5 */
690 #define CONFIG_SYS_UEC5_RX_CLK	QE_CLK_NONE
691 #define CONFIG_SYS_UEC5_TX_CLK	QE_CLK13 /* CLK 13 for RMII */
692 #define CONFIG_SYS_UEC5_ETH_TYPE	FAST_ETH
693 #define CONFIG_SYS_UEC5_PHY_ADDR	0x3	/* 0x3 for RMII */
694 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
695 #define CONFIG_SYS_UEC5_INTERFACE_SPEED	100
696 #endif /* CONFIG_UEC_ETH5 */
697 #endif /* CONFIG_TARGET_P1025RDB */
698 
699 /*
700  * Environment
701  */
702 #ifdef CONFIG_SPIFLASH
703 #define CONFIG_ENV_SIZE		0x2000	/* 8KB */
704 #define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
705 #define CONFIG_ENV_SECT_SIZE	0x10000
706 #elif defined(CONFIG_SDCARD)
707 #define CONFIG_FSL_FIXED_MMC_LOCATION
708 #define CONFIG_ENV_SIZE		0x2000
709 #define CONFIG_SYS_MMC_ENV_DEV	0
710 #elif defined(CONFIG_NAND)
711 #ifdef CONFIG_TPL_BUILD
712 #define CONFIG_ENV_SIZE		0x2000
713 #define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
714 #else
715 #define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
716 #endif
717 #define CONFIG_ENV_OFFSET	(1024 * 1024)
718 #define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
719 #elif defined(CONFIG_SYS_RAMBOOT)
720 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
721 #define CONFIG_ENV_SIZE		0x2000
722 #else
723 #define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
724 #define CONFIG_ENV_SIZE		0x2000
725 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
726 #endif
727 
728 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
729 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
730 
731 /*
732  * USB
733  */
734 #define CONFIG_HAS_FSL_DR_USB
735 
736 #if defined(CONFIG_HAS_FSL_DR_USB)
737 #ifdef CONFIG_USB_EHCI_HCD
738 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
739 #define CONFIG_USB_EHCI_FSL
740 #endif
741 #endif
742 
743 #if defined(CONFIG_TARGET_P1020RDB_PD)
744 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
745 #endif
746 
747 #ifdef CONFIG_MMC
748 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
749 #endif
750 
751 #undef CONFIG_WATCHDOG	/* watchdog disabled */
752 
753 /*
754  * Miscellaneous configurable options
755  */
756 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
757 
758 /*
759  * For booting Linux, the board info and command line data
760  * have to be in the first 64 MB of memory, since this is
761  * the maximum mapped by the Linux kernel during initialization.
762  */
763 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux*/
764 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
765 
766 #if defined(CONFIG_CMD_KGDB)
767 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
768 #endif
769 
770 /*
771  * Environment Configuration
772  */
773 #define CONFIG_HOSTNAME		"unknown"
774 #define CONFIG_ROOTPATH		"/opt/nfsroot"
775 #define CONFIG_BOOTFILE		"uImage"
776 #define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */
777 
778 /* default location for tftp and bootm */
779 #define CONFIG_LOADADDR	1000000
780 
781 #ifdef __SW_BOOT_NOR
782 #define __NOR_RST_CMD	\
783 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
784 i2c mw 18 3 __SW_BOOT_MASK 1; reset
785 #endif
786 #ifdef __SW_BOOT_SPI
787 #define __SPI_RST_CMD	\
788 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
789 i2c mw 18 3 __SW_BOOT_MASK 1; reset
790 #endif
791 #ifdef __SW_BOOT_SD
792 #define __SD_RST_CMD	\
793 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
794 i2c mw 18 3 __SW_BOOT_MASK 1; reset
795 #endif
796 #ifdef __SW_BOOT_NAND
797 #define __NAND_RST_CMD	\
798 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
799 i2c mw 18 3 __SW_BOOT_MASK 1; reset
800 #endif
801 #ifdef __SW_BOOT_PCIE
802 #define __PCIE_RST_CMD	\
803 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
804 i2c mw 18 3 __SW_BOOT_MASK 1; reset
805 #endif
806 
807 #define	CONFIG_EXTRA_ENV_SETTINGS	\
808 "netdev=eth0\0"	\
809 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"	\
810 "loadaddr=1000000\0"	\
811 "bootfile=uImage\0"	\
812 "tftpflash=tftpboot $loadaddr $uboot; "	\
813 	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
814 	"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
815 	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
816 	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
817 	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
818 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"    \
819 "consoledev=ttyS0\0"	\
820 "ramdiskaddr=2000000\0"	\
821 "ramdiskfile=rootfs.ext2.gz.uboot\0"	\
822 "fdtaddr=1e00000\0"	\
823 "bdev=sda1\0" \
824 "jffs2nor=mtdblock3\0"	\
825 "norbootaddr=ef080000\0"	\
826 "norfdtaddr=ef040000\0"	\
827 "jffs2nand=mtdblock9\0"	\
828 "nandbootaddr=100000\0"	\
829 "nandfdtaddr=80000\0"		\
830 "ramdisk_size=120000\0"	\
831 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
832 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
833 __stringify(__NOR_RST_CMD)"\0" \
834 __stringify(__SPI_RST_CMD)"\0" \
835 __stringify(__SD_RST_CMD)"\0" \
836 __stringify(__NAND_RST_CMD)"\0" \
837 __stringify(__PCIE_RST_CMD)"\0"
838 
839 #define CONFIG_NFSBOOTCOMMAND	\
840 "setenv bootargs root=/dev/nfs rw "	\
841 "nfsroot=$serverip:$rootpath "	\
842 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
843 "console=$consoledev,$baudrate $othbootargs;" \
844 "tftp $loadaddr $bootfile;"	\
845 "tftp $fdtaddr $fdtfile;"	\
846 "bootm $loadaddr - $fdtaddr"
847 
848 #define CONFIG_HDBOOT	\
849 "setenv bootargs root=/dev/$bdev rw rootdelay=30 "	\
850 "console=$consoledev,$baudrate $othbootargs;" \
851 "usb start;"	\
852 "ext2load usb 0:1 $loadaddr /boot/$bootfile;"	\
853 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"	\
854 "bootm $loadaddr - $fdtaddr"
855 
856 #define CONFIG_USB_FAT_BOOT	\
857 "setenv bootargs root=/dev/ram rw "	\
858 "console=$consoledev,$baudrate $othbootargs " \
859 "ramdisk_size=$ramdisk_size;"	\
860 "usb start;"	\
861 "fatload usb 0:2 $loadaddr $bootfile;"	\
862 "fatload usb 0:2 $fdtaddr $fdtfile;"	\
863 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"	\
864 "bootm $loadaddr $ramdiskaddr $fdtaddr"
865 
866 #define CONFIG_USB_EXT2_BOOT	\
867 "setenv bootargs root=/dev/ram rw "	\
868 "console=$consoledev,$baudrate $othbootargs " \
869 "ramdisk_size=$ramdisk_size;"	\
870 "usb start;"	\
871 "ext2load usb 0:4 $loadaddr $bootfile;"	\
872 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
873 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
874 "bootm $loadaddr $ramdiskaddr $fdtaddr"
875 
876 #define CONFIG_NORBOOT	\
877 "setenv bootargs root=/dev/$jffs2nor rw "	\
878 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"	\
879 "bootm $norbootaddr - $norfdtaddr"
880 
881 #define CONFIG_RAMBOOTCOMMAND	\
882 "setenv bootargs root=/dev/ram rw "	\
883 "console=$consoledev,$baudrate $othbootargs " \
884 "ramdisk_size=$ramdisk_size;"	\
885 "tftp $ramdiskaddr $ramdiskfile;"	\
886 "tftp $loadaddr $bootfile;"	\
887 "tftp $fdtaddr $fdtfile;"	\
888 "bootm $loadaddr $ramdiskaddr $fdtaddr"
889 
890 #define CONFIG_BOOTCOMMAND	CONFIG_HDBOOT
891 
892 #endif /* __CONFIG_H */
893