1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2016 Google, Inc
4  *
5  * From Coreboot src/soc/intel/broadwell/include/soc/gpio.h
6  */
7 
8 #ifndef __ASM_ARCH_GPIO
9 #define __ASM_ARCH_GPIO
10 
11 #define GPIO_PER_BANK	32
12 #define GPIO_BANKS	3
13 
14 struct broadwell_bank_platdata {
15 	uint16_t base_addr;
16 	const char *bank_name;
17 	int bank;
18 };
19 
20 /* PCH-LP GPIOBASE Registers */
21 struct pch_lp_gpio_regs {
22 	u32 own[GPIO_BANKS];
23 	u32 reserved0;
24 
25 	u16 pirq_to_ioxapic;
26 	u16 reserved1[3];
27 	u32 blink;
28 	u32 ser_blink;
29 
30 	u32 ser_blink_cmdsts;
31 	u32 ser_blink_data;
32 	u16 gpi_nmi_en;
33 	u16 gpi_nmi_sts;
34 	u32 reserved2;
35 
36 	u32 gpi_route[GPIO_BANKS];
37 	u32 reserved3;
38 
39 	u32 reserved4[4];
40 
41 	u32 alt_gpi_smi_sts;
42 	u32 alt_gpi_smi_en;
43 	u32 reserved5[2];
44 
45 	u32 rst_sel[GPIO_BANKS];
46 	u32 reserved6;
47 
48 	u32 reserved9[3];
49 	u32 gpio_gc;
50 
51 	u32 gpi_is[GPIO_BANKS];
52 	u32 reserved10;
53 
54 	u32 gpi_ie[GPIO_BANKS];
55 	u32 reserved11;
56 
57 	u32 reserved12[24];
58 
59 	struct {
60 		u32 conf_a;
61 		u32 conf_b;
62 	} config[GPIO_BANKS * GPIO_PER_BANK];
63 };
64 check_member(pch_lp_gpio_regs, gpi_ie[0], 0x90);
65 check_member(pch_lp_gpio_regs, config[0], 0x100);
66 
67 enum {
68 	CONFA_MODE_SHIFT	= 0,
69 	CONFA_MODE_GPIO		= 1 << CONFA_MODE_SHIFT,
70 
71 	CONFA_DIR_SHIFT		= 2,
72 	CONFA_DIR_INPUT		= 1 << CONFA_DIR_SHIFT,
73 
74 	CONFA_INVERT_SHIFT	= 3,
75 	CONFA_INVERT		= 1 << CONFA_INVERT_SHIFT,
76 
77 	CONFA_TRIGGER_SHIFT	= 4,
78 	CONFA_TRIGGER_LEVEL	= 1 << CONFA_TRIGGER_SHIFT,
79 
80 	CONFA_LEVEL_SHIFT	= 30,
81 	CONFA_LEVEL_HIGH	= 1UL << CONFA_LEVEL_SHIFT,
82 
83 	CONFA_OUTPUT_SHIFT	= 31,
84 	CONFA_OUTPUT_HIGH	= 1UL << CONFA_OUTPUT_SHIFT,
85 
86 	CONFB_SENSE_SHIFT	= 2,
87 	CONFB_SENSE_DISABLE	= 1 << CONFB_SENSE_SHIFT,
88 };
89 
90 #endif
91