1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 
3 /* Authors: Cheng Xu <chengyou@linux.alibaba.com> */
4 /*          Kai Shen <kaishen@linux.alibaba.com> */
5 /* Copyright (c) 2020-2022, Alibaba Group. */
6 
7 #ifndef __ERDMA_HW_H__
8 #define __ERDMA_HW_H__
9 
10 #include <linux/kernel.h>
11 #include <linux/types.h>
12 
13 /* PCIe device related definition. */
14 #define PCI_VENDOR_ID_ALIBABA 0x1ded
15 
16 #define ERDMA_PCI_WIDTH 64
17 #define ERDMA_FUNC_BAR 0
18 #define ERDMA_MISX_BAR 2
19 
20 #define ERDMA_BAR_MASK (BIT(ERDMA_FUNC_BAR) | BIT(ERDMA_MISX_BAR))
21 
22 /* MSI-X related. */
23 #define ERDMA_NUM_MSIX_VEC 32U
24 #define ERDMA_MSIX_VECTOR_CMDQ 0
25 
26 /* PCIe Bar0 Registers. */
27 #define ERDMA_REGS_VERSION_REG 0x0
28 #define ERDMA_REGS_DEV_CTRL_REG 0x10
29 #define ERDMA_REGS_DEV_ST_REG 0x14
30 #define ERDMA_REGS_NETDEV_MAC_L_REG 0x18
31 #define ERDMA_REGS_NETDEV_MAC_H_REG 0x1C
32 #define ERDMA_REGS_CMDQ_SQ_ADDR_L_REG 0x20
33 #define ERDMA_REGS_CMDQ_SQ_ADDR_H_REG 0x24
34 #define ERDMA_REGS_CMDQ_CQ_ADDR_L_REG 0x28
35 #define ERDMA_REGS_CMDQ_CQ_ADDR_H_REG 0x2C
36 #define ERDMA_REGS_CMDQ_DEPTH_REG 0x30
37 #define ERDMA_REGS_CMDQ_EQ_DEPTH_REG 0x34
38 #define ERDMA_REGS_CMDQ_EQ_ADDR_L_REG 0x38
39 #define ERDMA_REGS_CMDQ_EQ_ADDR_H_REG 0x3C
40 #define ERDMA_REGS_AEQ_ADDR_L_REG 0x40
41 #define ERDMA_REGS_AEQ_ADDR_H_REG 0x44
42 #define ERDMA_REGS_AEQ_DEPTH_REG 0x48
43 #define ERDMA_REGS_GRP_NUM_REG 0x4c
44 #define ERDMA_REGS_AEQ_DB_REG 0x50
45 #define ERDMA_CMDQ_SQ_DB_HOST_ADDR_REG 0x60
46 #define ERDMA_CMDQ_CQ_DB_HOST_ADDR_REG 0x68
47 #define ERDMA_CMDQ_EQ_DB_HOST_ADDR_REG 0x70
48 #define ERDMA_AEQ_DB_HOST_ADDR_REG 0x78
49 #define ERDMA_REGS_STATS_TSO_IN_PKTS_REG 0x80
50 #define ERDMA_REGS_STATS_TSO_OUT_PKTS_REG 0x88
51 #define ERDMA_REGS_STATS_TSO_OUT_BYTES_REG 0x90
52 #define ERDMA_REGS_STATS_TX_DROP_PKTS_REG 0x98
53 #define ERDMA_REGS_STATS_TX_BPS_METER_DROP_PKTS_REG 0xa0
54 #define ERDMA_REGS_STATS_TX_PPS_METER_DROP_PKTS_REG 0xa8
55 #define ERDMA_REGS_STATS_RX_PKTS_REG 0xc0
56 #define ERDMA_REGS_STATS_RX_BYTES_REG 0xc8
57 #define ERDMA_REGS_STATS_RX_DROP_PKTS_REG 0xd0
58 #define ERDMA_REGS_STATS_RX_BPS_METER_DROP_PKTS_REG 0xd8
59 #define ERDMA_REGS_STATS_RX_PPS_METER_DROP_PKTS_REG 0xe0
60 #define ERDMA_REGS_CEQ_DB_BASE_REG 0x100
61 #define ERDMA_CMDQ_SQDB_REG 0x200
62 #define ERDMA_CMDQ_CQDB_REG 0x300
63 
64 /* DEV_CTRL_REG details. */
65 #define ERDMA_REG_DEV_CTRL_RESET_MASK 0x00000001
66 #define ERDMA_REG_DEV_CTRL_INIT_MASK 0x00000002
67 
68 /* DEV_ST_REG details. */
69 #define ERDMA_REG_DEV_ST_RESET_DONE_MASK 0x00000001U
70 #define ERDMA_REG_DEV_ST_INIT_DONE_MASK 0x00000002U
71 
72 /* eRDMA PCIe DBs definition. */
73 #define ERDMA_BAR_DB_SPACE_BASE 4096
74 
75 #define ERDMA_BAR_SQDB_SPACE_OFFSET ERDMA_BAR_DB_SPACE_BASE
76 #define ERDMA_BAR_SQDB_SPACE_SIZE (384 * 1024)
77 
78 #define ERDMA_BAR_RQDB_SPACE_OFFSET \
79 	(ERDMA_BAR_SQDB_SPACE_OFFSET + ERDMA_BAR_SQDB_SPACE_SIZE)
80 #define ERDMA_BAR_RQDB_SPACE_SIZE (96 * 1024)
81 
82 #define ERDMA_BAR_CQDB_SPACE_OFFSET \
83 	(ERDMA_BAR_RQDB_SPACE_OFFSET + ERDMA_BAR_RQDB_SPACE_SIZE)
84 
85 #define ERDMA_SDB_SHARED_PAGE_INDEX 95
86 
87 /* Doorbell related. */
88 #define ERDMA_DB_SIZE 8
89 
90 #define ERDMA_CQDB_IDX_MASK GENMASK_ULL(63, 56)
91 #define ERDMA_CQDB_CQN_MASK GENMASK_ULL(55, 32)
92 #define ERDMA_CQDB_ARM_MASK BIT_ULL(31)
93 #define ERDMA_CQDB_SOL_MASK BIT_ULL(30)
94 #define ERDMA_CQDB_CMDSN_MASK GENMASK_ULL(29, 28)
95 #define ERDMA_CQDB_CI_MASK GENMASK_ULL(23, 0)
96 
97 #define ERDMA_EQDB_ARM_MASK BIT(31)
98 #define ERDMA_EQDB_CI_MASK GENMASK_ULL(23, 0)
99 
100 #define ERDMA_PAGE_SIZE_SUPPORT 0x7FFFF000
101 
102 /* Hardware page size definition */
103 #define ERDMA_HW_PAGE_SHIFT 12
104 #define ERDMA_HW_PAGE_SIZE 4096
105 
106 /* WQE related. */
107 #define EQE_SIZE 16
108 #define EQE_SHIFT 4
109 #define RQE_SIZE 32
110 #define RQE_SHIFT 5
111 #define CQE_SIZE 32
112 #define CQE_SHIFT 5
113 #define SQEBB_SIZE 32
114 #define SQEBB_SHIFT 5
115 #define SQEBB_MASK (~(SQEBB_SIZE - 1))
116 #define SQEBB_ALIGN(size) ((size + SQEBB_SIZE - 1) & SQEBB_MASK)
117 #define SQEBB_COUNT(size) (SQEBB_ALIGN(size) >> SQEBB_SHIFT)
118 
119 #define ERDMA_MAX_SQE_SIZE 128
120 #define ERDMA_MAX_WQEBB_PER_SQE 4
121 
122 /* CMDQ related. */
123 #define ERDMA_CMDQ_MAX_OUTSTANDING 128
124 #define ERDMA_CMDQ_SQE_SIZE 128
125 
126 /* cmdq sub module definition. */
127 enum CMDQ_WQE_SUB_MOD {
128 	CMDQ_SUBMOD_RDMA = 0,
129 	CMDQ_SUBMOD_COMMON = 1
130 };
131 
132 enum CMDQ_RDMA_OPCODE {
133 	CMDQ_OPCODE_QUERY_DEVICE = 0,
134 	CMDQ_OPCODE_CREATE_QP = 1,
135 	CMDQ_OPCODE_DESTROY_QP = 2,
136 	CMDQ_OPCODE_MODIFY_QP = 3,
137 	CMDQ_OPCODE_CREATE_CQ = 4,
138 	CMDQ_OPCODE_DESTROY_CQ = 5,
139 	CMDQ_OPCODE_REFLUSH = 6,
140 	CMDQ_OPCODE_REG_MR = 8,
141 	CMDQ_OPCODE_DEREG_MR = 9
142 };
143 
144 enum CMDQ_COMMON_OPCODE {
145 	CMDQ_OPCODE_CREATE_EQ = 0,
146 	CMDQ_OPCODE_DESTROY_EQ = 1,
147 	CMDQ_OPCODE_QUERY_FW_INFO = 2,
148 	CMDQ_OPCODE_CONF_MTU = 3,
149 	CMDQ_OPCODE_CONF_DEVICE = 5,
150 	CMDQ_OPCODE_ALLOC_DB = 8,
151 	CMDQ_OPCODE_FREE_DB = 9,
152 };
153 
154 /* cmdq-SQE HDR */
155 #define ERDMA_CMD_HDR_WQEBB_CNT_MASK GENMASK_ULL(54, 52)
156 #define ERDMA_CMD_HDR_CONTEXT_COOKIE_MASK GENMASK_ULL(47, 32)
157 #define ERDMA_CMD_HDR_SUB_MOD_MASK GENMASK_ULL(25, 24)
158 #define ERDMA_CMD_HDR_OPCODE_MASK GENMASK_ULL(23, 16)
159 #define ERDMA_CMD_HDR_WQEBB_INDEX_MASK GENMASK_ULL(15, 0)
160 
161 struct erdma_cmdq_destroy_cq_req {
162 	u64 hdr;
163 	u32 cqn;
164 };
165 
166 #define ERDMA_EQ_TYPE_AEQ 0
167 #define ERDMA_EQ_TYPE_CEQ 1
168 
169 struct erdma_cmdq_create_eq_req {
170 	u64 hdr;
171 	u64 qbuf_addr;
172 	u8 vector_idx;
173 	u8 eqn;
174 	u8 depth;
175 	u8 qtype;
176 	u32 db_dma_addr_l;
177 	u32 db_dma_addr_h;
178 };
179 
180 struct erdma_cmdq_destroy_eq_req {
181 	u64 hdr;
182 	u64 rsvd0;
183 	u8 vector_idx;
184 	u8 eqn;
185 	u8 rsvd1;
186 	u8 qtype;
187 };
188 
189 /* config device cfg */
190 #define ERDMA_CMD_CONFIG_DEVICE_PS_EN_MASK BIT(31)
191 #define ERDMA_CMD_CONFIG_DEVICE_PGSHIFT_MASK GENMASK(4, 0)
192 
193 struct erdma_cmdq_config_device_req {
194 	u64 hdr;
195 	u32 cfg;
196 	u32 rsvd[5];
197 };
198 
199 struct erdma_cmdq_config_mtu_req {
200 	u64 hdr;
201 	u32 mtu;
202 };
203 
204 /* ext db requests(alloc and free) cfg */
205 #define ERDMA_CMD_EXT_DB_CQ_EN_MASK BIT(2)
206 #define ERDMA_CMD_EXT_DB_RQ_EN_MASK BIT(1)
207 #define ERDMA_CMD_EXT_DB_SQ_EN_MASK BIT(0)
208 
209 struct erdma_cmdq_ext_db_req {
210 	u64 hdr;
211 	u32 cfg;
212 	u16 rdb_off;
213 	u16 sdb_off;
214 	u16 rsvd0;
215 	u16 cdb_off;
216 	u32 rsvd1[3];
217 };
218 
219 /* alloc db response qword 0 definition */
220 #define ERDMA_CMD_ALLOC_DB_RESP_RDB_MASK GENMASK_ULL(63, 48)
221 #define ERDMA_CMD_ALLOC_DB_RESP_CDB_MASK GENMASK_ULL(47, 32)
222 #define ERDMA_CMD_ALLOC_DB_RESP_SDB_MASK GENMASK_ULL(15, 0)
223 
224 /* create_cq cfg0 */
225 #define ERDMA_CMD_CREATE_CQ_DEPTH_MASK GENMASK(31, 24)
226 #define ERDMA_CMD_CREATE_CQ_PAGESIZE_MASK GENMASK(23, 20)
227 #define ERDMA_CMD_CREATE_CQ_CQN_MASK GENMASK(19, 0)
228 
229 /* create_cq cfg1 */
230 #define ERDMA_CMD_CREATE_CQ_MTT_CNT_MASK GENMASK(31, 16)
231 #define ERDMA_CMD_CREATE_CQ_MTT_LEVEL_MASK BIT(15)
232 #define ERDMA_CMD_CREATE_CQ_MTT_DB_CFG_MASK BIT(11)
233 #define ERDMA_CMD_CREATE_CQ_EQN_MASK GENMASK(9, 0)
234 
235 /* create_cq cfg2 */
236 #define ERDMA_CMD_CREATE_CQ_DB_CFG_MASK GENMASK(15, 0)
237 
238 struct erdma_cmdq_create_cq_req {
239 	u64 hdr;
240 	u32 cfg0;
241 	u32 qbuf_addr_l;
242 	u32 qbuf_addr_h;
243 	u32 cfg1;
244 	u64 cq_db_info_addr;
245 	u32 first_page_offset;
246 	u32 cfg2;
247 };
248 
249 /* regmr/deregmr cfg0 */
250 #define ERDMA_CMD_MR_VALID_MASK BIT(31)
251 #define ERDMA_CMD_MR_VERSION_MASK GENMASK(30, 28)
252 #define ERDMA_CMD_MR_KEY_MASK GENMASK(27, 20)
253 #define ERDMA_CMD_MR_MPT_IDX_MASK GENMASK(19, 0)
254 
255 /* regmr cfg1 */
256 #define ERDMA_CMD_REGMR_PD_MASK GENMASK(31, 12)
257 #define ERDMA_CMD_REGMR_TYPE_MASK GENMASK(7, 6)
258 #define ERDMA_CMD_REGMR_RIGHT_MASK GENMASK(5, 1)
259 
260 /* regmr cfg2 */
261 #define ERDMA_CMD_REGMR_PAGESIZE_MASK GENMASK(31, 27)
262 #define ERDMA_CMD_REGMR_MTT_PAGESIZE_MASK GENMASK(26, 24)
263 #define ERDMA_CMD_REGMR_MTT_LEVEL_MASK GENMASK(21, 20)
264 #define ERDMA_CMD_REGMR_MTT_CNT_MASK GENMASK(19, 0)
265 
266 struct erdma_cmdq_reg_mr_req {
267 	u64 hdr;
268 	u32 cfg0;
269 	u32 cfg1;
270 	u64 start_va;
271 	u32 size;
272 	u32 cfg2;
273 	union {
274 		u64 phy_addr[4];
275 		struct {
276 			u64 rsvd;
277 			u32 size_h;
278 			u32 mtt_cnt_h;
279 		};
280 	};
281 };
282 
283 struct erdma_cmdq_dereg_mr_req {
284 	u64 hdr;
285 	u32 cfg;
286 };
287 
288 /* modify qp cfg */
289 #define ERDMA_CMD_MODIFY_QP_STATE_MASK GENMASK(31, 24)
290 #define ERDMA_CMD_MODIFY_QP_CC_MASK GENMASK(23, 20)
291 #define ERDMA_CMD_MODIFY_QP_QPN_MASK GENMASK(19, 0)
292 
293 struct erdma_cmdq_modify_qp_req {
294 	u64 hdr;
295 	u32 cfg;
296 	u32 cookie;
297 	__be32 dip;
298 	__be32 sip;
299 	__be16 sport;
300 	__be16 dport;
301 	u32 send_nxt;
302 	u32 recv_nxt;
303 };
304 
305 /* create qp cfg0 */
306 #define ERDMA_CMD_CREATE_QP_SQ_DEPTH_MASK GENMASK(31, 20)
307 #define ERDMA_CMD_CREATE_QP_QPN_MASK GENMASK(19, 0)
308 
309 /* create qp cfg1 */
310 #define ERDMA_CMD_CREATE_QP_RQ_DEPTH_MASK GENMASK(31, 20)
311 #define ERDMA_CMD_CREATE_QP_PD_MASK GENMASK(19, 0)
312 
313 /* create qp cqn_mtt_cfg */
314 #define ERDMA_CMD_CREATE_QP_PAGE_SIZE_MASK GENMASK(31, 28)
315 #define ERDMA_CMD_CREATE_QP_DB_CFG_MASK BIT(25)
316 #define ERDMA_CMD_CREATE_QP_CQN_MASK GENMASK(23, 0)
317 
318 /* create qp mtt_cfg */
319 #define ERDMA_CMD_CREATE_QP_PAGE_OFFSET_MASK GENMASK(31, 12)
320 #define ERDMA_CMD_CREATE_QP_MTT_CNT_MASK GENMASK(11, 1)
321 #define ERDMA_CMD_CREATE_QP_MTT_LEVEL_MASK BIT(0)
322 
323 /* create qp db cfg */
324 #define ERDMA_CMD_CREATE_QP_SQDB_CFG_MASK GENMASK(31, 16)
325 #define ERDMA_CMD_CREATE_QP_RQDB_CFG_MASK GENMASK(15, 0)
326 
327 #define ERDMA_CMDQ_CREATE_QP_RESP_COOKIE_MASK GENMASK_ULL(31, 0)
328 
329 struct erdma_cmdq_create_qp_req {
330 	u64 hdr;
331 	u32 cfg0;
332 	u32 cfg1;
333 	u32 sq_cqn_mtt_cfg;
334 	u32 rq_cqn_mtt_cfg;
335 	u64 sq_buf_addr;
336 	u64 rq_buf_addr;
337 	u32 sq_mtt_cfg;
338 	u32 rq_mtt_cfg;
339 	u64 sq_db_info_dma_addr;
340 	u64 rq_db_info_dma_addr;
341 
342 	u64 sq_mtt_entry[3];
343 	u64 rq_mtt_entry[3];
344 
345 	u32 db_cfg;
346 };
347 
348 struct erdma_cmdq_destroy_qp_req {
349 	u64 hdr;
350 	u32 qpn;
351 };
352 
353 struct erdma_cmdq_reflush_req {
354 	u64 hdr;
355 	u32 qpn;
356 	u32 sq_pi;
357 	u32 rq_pi;
358 };
359 
360 /* cap qword 0 definition */
361 #define ERDMA_CMD_DEV_CAP_MAX_CQE_MASK GENMASK_ULL(47, 40)
362 #define ERDMA_CMD_DEV_CAP_FLAGS_MASK GENMASK_ULL(31, 24)
363 #define ERDMA_CMD_DEV_CAP_MAX_RECV_WR_MASK GENMASK_ULL(23, 16)
364 #define ERDMA_CMD_DEV_CAP_MAX_MR_SIZE_MASK GENMASK_ULL(7, 0)
365 
366 /* cap qword 1 definition */
367 #define ERDMA_CMD_DEV_CAP_DMA_LOCAL_KEY_MASK GENMASK_ULL(63, 32)
368 #define ERDMA_CMD_DEV_CAP_DEFAULT_CC_MASK GENMASK_ULL(31, 28)
369 #define ERDMA_CMD_DEV_CAP_QBLOCK_MASK GENMASK_ULL(27, 16)
370 #define ERDMA_CMD_DEV_CAP_MAX_MW_MASK GENMASK_ULL(7, 0)
371 
372 #define ERDMA_NQP_PER_QBLOCK 1024
373 
374 enum {
375 	ERDMA_DEV_CAP_FLAGS_ATOMIC = 1 << 7,
376 	ERDMA_DEV_CAP_FLAGS_MTT_VA = 1 << 5,
377 	ERDMA_DEV_CAP_FLAGS_EXTEND_DB = 1 << 3,
378 };
379 
380 #define ERDMA_CMD_INFO0_FW_VER_MASK GENMASK_ULL(31, 0)
381 
382 /* CQE hdr */
383 #define ERDMA_CQE_HDR_OWNER_MASK BIT(31)
384 #define ERDMA_CQE_HDR_OPCODE_MASK GENMASK(23, 16)
385 #define ERDMA_CQE_HDR_QTYPE_MASK GENMASK(15, 8)
386 #define ERDMA_CQE_HDR_SYNDROME_MASK GENMASK(7, 0)
387 
388 #define ERDMA_CQE_QTYPE_SQ 0
389 #define ERDMA_CQE_QTYPE_RQ 1
390 #define ERDMA_CQE_QTYPE_CMDQ 2
391 
392 struct erdma_cqe {
393 	__be32 hdr;
394 	__be32 qe_idx;
395 	__be32 qpn;
396 	union {
397 		__le32 imm_data;
398 		__be32 inv_rkey;
399 	};
400 	__be32 size;
401 	__be32 rsvd[3];
402 };
403 
404 struct erdma_sge {
405 	__aligned_le64 addr;
406 	__le32 length;
407 	__le32 key;
408 };
409 
410 /* Receive Queue Element */
411 struct erdma_rqe {
412 	__le16 qe_idx;
413 	__le16 rsvd0;
414 	__le32 qpn;
415 	__le32 rsvd1;
416 	__le32 rsvd2;
417 	__le64 to;
418 	__le32 length;
419 	__le32 stag;
420 };
421 
422 /* SQE */
423 #define ERDMA_SQE_HDR_SGL_LEN_MASK GENMASK_ULL(63, 56)
424 #define ERDMA_SQE_HDR_WQEBB_CNT_MASK GENMASK_ULL(54, 52)
425 #define ERDMA_SQE_HDR_QPN_MASK GENMASK_ULL(51, 32)
426 #define ERDMA_SQE_HDR_OPCODE_MASK GENMASK_ULL(31, 27)
427 #define ERDMA_SQE_HDR_DWQE_MASK BIT_ULL(26)
428 #define ERDMA_SQE_HDR_INLINE_MASK BIT_ULL(25)
429 #define ERDMA_SQE_HDR_FENCE_MASK BIT_ULL(24)
430 #define ERDMA_SQE_HDR_SE_MASK BIT_ULL(23)
431 #define ERDMA_SQE_HDR_CE_MASK BIT_ULL(22)
432 #define ERDMA_SQE_HDR_WQEBB_INDEX_MASK GENMASK_ULL(15, 0)
433 
434 /* REG MR attrs */
435 #define ERDMA_SQE_MR_ACCESS_MASK GENMASK(5, 1)
436 #define ERDMA_SQE_MR_MTT_TYPE_MASK GENMASK(7, 6)
437 #define ERDMA_SQE_MR_MTT_CNT_MASK GENMASK(31, 12)
438 
439 struct erdma_write_sqe {
440 	__le64 hdr;
441 	__be32 imm_data;
442 	__le32 length;
443 
444 	__le32 sink_stag;
445 	__le32 sink_to_l;
446 	__le32 sink_to_h;
447 
448 	__le32 rsvd;
449 
450 	struct erdma_sge sgl[];
451 };
452 
453 struct erdma_send_sqe {
454 	__le64 hdr;
455 	union {
456 		__be32 imm_data;
457 		__le32 invalid_stag;
458 	};
459 
460 	__le32 length;
461 	struct erdma_sge sgl[];
462 };
463 
464 struct erdma_readreq_sqe {
465 	__le64 hdr;
466 	__le32 invalid_stag;
467 	__le32 length;
468 	__le32 sink_stag;
469 	__le32 sink_to_l;
470 	__le32 sink_to_h;
471 	__le32 rsvd;
472 };
473 
474 struct erdma_atomic_sqe {
475 	__le64 hdr;
476 	__le64 rsvd;
477 	__le64 fetchadd_swap_data;
478 	__le64 cmp_data;
479 
480 	struct erdma_sge remote;
481 	struct erdma_sge sgl;
482 };
483 
484 struct erdma_reg_mr_sqe {
485 	__le64 hdr;
486 	__le64 addr;
487 	__le32 length;
488 	__le32 stag;
489 	__le32 attrs;
490 	__le32 rsvd;
491 };
492 
493 /* EQ related. */
494 #define ERDMA_DEFAULT_EQ_DEPTH 4096
495 
496 /* ceqe */
497 #define ERDMA_CEQE_HDR_DB_MASK BIT_ULL(63)
498 #define ERDMA_CEQE_HDR_PI_MASK GENMASK_ULL(55, 32)
499 #define ERDMA_CEQE_HDR_O_MASK BIT_ULL(31)
500 #define ERDMA_CEQE_HDR_CQN_MASK GENMASK_ULL(19, 0)
501 
502 /* aeqe */
503 #define ERDMA_AEQE_HDR_O_MASK BIT(31)
504 #define ERDMA_AEQE_HDR_TYPE_MASK GENMASK(23, 16)
505 #define ERDMA_AEQE_HDR_SUBTYPE_MASK GENMASK(7, 0)
506 
507 #define ERDMA_AE_TYPE_QP_FATAL_EVENT 0
508 #define ERDMA_AE_TYPE_QP_ERQ_ERR_EVENT 1
509 #define ERDMA_AE_TYPE_ACC_ERR_EVENT 2
510 #define ERDMA_AE_TYPE_CQ_ERR 3
511 #define ERDMA_AE_TYPE_OTHER_ERROR 4
512 
513 struct erdma_aeqe {
514 	__le32 hdr;
515 	__le32 event_data0;
516 	__le32 event_data1;
517 	__le32 rsvd;
518 };
519 
520 enum erdma_opcode {
521 	ERDMA_OP_WRITE = 0,
522 	ERDMA_OP_READ = 1,
523 	ERDMA_OP_SEND = 2,
524 	ERDMA_OP_SEND_WITH_IMM = 3,
525 
526 	ERDMA_OP_RECEIVE = 4,
527 	ERDMA_OP_RECV_IMM = 5,
528 	ERDMA_OP_RECV_INV = 6,
529 
530 	ERDMA_OP_RSVD0 = 7,
531 	ERDMA_OP_RSVD1 = 8,
532 	ERDMA_OP_WRITE_WITH_IMM = 9,
533 
534 	ERDMA_OP_RSVD2 = 10,
535 	ERDMA_OP_RSVD3 = 11,
536 
537 	ERDMA_OP_RSP_SEND_IMM = 12,
538 	ERDMA_OP_SEND_WITH_INV = 13,
539 
540 	ERDMA_OP_REG_MR = 14,
541 	ERDMA_OP_LOCAL_INV = 15,
542 	ERDMA_OP_READ_WITH_INV = 16,
543 	ERDMA_OP_ATOMIC_CAS = 17,
544 	ERDMA_OP_ATOMIC_FAA = 18,
545 	ERDMA_NUM_OPCODES = 19,
546 	ERDMA_OP_INVALID = ERDMA_NUM_OPCODES + 1
547 };
548 
549 enum erdma_wc_status {
550 	ERDMA_WC_SUCCESS = 0,
551 	ERDMA_WC_GENERAL_ERR = 1,
552 	ERDMA_WC_RECV_WQE_FORMAT_ERR = 2,
553 	ERDMA_WC_RECV_STAG_INVALID_ERR = 3,
554 	ERDMA_WC_RECV_ADDR_VIOLATION_ERR = 4,
555 	ERDMA_WC_RECV_RIGHT_VIOLATION_ERR = 5,
556 	ERDMA_WC_RECV_PDID_ERR = 6,
557 	ERDMA_WC_RECV_WARRPING_ERR = 7,
558 	ERDMA_WC_SEND_WQE_FORMAT_ERR = 8,
559 	ERDMA_WC_SEND_WQE_ORD_EXCEED = 9,
560 	ERDMA_WC_SEND_STAG_INVALID_ERR = 10,
561 	ERDMA_WC_SEND_ADDR_VIOLATION_ERR = 11,
562 	ERDMA_WC_SEND_RIGHT_VIOLATION_ERR = 12,
563 	ERDMA_WC_SEND_PDID_ERR = 13,
564 	ERDMA_WC_SEND_WARRPING_ERR = 14,
565 	ERDMA_WC_FLUSH_ERR = 15,
566 	ERDMA_WC_RETRY_EXC_ERR = 16,
567 	ERDMA_NUM_WC_STATUS
568 };
569 
570 enum erdma_vendor_err {
571 	ERDMA_WC_VENDOR_NO_ERR = 0,
572 	ERDMA_WC_VENDOR_INVALID_RQE = 1,
573 	ERDMA_WC_VENDOR_RQE_INVALID_STAG = 2,
574 	ERDMA_WC_VENDOR_RQE_ADDR_VIOLATION = 3,
575 	ERDMA_WC_VENDOR_RQE_ACCESS_RIGHT_ERR = 4,
576 	ERDMA_WC_VENDOR_RQE_INVALID_PD = 5,
577 	ERDMA_WC_VENDOR_RQE_WRAP_ERR = 6,
578 	ERDMA_WC_VENDOR_INVALID_SQE = 0x20,
579 	ERDMA_WC_VENDOR_ZERO_ORD = 0x21,
580 	ERDMA_WC_VENDOR_SQE_INVALID_STAG = 0x30,
581 	ERDMA_WC_VENDOR_SQE_ADDR_VIOLATION = 0x31,
582 	ERDMA_WC_VENDOR_SQE_ACCESS_ERR = 0x32,
583 	ERDMA_WC_VENDOR_SQE_INVALID_PD = 0x33,
584 	ERDMA_WC_VENDOR_SQE_WARP_ERR = 0x34
585 };
586 
587 #endif
588