1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * (C) Copyright 2015 Google, Inc
4 */
5
6 #ifndef _ASM_ARCH_CLOCK_H
7 #define _ASM_ARCH_CLOCK_H
8
9 /* define pll mode */
10 #define RKCLK_PLL_MODE_SLOW 0
11 #define RKCLK_PLL_MODE_NORMAL 1
12
13 enum {
14 ROCKCHIP_SYSCON_NOC,
15 ROCKCHIP_SYSCON_GRF,
16 ROCKCHIP_SYSCON_SGRF,
17 ROCKCHIP_SYSCON_PMU,
18 ROCKCHIP_SYSCON_PMUGRF,
19 ROCKCHIP_SYSCON_PMUSGRF,
20 ROCKCHIP_SYSCON_CIC,
21 ROCKCHIP_SYSCON_MSCH,
22 };
23
24 /* Standard Rockchip clock numbers */
25 enum rk_clk_id {
26 CLK_OSC,
27 CLK_ARM,
28 CLK_DDR,
29 CLK_CODEC,
30 CLK_GENERAL,
31 CLK_NEW,
32
33 CLK_COUNT,
34 };
35
rk_pll_id(enum rk_clk_id clk_id)36 static inline int rk_pll_id(enum rk_clk_id clk_id)
37 {
38 return clk_id - 1;
39 }
40
41 struct sysreset_reg {
42 unsigned int glb_srst_fst_value;
43 unsigned int glb_srst_snd_value;
44 };
45
46 struct softreset_reg {
47 void __iomem *base;
48 unsigned int sf_reset_offset;
49 unsigned int sf_reset_num;
50 };
51
52 /**
53 * clk_get_divisor() - Calculate the required clock divisior
54 *
55 * Given an input rate and a required output_rate, calculate the Rockchip
56 * divisor needed to achieve this.
57 *
58 * @input_rate: Input clock rate in Hz
59 * @output_rate: Output clock rate in Hz
60 * @return divisor register value to use
61 */
clk_get_divisor(ulong input_rate,uint output_rate)62 static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
63 {
64 uint clk_div;
65
66 clk_div = input_rate / output_rate;
67 clk_div = (clk_div + 1) & 0xfffe;
68
69 return clk_div;
70 }
71
72 /**
73 * rockchip_get_cru() - get a pointer to the clock/reset unit registers
74 *
75 * @return pointer to registers, or -ve error on error
76 */
77 void *rockchip_get_cru(void);
78
79 /**
80 * rockchip_get_pmucru() - get a pointer to the clock/reset unit registers
81 *
82 * @return pointer to registers, or -ve error on error
83 */
84 void *rockchip_get_pmucru(void);
85
86 struct rk3288_cru;
87 struct rk3288_grf;
88
89 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf);
90
91 int rockchip_get_clk(struct udevice **devp);
92
93 /*
94 * rockchip_reset_bind() - Bind soft reset device as child of clock device
95 *
96 * @pdev: clock udevice
97 * @reg_offset: the first offset in cru for softreset registers
98 * @reg_number: the reg numbers of softreset registers
99 * @return 0 success, or error value
100 */
101 int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
102
103 #endif
104