1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Freescale i.MX7ULP LPSPI driver
4 //
5 // Copyright 2016 Freescale Semiconductor, Inc.
6 // Copyright 2018 NXP Semiconductors
7
8 #include <linux/clk.h>
9 #include <linux/completion.h>
10 #include <linux/delay.h>
11 #include <linux/dmaengine.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/err.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/irq.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma/imx-dma.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/slab.h>
25 #include <linux/spi/spi.h>
26 #include <linux/spi/spi_bitbang.h>
27 #include <linux/types.h>
28
29 #define DRIVER_NAME "fsl_lpspi"
30
31 #define FSL_LPSPI_RPM_TIMEOUT 50 /* 50ms */
32
33 /* The maximum bytes that edma can transfer once.*/
34 #define FSL_LPSPI_MAX_EDMA_BYTES ((1 << 15) - 1)
35
36 /* i.MX7ULP LPSPI registers */
37 #define IMX7ULP_VERID 0x0
38 #define IMX7ULP_PARAM 0x4
39 #define IMX7ULP_CR 0x10
40 #define IMX7ULP_SR 0x14
41 #define IMX7ULP_IER 0x18
42 #define IMX7ULP_DER 0x1c
43 #define IMX7ULP_CFGR0 0x20
44 #define IMX7ULP_CFGR1 0x24
45 #define IMX7ULP_DMR0 0x30
46 #define IMX7ULP_DMR1 0x34
47 #define IMX7ULP_CCR 0x40
48 #define IMX7ULP_FCR 0x58
49 #define IMX7ULP_FSR 0x5c
50 #define IMX7ULP_TCR 0x60
51 #define IMX7ULP_TDR 0x64
52 #define IMX7ULP_RSR 0x70
53 #define IMX7ULP_RDR 0x74
54
55 /* General control register field define */
56 #define CR_RRF BIT(9)
57 #define CR_RTF BIT(8)
58 #define CR_RST BIT(1)
59 #define CR_MEN BIT(0)
60 #define SR_MBF BIT(24)
61 #define SR_TCF BIT(10)
62 #define SR_FCF BIT(9)
63 #define SR_RDF BIT(1)
64 #define SR_TDF BIT(0)
65 #define IER_TCIE BIT(10)
66 #define IER_FCIE BIT(9)
67 #define IER_RDIE BIT(1)
68 #define IER_TDIE BIT(0)
69 #define DER_RDDE BIT(1)
70 #define DER_TDDE BIT(0)
71 #define CFGR1_PCSCFG BIT(27)
72 #define CFGR1_PINCFG (BIT(24)|BIT(25))
73 #define CFGR1_PCSPOL BIT(8)
74 #define CFGR1_NOSTALL BIT(3)
75 #define CFGR1_HOST BIT(0)
76 #define FSR_TXCOUNT (0xFF)
77 #define RSR_RXEMPTY BIT(1)
78 #define TCR_CPOL BIT(31)
79 #define TCR_CPHA BIT(30)
80 #define TCR_CONT BIT(21)
81 #define TCR_CONTC BIT(20)
82 #define TCR_RXMSK BIT(19)
83 #define TCR_TXMSK BIT(18)
84
85 struct lpspi_config {
86 u8 bpw;
87 u8 chip_select;
88 u8 prescale;
89 u16 mode;
90 u32 speed_hz;
91 };
92
93 struct fsl_lpspi_data {
94 struct device *dev;
95 void __iomem *base;
96 unsigned long base_phys;
97 struct clk *clk_ipg;
98 struct clk *clk_per;
99 bool is_target;
100 bool is_only_cs1;
101 bool is_first_byte;
102
103 void *rx_buf;
104 const void *tx_buf;
105 void (*tx)(struct fsl_lpspi_data *);
106 void (*rx)(struct fsl_lpspi_data *);
107
108 u32 remain;
109 u8 watermark;
110 u8 txfifosize;
111 u8 rxfifosize;
112
113 struct lpspi_config config;
114 struct completion xfer_done;
115
116 bool target_aborted;
117
118 /* DMA */
119 bool usedma;
120 struct completion dma_rx_completion;
121 struct completion dma_tx_completion;
122 };
123
124 static const struct of_device_id fsl_lpspi_dt_ids[] = {
125 { .compatible = "fsl,imx7ulp-spi", },
126 { /* sentinel */ }
127 };
128 MODULE_DEVICE_TABLE(of, fsl_lpspi_dt_ids);
129
130 #define LPSPI_BUF_RX(type) \
131 static void fsl_lpspi_buf_rx_##type(struct fsl_lpspi_data *fsl_lpspi) \
132 { \
133 unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \
134 \
135 if (fsl_lpspi->rx_buf) { \
136 *(type *)fsl_lpspi->rx_buf = val; \
137 fsl_lpspi->rx_buf += sizeof(type); \
138 } \
139 }
140
141 #define LPSPI_BUF_TX(type) \
142 static void fsl_lpspi_buf_tx_##type(struct fsl_lpspi_data *fsl_lpspi) \
143 { \
144 type val = 0; \
145 \
146 if (fsl_lpspi->tx_buf) { \
147 val = *(type *)fsl_lpspi->tx_buf; \
148 fsl_lpspi->tx_buf += sizeof(type); \
149 } \
150 \
151 fsl_lpspi->remain -= sizeof(type); \
152 writel(val, fsl_lpspi->base + IMX7ULP_TDR); \
153 }
154
155 LPSPI_BUF_RX(u8)
LPSPI_BUF_TX(u8)156 LPSPI_BUF_TX(u8)
157 LPSPI_BUF_RX(u16)
158 LPSPI_BUF_TX(u16)
159 LPSPI_BUF_RX(u32)
160 LPSPI_BUF_TX(u32)
161
162 static void fsl_lpspi_intctrl(struct fsl_lpspi_data *fsl_lpspi,
163 unsigned int enable)
164 {
165 writel(enable, fsl_lpspi->base + IMX7ULP_IER);
166 }
167
fsl_lpspi_bytes_per_word(const int bpw)168 static int fsl_lpspi_bytes_per_word(const int bpw)
169 {
170 return DIV_ROUND_UP(bpw, BITS_PER_BYTE);
171 }
172
fsl_lpspi_can_dma(struct spi_controller * controller,struct spi_device * spi,struct spi_transfer * transfer)173 static bool fsl_lpspi_can_dma(struct spi_controller *controller,
174 struct spi_device *spi,
175 struct spi_transfer *transfer)
176 {
177 unsigned int bytes_per_word;
178
179 if (!controller->dma_rx)
180 return false;
181
182 bytes_per_word = fsl_lpspi_bytes_per_word(transfer->bits_per_word);
183
184 switch (bytes_per_word) {
185 case 1:
186 case 2:
187 case 4:
188 break;
189 default:
190 return false;
191 }
192
193 return true;
194 }
195
lpspi_prepare_xfer_hardware(struct spi_controller * controller)196 static int lpspi_prepare_xfer_hardware(struct spi_controller *controller)
197 {
198 struct fsl_lpspi_data *fsl_lpspi =
199 spi_controller_get_devdata(controller);
200 int ret;
201
202 ret = pm_runtime_resume_and_get(fsl_lpspi->dev);
203 if (ret < 0) {
204 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
205 return ret;
206 }
207
208 return 0;
209 }
210
lpspi_unprepare_xfer_hardware(struct spi_controller * controller)211 static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller)
212 {
213 struct fsl_lpspi_data *fsl_lpspi =
214 spi_controller_get_devdata(controller);
215
216 pm_runtime_mark_last_busy(fsl_lpspi->dev);
217 pm_runtime_put_autosuspend(fsl_lpspi->dev);
218
219 return 0;
220 }
221
fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data * fsl_lpspi)222 static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi)
223 {
224 u8 txfifo_cnt;
225 u32 temp;
226
227 txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
228
229 while (txfifo_cnt < fsl_lpspi->txfifosize) {
230 if (!fsl_lpspi->remain)
231 break;
232 fsl_lpspi->tx(fsl_lpspi);
233 txfifo_cnt++;
234 }
235
236 if (txfifo_cnt < fsl_lpspi->txfifosize) {
237 if (!fsl_lpspi->is_target) {
238 temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
239 temp &= ~TCR_CONTC;
240 writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
241 }
242
243 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
244 } else
245 fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE);
246 }
247
fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data * fsl_lpspi)248 static void fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data *fsl_lpspi)
249 {
250 while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY))
251 fsl_lpspi->rx(fsl_lpspi);
252 }
253
fsl_lpspi_set_cmd(struct fsl_lpspi_data * fsl_lpspi)254 static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi)
255 {
256 u32 temp = 0;
257
258 temp |= fsl_lpspi->config.bpw - 1;
259 temp |= (fsl_lpspi->config.mode & 0x3) << 30;
260 temp |= (fsl_lpspi->config.chip_select & 0x3) << 24;
261 if (!fsl_lpspi->is_target) {
262 temp |= fsl_lpspi->config.prescale << 27;
263 /*
264 * Set TCR_CONT will keep SS asserted after current transfer.
265 * For the first transfer, clear TCR_CONTC to assert SS.
266 * For subsequent transfer, set TCR_CONTC to keep SS asserted.
267 */
268 if (!fsl_lpspi->usedma) {
269 temp |= TCR_CONT;
270 if (fsl_lpspi->is_first_byte)
271 temp &= ~TCR_CONTC;
272 else
273 temp |= TCR_CONTC;
274 }
275 }
276 writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
277
278 dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp);
279 }
280
fsl_lpspi_set_watermark(struct fsl_lpspi_data * fsl_lpspi)281 static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi)
282 {
283 u32 temp;
284
285 if (!fsl_lpspi->usedma)
286 temp = fsl_lpspi->watermark >> 1 |
287 (fsl_lpspi->watermark >> 1) << 16;
288 else
289 temp = fsl_lpspi->watermark >> 1;
290
291 writel(temp, fsl_lpspi->base + IMX7ULP_FCR);
292
293 dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp);
294 }
295
fsl_lpspi_set_bitrate(struct fsl_lpspi_data * fsl_lpspi)296 static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
297 {
298 struct lpspi_config config = fsl_lpspi->config;
299 unsigned int perclk_rate, scldiv, div;
300 u8 prescale;
301
302 perclk_rate = clk_get_rate(fsl_lpspi->clk_per);
303
304 if (!config.speed_hz) {
305 dev_err(fsl_lpspi->dev,
306 "error: the transmission speed provided is 0!\n");
307 return -EINVAL;
308 }
309
310 if (config.speed_hz > perclk_rate / 2) {
311 dev_err(fsl_lpspi->dev,
312 "per-clk should be at least two times of transfer speed");
313 return -EINVAL;
314 }
315
316 div = DIV_ROUND_UP(perclk_rate, config.speed_hz);
317
318 for (prescale = 0; prescale < 8; prescale++) {
319 scldiv = div / (1 << prescale) - 2;
320 if (scldiv < 256) {
321 fsl_lpspi->config.prescale = prescale;
322 break;
323 }
324 }
325
326 if (scldiv >= 256)
327 return -EINVAL;
328
329 writel(scldiv | (scldiv << 8) | ((scldiv >> 1) << 16),
330 fsl_lpspi->base + IMX7ULP_CCR);
331
332 dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale=%d, scldiv=%d\n",
333 perclk_rate, config.speed_hz, prescale, scldiv);
334
335 return 0;
336 }
337
fsl_lpspi_dma_configure(struct spi_controller * controller)338 static int fsl_lpspi_dma_configure(struct spi_controller *controller)
339 {
340 int ret;
341 enum dma_slave_buswidth buswidth;
342 struct dma_slave_config rx = {}, tx = {};
343 struct fsl_lpspi_data *fsl_lpspi =
344 spi_controller_get_devdata(controller);
345
346 switch (fsl_lpspi_bytes_per_word(fsl_lpspi->config.bpw)) {
347 case 4:
348 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
349 break;
350 case 2:
351 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
352 break;
353 case 1:
354 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
355 break;
356 default:
357 return -EINVAL;
358 }
359
360 tx.direction = DMA_MEM_TO_DEV;
361 tx.dst_addr = fsl_lpspi->base_phys + IMX7ULP_TDR;
362 tx.dst_addr_width = buswidth;
363 tx.dst_maxburst = 1;
364 ret = dmaengine_slave_config(controller->dma_tx, &tx);
365 if (ret) {
366 dev_err(fsl_lpspi->dev, "TX dma configuration failed with %d\n",
367 ret);
368 return ret;
369 }
370
371 rx.direction = DMA_DEV_TO_MEM;
372 rx.src_addr = fsl_lpspi->base_phys + IMX7ULP_RDR;
373 rx.src_addr_width = buswidth;
374 rx.src_maxburst = 1;
375 ret = dmaengine_slave_config(controller->dma_rx, &rx);
376 if (ret) {
377 dev_err(fsl_lpspi->dev, "RX dma configuration failed with %d\n",
378 ret);
379 return ret;
380 }
381
382 return 0;
383 }
384
fsl_lpspi_config(struct fsl_lpspi_data * fsl_lpspi)385 static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
386 {
387 u32 temp;
388 int ret;
389
390 if (!fsl_lpspi->is_target) {
391 ret = fsl_lpspi_set_bitrate(fsl_lpspi);
392 if (ret)
393 return ret;
394 }
395
396 fsl_lpspi_set_watermark(fsl_lpspi);
397
398 if (!fsl_lpspi->is_target)
399 temp = CFGR1_HOST;
400 else
401 temp = CFGR1_PINCFG;
402 if (fsl_lpspi->config.mode & SPI_CS_HIGH)
403 temp |= CFGR1_PCSPOL;
404 writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
405
406 temp = readl(fsl_lpspi->base + IMX7ULP_CR);
407 temp |= CR_RRF | CR_RTF | CR_MEN;
408 writel(temp, fsl_lpspi->base + IMX7ULP_CR);
409
410 temp = 0;
411 if (fsl_lpspi->usedma)
412 temp = DER_TDDE | DER_RDDE;
413 writel(temp, fsl_lpspi->base + IMX7ULP_DER);
414
415 return 0;
416 }
417
fsl_lpspi_setup_transfer(struct spi_controller * controller,struct spi_device * spi,struct spi_transfer * t)418 static int fsl_lpspi_setup_transfer(struct spi_controller *controller,
419 struct spi_device *spi,
420 struct spi_transfer *t)
421 {
422 struct fsl_lpspi_data *fsl_lpspi =
423 spi_controller_get_devdata(spi->controller);
424
425 if (t == NULL)
426 return -EINVAL;
427
428 fsl_lpspi->config.mode = spi->mode;
429 fsl_lpspi->config.bpw = t->bits_per_word;
430 fsl_lpspi->config.speed_hz = t->speed_hz;
431 if (fsl_lpspi->is_only_cs1)
432 fsl_lpspi->config.chip_select = 1;
433 else
434 fsl_lpspi->config.chip_select = spi_get_chipselect(spi, 0);
435
436 if (!fsl_lpspi->config.speed_hz)
437 fsl_lpspi->config.speed_hz = spi->max_speed_hz;
438 if (!fsl_lpspi->config.bpw)
439 fsl_lpspi->config.bpw = spi->bits_per_word;
440
441 /* Initialize the functions for transfer */
442 if (fsl_lpspi->config.bpw <= 8) {
443 fsl_lpspi->rx = fsl_lpspi_buf_rx_u8;
444 fsl_lpspi->tx = fsl_lpspi_buf_tx_u8;
445 } else if (fsl_lpspi->config.bpw <= 16) {
446 fsl_lpspi->rx = fsl_lpspi_buf_rx_u16;
447 fsl_lpspi->tx = fsl_lpspi_buf_tx_u16;
448 } else {
449 fsl_lpspi->rx = fsl_lpspi_buf_rx_u32;
450 fsl_lpspi->tx = fsl_lpspi_buf_tx_u32;
451 }
452
453 if (t->len <= fsl_lpspi->txfifosize)
454 fsl_lpspi->watermark = t->len;
455 else
456 fsl_lpspi->watermark = fsl_lpspi->txfifosize;
457
458 if (fsl_lpspi_can_dma(controller, spi, t))
459 fsl_lpspi->usedma = true;
460 else
461 fsl_lpspi->usedma = false;
462
463 return fsl_lpspi_config(fsl_lpspi);
464 }
465
fsl_lpspi_target_abort(struct spi_controller * controller)466 static int fsl_lpspi_target_abort(struct spi_controller *controller)
467 {
468 struct fsl_lpspi_data *fsl_lpspi =
469 spi_controller_get_devdata(controller);
470
471 fsl_lpspi->target_aborted = true;
472 if (!fsl_lpspi->usedma)
473 complete(&fsl_lpspi->xfer_done);
474 else {
475 complete(&fsl_lpspi->dma_tx_completion);
476 complete(&fsl_lpspi->dma_rx_completion);
477 }
478
479 return 0;
480 }
481
fsl_lpspi_wait_for_completion(struct spi_controller * controller)482 static int fsl_lpspi_wait_for_completion(struct spi_controller *controller)
483 {
484 struct fsl_lpspi_data *fsl_lpspi =
485 spi_controller_get_devdata(controller);
486
487 if (fsl_lpspi->is_target) {
488 if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) ||
489 fsl_lpspi->target_aborted) {
490 dev_dbg(fsl_lpspi->dev, "interrupted\n");
491 return -EINTR;
492 }
493 } else {
494 if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) {
495 dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n");
496 return -ETIMEDOUT;
497 }
498 }
499
500 return 0;
501 }
502
fsl_lpspi_reset(struct fsl_lpspi_data * fsl_lpspi)503 static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi)
504 {
505 u32 temp;
506
507 if (!fsl_lpspi->usedma) {
508 /* Disable all interrupt */
509 fsl_lpspi_intctrl(fsl_lpspi, 0);
510 }
511
512 /* W1C for all flags in SR */
513 temp = 0x3F << 8;
514 writel(temp, fsl_lpspi->base + IMX7ULP_SR);
515
516 /* Clear FIFO and disable module */
517 temp = CR_RRF | CR_RTF;
518 writel(temp, fsl_lpspi->base + IMX7ULP_CR);
519
520 return 0;
521 }
522
fsl_lpspi_dma_rx_callback(void * cookie)523 static void fsl_lpspi_dma_rx_callback(void *cookie)
524 {
525 struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
526
527 complete(&fsl_lpspi->dma_rx_completion);
528 }
529
fsl_lpspi_dma_tx_callback(void * cookie)530 static void fsl_lpspi_dma_tx_callback(void *cookie)
531 {
532 struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
533
534 complete(&fsl_lpspi->dma_tx_completion);
535 }
536
fsl_lpspi_calculate_timeout(struct fsl_lpspi_data * fsl_lpspi,int size)537 static int fsl_lpspi_calculate_timeout(struct fsl_lpspi_data *fsl_lpspi,
538 int size)
539 {
540 unsigned long timeout = 0;
541
542 /* Time with actual data transfer and CS change delay related to HW */
543 timeout = (8 + 4) * size / fsl_lpspi->config.speed_hz;
544
545 /* Add extra second for scheduler related activities */
546 timeout += 1;
547
548 /* Double calculated timeout */
549 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
550 }
551
fsl_lpspi_dma_transfer(struct spi_controller * controller,struct fsl_lpspi_data * fsl_lpspi,struct spi_transfer * transfer)552 static int fsl_lpspi_dma_transfer(struct spi_controller *controller,
553 struct fsl_lpspi_data *fsl_lpspi,
554 struct spi_transfer *transfer)
555 {
556 struct dma_async_tx_descriptor *desc_tx, *desc_rx;
557 unsigned long transfer_timeout;
558 unsigned long timeout;
559 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
560 int ret;
561
562 ret = fsl_lpspi_dma_configure(controller);
563 if (ret)
564 return ret;
565
566 desc_rx = dmaengine_prep_slave_sg(controller->dma_rx,
567 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
568 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
569 if (!desc_rx)
570 return -EINVAL;
571
572 desc_rx->callback = fsl_lpspi_dma_rx_callback;
573 desc_rx->callback_param = (void *)fsl_lpspi;
574 dmaengine_submit(desc_rx);
575 reinit_completion(&fsl_lpspi->dma_rx_completion);
576 dma_async_issue_pending(controller->dma_rx);
577
578 desc_tx = dmaengine_prep_slave_sg(controller->dma_tx,
579 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
580 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
581 if (!desc_tx) {
582 dmaengine_terminate_all(controller->dma_tx);
583 return -EINVAL;
584 }
585
586 desc_tx->callback = fsl_lpspi_dma_tx_callback;
587 desc_tx->callback_param = (void *)fsl_lpspi;
588 dmaengine_submit(desc_tx);
589 reinit_completion(&fsl_lpspi->dma_tx_completion);
590 dma_async_issue_pending(controller->dma_tx);
591
592 fsl_lpspi->target_aborted = false;
593
594 if (!fsl_lpspi->is_target) {
595 transfer_timeout = fsl_lpspi_calculate_timeout(fsl_lpspi,
596 transfer->len);
597
598 /* Wait eDMA to finish the data transfer.*/
599 timeout = wait_for_completion_timeout(&fsl_lpspi->dma_tx_completion,
600 transfer_timeout);
601 if (!timeout) {
602 dev_err(fsl_lpspi->dev, "I/O Error in DMA TX\n");
603 dmaengine_terminate_all(controller->dma_tx);
604 dmaengine_terminate_all(controller->dma_rx);
605 fsl_lpspi_reset(fsl_lpspi);
606 return -ETIMEDOUT;
607 }
608
609 timeout = wait_for_completion_timeout(&fsl_lpspi->dma_rx_completion,
610 transfer_timeout);
611 if (!timeout) {
612 dev_err(fsl_lpspi->dev, "I/O Error in DMA RX\n");
613 dmaengine_terminate_all(controller->dma_tx);
614 dmaengine_terminate_all(controller->dma_rx);
615 fsl_lpspi_reset(fsl_lpspi);
616 return -ETIMEDOUT;
617 }
618 } else {
619 if (wait_for_completion_interruptible(&fsl_lpspi->dma_tx_completion) ||
620 fsl_lpspi->target_aborted) {
621 dev_dbg(fsl_lpspi->dev,
622 "I/O Error in DMA TX interrupted\n");
623 dmaengine_terminate_all(controller->dma_tx);
624 dmaengine_terminate_all(controller->dma_rx);
625 fsl_lpspi_reset(fsl_lpspi);
626 return -EINTR;
627 }
628
629 if (wait_for_completion_interruptible(&fsl_lpspi->dma_rx_completion) ||
630 fsl_lpspi->target_aborted) {
631 dev_dbg(fsl_lpspi->dev,
632 "I/O Error in DMA RX interrupted\n");
633 dmaengine_terminate_all(controller->dma_tx);
634 dmaengine_terminate_all(controller->dma_rx);
635 fsl_lpspi_reset(fsl_lpspi);
636 return -EINTR;
637 }
638 }
639
640 fsl_lpspi_reset(fsl_lpspi);
641
642 return 0;
643 }
644
fsl_lpspi_dma_exit(struct spi_controller * controller)645 static void fsl_lpspi_dma_exit(struct spi_controller *controller)
646 {
647 if (controller->dma_rx) {
648 dma_release_channel(controller->dma_rx);
649 controller->dma_rx = NULL;
650 }
651
652 if (controller->dma_tx) {
653 dma_release_channel(controller->dma_tx);
654 controller->dma_tx = NULL;
655 }
656 }
657
fsl_lpspi_dma_init(struct device * dev,struct fsl_lpspi_data * fsl_lpspi,struct spi_controller * controller)658 static int fsl_lpspi_dma_init(struct device *dev,
659 struct fsl_lpspi_data *fsl_lpspi,
660 struct spi_controller *controller)
661 {
662 int ret;
663
664 /* Prepare for TX DMA: */
665 controller->dma_tx = dma_request_chan(dev, "tx");
666 if (IS_ERR(controller->dma_tx)) {
667 ret = PTR_ERR(controller->dma_tx);
668 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
669 controller->dma_tx = NULL;
670 goto err;
671 }
672
673 /* Prepare for RX DMA: */
674 controller->dma_rx = dma_request_chan(dev, "rx");
675 if (IS_ERR(controller->dma_rx)) {
676 ret = PTR_ERR(controller->dma_rx);
677 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
678 controller->dma_rx = NULL;
679 goto err;
680 }
681
682 init_completion(&fsl_lpspi->dma_rx_completion);
683 init_completion(&fsl_lpspi->dma_tx_completion);
684 controller->can_dma = fsl_lpspi_can_dma;
685 controller->max_dma_len = FSL_LPSPI_MAX_EDMA_BYTES;
686
687 return 0;
688 err:
689 fsl_lpspi_dma_exit(controller);
690 return ret;
691 }
692
fsl_lpspi_pio_transfer(struct spi_controller * controller,struct spi_transfer * t)693 static int fsl_lpspi_pio_transfer(struct spi_controller *controller,
694 struct spi_transfer *t)
695 {
696 struct fsl_lpspi_data *fsl_lpspi =
697 spi_controller_get_devdata(controller);
698 int ret;
699
700 fsl_lpspi->tx_buf = t->tx_buf;
701 fsl_lpspi->rx_buf = t->rx_buf;
702 fsl_lpspi->remain = t->len;
703
704 reinit_completion(&fsl_lpspi->xfer_done);
705 fsl_lpspi->target_aborted = false;
706
707 fsl_lpspi_write_tx_fifo(fsl_lpspi);
708
709 ret = fsl_lpspi_wait_for_completion(controller);
710 if (ret)
711 return ret;
712
713 fsl_lpspi_reset(fsl_lpspi);
714
715 return 0;
716 }
717
fsl_lpspi_transfer_one(struct spi_controller * controller,struct spi_device * spi,struct spi_transfer * t)718 static int fsl_lpspi_transfer_one(struct spi_controller *controller,
719 struct spi_device *spi,
720 struct spi_transfer *t)
721 {
722 struct fsl_lpspi_data *fsl_lpspi =
723 spi_controller_get_devdata(controller);
724 int ret;
725
726 fsl_lpspi->is_first_byte = true;
727 ret = fsl_lpspi_setup_transfer(controller, spi, t);
728 if (ret < 0)
729 return ret;
730
731 fsl_lpspi_set_cmd(fsl_lpspi);
732 fsl_lpspi->is_first_byte = false;
733
734 if (fsl_lpspi->usedma)
735 ret = fsl_lpspi_dma_transfer(controller, fsl_lpspi, t);
736 else
737 ret = fsl_lpspi_pio_transfer(controller, t);
738 if (ret < 0)
739 return ret;
740
741 return 0;
742 }
743
fsl_lpspi_isr(int irq,void * dev_id)744 static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id)
745 {
746 u32 temp_SR, temp_IER;
747 struct fsl_lpspi_data *fsl_lpspi = dev_id;
748
749 temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER);
750 fsl_lpspi_intctrl(fsl_lpspi, 0);
751 temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR);
752
753 fsl_lpspi_read_rx_fifo(fsl_lpspi);
754
755 if ((temp_SR & SR_TDF) && (temp_IER & IER_TDIE)) {
756 fsl_lpspi_write_tx_fifo(fsl_lpspi);
757 return IRQ_HANDLED;
758 }
759
760 if (temp_SR & SR_MBF ||
761 readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_TXCOUNT) {
762 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
763 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
764 return IRQ_HANDLED;
765 }
766
767 if (temp_SR & SR_FCF && (temp_IER & IER_FCIE)) {
768 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
769 complete(&fsl_lpspi->xfer_done);
770 return IRQ_HANDLED;
771 }
772
773 return IRQ_NONE;
774 }
775
776 #ifdef CONFIG_PM
fsl_lpspi_runtime_resume(struct device * dev)777 static int fsl_lpspi_runtime_resume(struct device *dev)
778 {
779 struct spi_controller *controller = dev_get_drvdata(dev);
780 struct fsl_lpspi_data *fsl_lpspi;
781 int ret;
782
783 fsl_lpspi = spi_controller_get_devdata(controller);
784
785 ret = clk_prepare_enable(fsl_lpspi->clk_per);
786 if (ret)
787 return ret;
788
789 ret = clk_prepare_enable(fsl_lpspi->clk_ipg);
790 if (ret) {
791 clk_disable_unprepare(fsl_lpspi->clk_per);
792 return ret;
793 }
794
795 return 0;
796 }
797
fsl_lpspi_runtime_suspend(struct device * dev)798 static int fsl_lpspi_runtime_suspend(struct device *dev)
799 {
800 struct spi_controller *controller = dev_get_drvdata(dev);
801 struct fsl_lpspi_data *fsl_lpspi;
802
803 fsl_lpspi = spi_controller_get_devdata(controller);
804
805 clk_disable_unprepare(fsl_lpspi->clk_per);
806 clk_disable_unprepare(fsl_lpspi->clk_ipg);
807
808 return 0;
809 }
810 #endif
811
fsl_lpspi_init_rpm(struct fsl_lpspi_data * fsl_lpspi)812 static int fsl_lpspi_init_rpm(struct fsl_lpspi_data *fsl_lpspi)
813 {
814 struct device *dev = fsl_lpspi->dev;
815
816 pm_runtime_enable(dev);
817 pm_runtime_set_autosuspend_delay(dev, FSL_LPSPI_RPM_TIMEOUT);
818 pm_runtime_use_autosuspend(dev);
819
820 return 0;
821 }
822
fsl_lpspi_probe(struct platform_device * pdev)823 static int fsl_lpspi_probe(struct platform_device *pdev)
824 {
825 struct fsl_lpspi_data *fsl_lpspi;
826 struct spi_controller *controller;
827 struct resource *res;
828 int ret, irq;
829 u32 num_cs;
830 u32 temp;
831 bool is_target;
832
833 is_target = of_property_read_bool((&pdev->dev)->of_node, "spi-slave");
834 if (is_target)
835 controller = devm_spi_alloc_target(&pdev->dev,
836 sizeof(struct fsl_lpspi_data));
837 else
838 controller = devm_spi_alloc_host(&pdev->dev,
839 sizeof(struct fsl_lpspi_data));
840
841 if (!controller)
842 return -ENOMEM;
843
844 platform_set_drvdata(pdev, controller);
845
846 fsl_lpspi = spi_controller_get_devdata(controller);
847 fsl_lpspi->dev = &pdev->dev;
848 fsl_lpspi->is_target = is_target;
849 fsl_lpspi->is_only_cs1 = of_property_read_bool((&pdev->dev)->of_node,
850 "fsl,spi-only-use-cs1-sel");
851
852 init_completion(&fsl_lpspi->xfer_done);
853
854 fsl_lpspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
855 if (IS_ERR(fsl_lpspi->base)) {
856 ret = PTR_ERR(fsl_lpspi->base);
857 goto out_controller_put;
858 }
859 fsl_lpspi->base_phys = res->start;
860
861 irq = platform_get_irq(pdev, 0);
862 if (irq < 0) {
863 ret = irq;
864 goto out_controller_put;
865 }
866
867 ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, 0,
868 dev_name(&pdev->dev), fsl_lpspi);
869 if (ret) {
870 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
871 goto out_controller_put;
872 }
873
874 fsl_lpspi->clk_per = devm_clk_get(&pdev->dev, "per");
875 if (IS_ERR(fsl_lpspi->clk_per)) {
876 ret = PTR_ERR(fsl_lpspi->clk_per);
877 goto out_controller_put;
878 }
879
880 fsl_lpspi->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
881 if (IS_ERR(fsl_lpspi->clk_ipg)) {
882 ret = PTR_ERR(fsl_lpspi->clk_ipg);
883 goto out_controller_put;
884 }
885
886 /* enable the clock */
887 ret = fsl_lpspi_init_rpm(fsl_lpspi);
888 if (ret)
889 goto out_controller_put;
890
891 ret = pm_runtime_get_sync(fsl_lpspi->dev);
892 if (ret < 0) {
893 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
894 goto out_pm_get;
895 }
896
897 temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);
898 fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
899 fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
900 if (of_property_read_u32((&pdev->dev)->of_node, "num-cs",
901 &num_cs)) {
902 if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx93-spi"))
903 num_cs = ((temp >> 16) & 0xf);
904 else
905 num_cs = 1;
906 }
907
908 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
909 controller->transfer_one = fsl_lpspi_transfer_one;
910 controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware;
911 controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware;
912 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
913 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
914 controller->dev.of_node = pdev->dev.of_node;
915 controller->bus_num = pdev->id;
916 controller->num_chipselect = num_cs;
917 controller->target_abort = fsl_lpspi_target_abort;
918 if (!fsl_lpspi->is_target)
919 controller->use_gpio_descriptors = true;
920
921 ret = fsl_lpspi_dma_init(&pdev->dev, fsl_lpspi, controller);
922 if (ret == -EPROBE_DEFER)
923 goto out_pm_get;
924 if (ret < 0)
925 dev_warn(&pdev->dev, "dma setup error %d, use pio\n", ret);
926 else
927 /*
928 * disable LPSPI module IRQ when enable DMA mode successfully,
929 * to prevent the unexpected LPSPI module IRQ events.
930 */
931 disable_irq(irq);
932
933 ret = devm_spi_register_controller(&pdev->dev, controller);
934 if (ret < 0) {
935 dev_err_probe(&pdev->dev, ret, "spi_register_controller error\n");
936 goto free_dma;
937 }
938
939 pm_runtime_mark_last_busy(fsl_lpspi->dev);
940 pm_runtime_put_autosuspend(fsl_lpspi->dev);
941
942 return 0;
943
944 free_dma:
945 fsl_lpspi_dma_exit(controller);
946 out_pm_get:
947 pm_runtime_dont_use_autosuspend(fsl_lpspi->dev);
948 pm_runtime_put_sync(fsl_lpspi->dev);
949 pm_runtime_disable(fsl_lpspi->dev);
950 out_controller_put:
951 spi_controller_put(controller);
952
953 return ret;
954 }
955
fsl_lpspi_remove(struct platform_device * pdev)956 static void fsl_lpspi_remove(struct platform_device *pdev)
957 {
958 struct spi_controller *controller = platform_get_drvdata(pdev);
959 struct fsl_lpspi_data *fsl_lpspi =
960 spi_controller_get_devdata(controller);
961
962 fsl_lpspi_dma_exit(controller);
963
964 pm_runtime_disable(fsl_lpspi->dev);
965 }
966
fsl_lpspi_suspend(struct device * dev)967 static int __maybe_unused fsl_lpspi_suspend(struct device *dev)
968 {
969 pinctrl_pm_select_sleep_state(dev);
970 return pm_runtime_force_suspend(dev);
971 }
972
fsl_lpspi_resume(struct device * dev)973 static int __maybe_unused fsl_lpspi_resume(struct device *dev)
974 {
975 int ret;
976
977 ret = pm_runtime_force_resume(dev);
978 if (ret) {
979 dev_err(dev, "Error in resume: %d\n", ret);
980 return ret;
981 }
982
983 pinctrl_pm_select_default_state(dev);
984
985 return 0;
986 }
987
988 static const struct dev_pm_ops fsl_lpspi_pm_ops = {
989 SET_RUNTIME_PM_OPS(fsl_lpspi_runtime_suspend,
990 fsl_lpspi_runtime_resume, NULL)
991 SET_SYSTEM_SLEEP_PM_OPS(fsl_lpspi_suspend, fsl_lpspi_resume)
992 };
993
994 static struct platform_driver fsl_lpspi_driver = {
995 .driver = {
996 .name = DRIVER_NAME,
997 .of_match_table = fsl_lpspi_dt_ids,
998 .pm = &fsl_lpspi_pm_ops,
999 },
1000 .probe = fsl_lpspi_probe,
1001 .remove_new = fsl_lpspi_remove,
1002 };
1003 module_platform_driver(fsl_lpspi_driver);
1004
1005 MODULE_DESCRIPTION("LPSPI Controller driver");
1006 MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>");
1007 MODULE_LICENSE("GPL");
1008