1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * cbe_regs.h
4  *
5  * This file is intended to hold the various register definitions for CBE
6  * on-chip system devices (memory controller, IO controller, etc...)
7  *
8  * (C) Copyright IBM Corporation 2001,2006
9  *
10  * Authors: Maximino Aguilar (maguilar@us.ibm.com)
11  *          David J. Erb (djerb@us.ibm.com)
12  *
13  * (c) 2006 Benjamin Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
14  */
15 
16 #ifndef CBE_REGS_H
17 #define CBE_REGS_H
18 
19 #include <asm/cell-pmu.h>
20 
21 /*
22  *
23  * Some HID register definitions
24  *
25  */
26 
27 /* CBE specific HID0 bits */
28 #define HID0_CBE_THERM_WAKEUP	0x0000020000000000ul
29 #define HID0_CBE_SYSERR_WAKEUP	0x0000008000000000ul
30 #define HID0_CBE_THERM_INT_EN	0x0000000400000000ul
31 #define HID0_CBE_SYSERR_INT_EN	0x0000000200000000ul
32 
33 #define MAX_CBE		2
34 
35 /*
36  *
37  * Pervasive unit register definitions
38  *
39  */
40 
41 union spe_reg {
42 	u64 val;
43 	u8 spe[8];
44 };
45 
46 union ppe_spe_reg {
47 	u64 val;
48 	struct {
49 		u32 ppe;
50 		u32 spe;
51 	};
52 };
53 
54 
55 struct cbe_pmd_regs {
56 	/* Debug Bus Control */
57 	u64	pad_0x0000;					/* 0x0000 */
58 
59 	u64	group_control;					/* 0x0008 */
60 
61 	u8	pad_0x0010_0x00a8 [0x00a8 - 0x0010];		/* 0x0010 */
62 
63 	u64	debug_bus_control;				/* 0x00a8 */
64 
65 	u8	pad_0x00b0_0x0100 [0x0100 - 0x00b0];		/* 0x00b0 */
66 
67 	u64	trace_aux_data;					/* 0x0100 */
68 	u64	trace_buffer_0_63;				/* 0x0108 */
69 	u64	trace_buffer_64_127;				/* 0x0110 */
70 	u64	trace_address;					/* 0x0118 */
71 	u64	ext_tr_timer;					/* 0x0120 */
72 
73 	u8	pad_0x0128_0x0400 [0x0400 - 0x0128];		/* 0x0128 */
74 
75 	/* Performance Monitor */
76 	u64	pm_status;					/* 0x0400 */
77 	u64	pm_control;					/* 0x0408 */
78 	u64	pm_interval;					/* 0x0410 */
79 	u64	pm_ctr[4];					/* 0x0418 */
80 	u64	pm_start_stop;					/* 0x0438 */
81 	u64	pm07_control[8];				/* 0x0440 */
82 
83 	u8	pad_0x0480_0x0800 [0x0800 - 0x0480];		/* 0x0480 */
84 
85 	/* Thermal Sensor Registers */
86 	union	spe_reg	ts_ctsr1;				/* 0x0800 */
87 	u64	ts_ctsr2;					/* 0x0808 */
88 	union	spe_reg	ts_mtsr1;				/* 0x0810 */
89 	u64	ts_mtsr2;					/* 0x0818 */
90 	union	spe_reg	ts_itr1;				/* 0x0820 */
91 	u64	ts_itr2;					/* 0x0828 */
92 	u64	ts_gitr;					/* 0x0830 */
93 	u64	ts_isr;						/* 0x0838 */
94 	u64	ts_imr;						/* 0x0840 */
95 	union	spe_reg	tm_cr1;					/* 0x0848 */
96 	u64	tm_cr2;						/* 0x0850 */
97 	u64	tm_simr;					/* 0x0858 */
98 	union	ppe_spe_reg tm_tpr;				/* 0x0860 */
99 	union	spe_reg	tm_str1;				/* 0x0868 */
100 	u64	tm_str2;					/* 0x0870 */
101 	union	ppe_spe_reg tm_tsr;				/* 0x0878 */
102 
103 	/* Power Management */
104 	u64	pmcr;						/* 0x0880 */
105 #define CBE_PMD_PAUSE_ZERO_CONTROL	0x10000
106 	u64	pmsr;						/* 0x0888 */
107 
108 	/* Time Base Register */
109 	u64	tbr;						/* 0x0890 */
110 
111 	u8	pad_0x0898_0x0c00 [0x0c00 - 0x0898];		/* 0x0898 */
112 
113 	/* Fault Isolation Registers */
114 	u64	checkstop_fir;					/* 0x0c00 */
115 	u64	recoverable_fir;				/* 0x0c08 */
116 	u64	spec_att_mchk_fir;				/* 0x0c10 */
117 	u32	fir_mode_reg;					/* 0x0c18 */
118 	u8	pad_0x0c1c_0x0c20 [4];				/* 0x0c1c */
119 #define CBE_PMD_FIR_MODE_M8		0x00800
120 	u64	fir_enable_mask;				/* 0x0c20 */
121 
122 	u8	pad_0x0c28_0x0ca8 [0x0ca8 - 0x0c28];		/* 0x0c28 */
123 	u64	ras_esc_0;					/* 0x0ca8 */
124 	u8	pad_0x0cb0_0x1000 [0x1000 - 0x0cb0];		/* 0x0cb0 */
125 };
126 
127 extern struct cbe_pmd_regs __iomem *cbe_get_pmd_regs(struct device_node *np);
128 extern struct cbe_pmd_regs __iomem *cbe_get_cpu_pmd_regs(int cpu);
129 
130 /*
131  * PMU shadow registers
132  *
133  * Many of the registers in the performance monitoring unit are write-only,
134  * so we need to save a copy of what we write to those registers.
135  *
136  * The actual data counters are read/write. However, writing to the counters
137  * only takes effect if the PMU is enabled. Otherwise the value is stored in
138  * a hardware latch until the next time the PMU is enabled. So we save a copy
139  * of the counter values if we need to read them back while the PMU is
140  * disabled. The counter_value_in_latch field is a bitmap indicating which
141  * counters currently have a value waiting to be written.
142  */
143 
144 struct cbe_pmd_shadow_regs {
145 	u32 group_control;
146 	u32 debug_bus_control;
147 	u32 trace_address;
148 	u32 ext_tr_timer;
149 	u32 pm_status;
150 	u32 pm_control;
151 	u32 pm_interval;
152 	u32 pm_start_stop;
153 	u32 pm07_control[NR_CTRS];
154 
155 	u32 pm_ctr[NR_PHYS_CTRS];
156 	u32 counter_value_in_latch;
157 };
158 
159 extern struct cbe_pmd_shadow_regs *cbe_get_pmd_shadow_regs(struct device_node *np);
160 extern struct cbe_pmd_shadow_regs *cbe_get_cpu_pmd_shadow_regs(int cpu);
161 
162 /*
163  *
164  * IIC unit register definitions
165  *
166  */
167 
168 struct cbe_iic_pending_bits {
169 	u32 data;
170 	u8 flags;
171 	u8 class;
172 	u8 source;
173 	u8 prio;
174 };
175 
176 #define CBE_IIC_IRQ_VALID	0x80
177 #define CBE_IIC_IRQ_IPI		0x40
178 
179 struct cbe_iic_thread_regs {
180 	struct cbe_iic_pending_bits pending;
181 	struct cbe_iic_pending_bits pending_destr;
182 	u64 generate;
183 	u64 prio;
184 };
185 
186 struct cbe_iic_regs {
187 	u8	pad_0x0000_0x0400[0x0400 - 0x0000];		/* 0x0000 */
188 
189 	/* IIC interrupt registers */
190 	struct	cbe_iic_thread_regs thread[2];			/* 0x0400 */
191 
192 	u64	iic_ir;						/* 0x0440 */
193 #define CBE_IIC_IR_PRIO(x)      (((x) & 0xf) << 12)
194 #define CBE_IIC_IR_DEST_NODE(x) (((x) & 0xf) << 4)
195 #define CBE_IIC_IR_DEST_UNIT(x) ((x) & 0xf)
196 #define CBE_IIC_IR_IOC_0        0x0
197 #define CBE_IIC_IR_IOC_1S       0xb
198 #define CBE_IIC_IR_PT_0         0xe
199 #define CBE_IIC_IR_PT_1         0xf
200 
201 	u64	iic_is;						/* 0x0448 */
202 #define CBE_IIC_IS_PMI		0x2
203 
204 	u8	pad_0x0450_0x0500[0x0500 - 0x0450];		/* 0x0450 */
205 
206 	/* IOC FIR */
207 	u64	ioc_fir_reset;					/* 0x0500 */
208 	u64	ioc_fir_set;					/* 0x0508 */
209 	u64	ioc_checkstop_enable;				/* 0x0510 */
210 	u64	ioc_fir_error_mask;				/* 0x0518 */
211 	u64	ioc_syserr_enable;				/* 0x0520 */
212 	u64	ioc_fir;					/* 0x0528 */
213 
214 	u8	pad_0x0530_0x1000[0x1000 - 0x0530];		/* 0x0530 */
215 };
216 
217 extern struct cbe_iic_regs __iomem *cbe_get_iic_regs(struct device_node *np);
218 extern struct cbe_iic_regs __iomem *cbe_get_cpu_iic_regs(int cpu);
219 
220 
221 struct cbe_mic_tm_regs {
222 	u8	pad_0x0000_0x0040[0x0040 - 0x0000];		/* 0x0000 */
223 
224 	u64	mic_ctl_cnfg2;					/* 0x0040 */
225 #define CBE_MIC_ENABLE_AUX_TRC		0x8000000000000000LL
226 #define CBE_MIC_DISABLE_PWR_SAV_2	0x0200000000000000LL
227 #define CBE_MIC_DISABLE_AUX_TRC_WRAP	0x0100000000000000LL
228 #define CBE_MIC_ENABLE_AUX_TRC_INT	0x0080000000000000LL
229 
230 	u64	pad_0x0048;					/* 0x0048 */
231 
232 	u64	mic_aux_trc_base;				/* 0x0050 */
233 	u64	mic_aux_trc_max_addr;				/* 0x0058 */
234 	u64	mic_aux_trc_cur_addr;				/* 0x0060 */
235 	u64	mic_aux_trc_grf_addr;				/* 0x0068 */
236 	u64	mic_aux_trc_grf_data;				/* 0x0070 */
237 
238 	u64	pad_0x0078;					/* 0x0078 */
239 
240 	u64	mic_ctl_cnfg_0;					/* 0x0080 */
241 #define CBE_MIC_DISABLE_PWR_SAV_0	0x8000000000000000LL
242 
243 	u64	pad_0x0088;					/* 0x0088 */
244 
245 	u64	slow_fast_timer_0;				/* 0x0090 */
246 	u64	slow_next_timer_0;				/* 0x0098 */
247 
248 	u8	pad_0x00a0_0x00f8[0x00f8 - 0x00a0];		/* 0x00a0 */
249 	u64    	mic_df_ecc_address_0;				/* 0x00f8 */
250 
251 	u8	pad_0x0100_0x01b8[0x01b8 - 0x0100];		/* 0x0100 */
252 	u64    	mic_df_ecc_address_1;				/* 0x01b8 */
253 
254 	u64	mic_ctl_cnfg_1;					/* 0x01c0 */
255 #define CBE_MIC_DISABLE_PWR_SAV_1	0x8000000000000000LL
256 
257 	u64	pad_0x01c8;					/* 0x01c8 */
258 
259 	u64	slow_fast_timer_1;				/* 0x01d0 */
260 	u64	slow_next_timer_1;				/* 0x01d8 */
261 
262 	u8	pad_0x01e0_0x0208[0x0208 - 0x01e0];		/* 0x01e0 */
263 	u64	mic_exc;					/* 0x0208 */
264 #define CBE_MIC_EXC_BLOCK_SCRUB		0x0800000000000000ULL
265 #define CBE_MIC_EXC_FAST_SCRUB		0x0100000000000000ULL
266 
267 	u64	mic_mnt_cfg;					/* 0x0210 */
268 #define CBE_MIC_MNT_CFG_CHAN_0_POP	0x0002000000000000ULL
269 #define CBE_MIC_MNT_CFG_CHAN_1_POP	0x0004000000000000ULL
270 
271 	u64	mic_df_config;					/* 0x0218 */
272 #define CBE_MIC_ECC_DISABLE_0		0x4000000000000000ULL
273 #define CBE_MIC_ECC_REP_SINGLE_0	0x2000000000000000ULL
274 #define CBE_MIC_ECC_DISABLE_1		0x0080000000000000ULL
275 #define CBE_MIC_ECC_REP_SINGLE_1	0x0040000000000000ULL
276 
277 	u8	pad_0x0220_0x0230[0x0230 - 0x0220];		/* 0x0220 */
278 	u64	mic_fir;					/* 0x0230 */
279 #define CBE_MIC_FIR_ECC_SINGLE_0_ERR	0x0200000000000000ULL
280 #define CBE_MIC_FIR_ECC_MULTI_0_ERR	0x0100000000000000ULL
281 #define CBE_MIC_FIR_ECC_SINGLE_1_ERR	0x0080000000000000ULL
282 #define CBE_MIC_FIR_ECC_MULTI_1_ERR	0x0040000000000000ULL
283 #define CBE_MIC_FIR_ECC_ERR_MASK	0xffff000000000000ULL
284 #define CBE_MIC_FIR_ECC_SINGLE_0_CTE	0x0000020000000000ULL
285 #define CBE_MIC_FIR_ECC_MULTI_0_CTE	0x0000010000000000ULL
286 #define CBE_MIC_FIR_ECC_SINGLE_1_CTE	0x0000008000000000ULL
287 #define CBE_MIC_FIR_ECC_MULTI_1_CTE	0x0000004000000000ULL
288 #define CBE_MIC_FIR_ECC_CTE_MASK	0x0000ffff00000000ULL
289 #define CBE_MIC_FIR_ECC_SINGLE_0_RESET	0x0000000002000000ULL
290 #define CBE_MIC_FIR_ECC_MULTI_0_RESET	0x0000000001000000ULL
291 #define CBE_MIC_FIR_ECC_SINGLE_1_RESET	0x0000000000800000ULL
292 #define CBE_MIC_FIR_ECC_MULTI_1_RESET	0x0000000000400000ULL
293 #define CBE_MIC_FIR_ECC_RESET_MASK	0x00000000ffff0000ULL
294 #define CBE_MIC_FIR_ECC_SINGLE_0_SET	0x0000000000000200ULL
295 #define CBE_MIC_FIR_ECC_MULTI_0_SET	0x0000000000000100ULL
296 #define CBE_MIC_FIR_ECC_SINGLE_1_SET	0x0000000000000080ULL
297 #define CBE_MIC_FIR_ECC_MULTI_1_SET	0x0000000000000040ULL
298 #define CBE_MIC_FIR_ECC_SET_MASK	0x000000000000ffffULL
299 	u64	mic_fir_debug;					/* 0x0238 */
300 
301 	u8	pad_0x0240_0x1000[0x1000 - 0x0240];		/* 0x0240 */
302 };
303 
304 extern struct cbe_mic_tm_regs __iomem *cbe_get_mic_tm_regs(struct device_node *np);
305 extern struct cbe_mic_tm_regs __iomem *cbe_get_cpu_mic_tm_regs(int cpu);
306 
307 
308 /* Cell page table entries */
309 #define CBE_IOPTE_PP_W		0x8000000000000000ul /* protection: write */
310 #define CBE_IOPTE_PP_R		0x4000000000000000ul /* protection: read */
311 #define CBE_IOPTE_M		0x2000000000000000ul /* coherency required */
312 #define CBE_IOPTE_SO_R		0x1000000000000000ul /* ordering: writes */
313 #define CBE_IOPTE_SO_RW		0x1800000000000000ul /* ordering: r & w */
314 #define CBE_IOPTE_RPN_Mask	0x07fffffffffff000ul /* RPN */
315 #define CBE_IOPTE_H		0x0000000000000800ul /* cache hint */
316 #define CBE_IOPTE_IOID_Mask	0x00000000000007fful /* ioid */
317 
318 /* some utility functions to deal with SMT */
319 extern u32 cbe_get_hw_thread_id(int cpu);
320 extern u32 cbe_cpu_to_node(int cpu);
321 extern u32 cbe_node_to_cpu(int node);
322 
323 /* Init this module early */
324 extern void cbe_regs_init(void);
325 
326 
327 #endif /* CBE_REGS_H */
328