1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * TI CAL camera interface driver
4  *
5  * Copyright (c) 2015 Texas Instruments Inc.
6  *
7  * Benoit Parrot, <bparrot@ti.com>
8  */
9 
10 #ifndef __TI_CAL_REGS_H
11 #define __TI_CAL_REGS_H
12 
13 /*
14  * struct cal_dev.flags possibilities
15  *
16  * DRA72_CAL_PRE_ES2_LDO_DISABLE:
17  *   Errata i913: CSI2 LDO Needs to be disabled when module is powered on
18  *
19  *   Enabling CSI2 LDO shorts it to core supply. It is crucial the 2 CSI2
20  *   LDOs on the device are disabled if CSI-2 module is powered on
21  *   (0x4845 B304 | 0x4845 B384 [28:27] = 0x1) or in ULPS (0x4845 B304
22  *   | 0x4845 B384 [28:27] = 0x2) mode. Common concerns include: high
23  *   current draw on the module supply in active mode.
24  *
25  *   Errata does not apply when CSI-2 module is powered off
26  *   (0x4845 B304 | 0x4845 B384 [28:27] = 0x0).
27  *
28  * SW Workaround:
29  *	Set the following register bits to disable the LDO,
30  *	which is essentially CSI2 REG10 bit 6:
31  *
32  *		Core 0:  0x4845 B828 = 0x0000 0040
33  *		Core 1:  0x4845 B928 = 0x0000 0040
34  */
35 #define DRA72_CAL_PRE_ES2_LDO_DISABLE BIT(0)
36 
37 /* CAL register offsets */
38 
39 #define CAL_HL_REVISION			0x0000
40 #define CAL_HL_HWINFO			0x0004
41 #define CAL_HL_SYSCONFIG		0x0010
42 #define CAL_HL_IRQ_EOI			0x001c
43 #define CAL_HL_IRQSTATUS_RAW(m)		(0x20U + (m) * 0x10U)
44 #define CAL_HL_IRQSTATUS(m)		(0x24U + (m) * 0x10U)
45 #define CAL_HL_IRQENABLE_SET(m)		(0x28U + (m) * 0x10U)
46 #define CAL_HL_IRQENABLE_CLR(m)		(0x2cU + (m) * 0x10U)
47 #define CAL_PIX_PROC(m)			(0xc0U + (m) * 0x4U)
48 #define CAL_CTRL			0x100
49 #define CAL_CTRL1			0x104
50 #define CAL_LINE_NUMBER_EVT		0x108
51 #define CAL_VPORT_CTRL1			0x120
52 #define CAL_VPORT_CTRL2			0x124
53 #define CAL_BYS_CTRL1			0x130
54 #define CAL_BYS_CTRL2			0x134
55 #define CAL_RD_DMA_CTRL			0x140
56 #define CAL_RD_DMA_PIX_ADDR		0x144
57 #define CAL_RD_DMA_PIX_OFST		0x148
58 #define CAL_RD_DMA_XSIZE		0x14c
59 #define CAL_RD_DMA_YSIZE		0x150
60 #define CAL_RD_DMA_INIT_ADDR		0x154
61 #define CAL_RD_DMA_INIT_OFST		0x168
62 #define CAL_RD_DMA_CTRL2		0x16c
63 #define CAL_WR_DMA_CTRL(m)		(0x200U + (m) * 0x10U)
64 #define CAL_WR_DMA_ADDR(m)		(0x204U + (m) * 0x10U)
65 #define CAL_WR_DMA_OFST(m)		(0x208U + (m) * 0x10U)
66 #define CAL_WR_DMA_XSIZE(m)		(0x20cU + (m) * 0x10U)
67 #define CAL_CSI2_PPI_CTRL(m)		(0x300U + (m) * 0x80U)
68 #define CAL_CSI2_COMPLEXIO_CFG(m)	(0x304U + (m) * 0x80U)
69 #define CAL_CSI2_COMPLEXIO_IRQSTATUS(m)	(0x308U + (m) * 0x80U)
70 #define CAL_CSI2_SHORT_PACKET(m)	(0x30cU + (m) * 0x80U)
71 #define CAL_CSI2_COMPLEXIO_IRQENABLE(m)	(0x310U + (m) * 0x80U)
72 #define CAL_CSI2_TIMING(m)		(0x314U + (m) * 0x80U)
73 #define CAL_CSI2_VC_IRQENABLE(m)	(0x318U + (m) * 0x80U)
74 #define CAL_CSI2_VC_IRQSTATUS(m)	(0x328U + (m) * 0x80U)
75 #define CAL_CSI2_CTX(phy, csi2_ctx)	(0x330U + (phy) * 0x80U + (csi2_ctx) * 4)
76 #define CAL_CSI2_STATUS(phy, csi2_ctx)	(0x350U + (phy) * 0x80U + (csi2_ctx) * 4)
77 
78 /* CAL CSI2 PHY register offsets */
79 #define CAL_CSI2_PHY_REG0		0x000
80 #define CAL_CSI2_PHY_REG1		0x004
81 #define CAL_CSI2_PHY_REG2		0x008
82 #define CAL_CSI2_PHY_REG10		0x028
83 
84 /* CAL Control Module Core Camerrx Control register offsets */
85 #define CM_CTRL_CORE_CAMERRX_CONTROL	0x000
86 
87 /*********************************************************************
88 * Field Definition Macros
89 *********************************************************************/
90 
91 #define CAL_HL_REVISION_MINOR_MASK		GENMASK(5, 0)
92 #define CAL_HL_REVISION_CUSTOM_MASK		GENMASK(7, 6)
93 #define CAL_HL_REVISION_MAJOR_MASK		GENMASK(10, 8)
94 #define CAL_HL_REVISION_RTL_MASK		GENMASK(15, 11)
95 #define CAL_HL_REVISION_FUNC_MASK		GENMASK(27, 16)
96 #define CAL_HL_REVISION_SCHEME_MASK		GENMASK(31, 30)
97 #define CAL_HL_REVISION_SCHEME_H08			1
98 #define CAL_HL_REVISION_SCHEME_LEGACY			0
99 
100 #define CAL_HL_HWINFO_WFIFO_MASK		GENMASK(3, 0)
101 #define CAL_HL_HWINFO_RFIFO_MASK		GENMASK(7, 4)
102 #define CAL_HL_HWINFO_PCTX_MASK			GENMASK(12, 8)
103 #define CAL_HL_HWINFO_WCTX_MASK			GENMASK(18, 13)
104 #define CAL_HL_HWINFO_VFIFO_MASK		GENMASK(22, 19)
105 #define CAL_HL_HWINFO_NCPORT_MASK		GENMASK(27, 23)
106 #define CAL_HL_HWINFO_NPPI_CTXS0_MASK		GENMASK(29, 28)
107 #define CAL_HL_HWINFO_NPPI_CTXS1_MASK		GENMASK(31, 30)
108 #define CAL_HL_HWINFO_NPPI_CONTEXTS_ZERO		0
109 #define CAL_HL_HWINFO_NPPI_CONTEXTS_FOUR		1
110 #define CAL_HL_HWINFO_NPPI_CONTEXTS_EIGHT		2
111 #define CAL_HL_HWINFO_NPPI_CONTEXTS_RESERVED		3
112 
113 #define CAL_HL_SYSCONFIG_SOFTRESET_MASK		BIT(0)
114 #define CAL_HL_SYSCONFIG_SOFTRESET_DONE			0x0
115 #define CAL_HL_SYSCONFIG_SOFTRESET_PENDING		0x1
116 #define CAL_HL_SYSCONFIG_SOFTRESET_NOACTION		0x0
117 #define CAL_HL_SYSCONFIG_SOFTRESET_RESET		0x1
118 #define CAL_HL_SYSCONFIG_IDLE_MASK		GENMASK(3, 2)
119 #define CAL_HL_SYSCONFIG_IDLEMODE_FORCE			0
120 #define CAL_HL_SYSCONFIG_IDLEMODE_NO			1
121 #define CAL_HL_SYSCONFIG_IDLEMODE_SMART1		2
122 #define CAL_HL_SYSCONFIG_IDLEMODE_SMART2		3
123 
124 #define CAL_HL_IRQ_EOI_LINE_NUMBER_MASK		BIT(0)
125 #define CAL_HL_IRQ_EOI_LINE_NUMBER_READ0		0
126 #define CAL_HL_IRQ_EOI_LINE_NUMBER_EOI0			0
127 
128 #define CAL_HL_IRQ_WDMA_END_MASK(m)		BIT(m)
129 #define CAL_HL_IRQ_WDMA_START_MASK(m)		BIT(m)
130 
131 #define CAL_HL_IRQ_OCPO_ERR_MASK		BIT(6)
132 
133 #define CAL_HL_IRQ_CIO_MASK(i)			BIT(16 + (i) * 8)
134 #define CAL_HL_IRQ_VC_MASK(i)			BIT(17 + (i) * 8)
135 
136 #define CAL_PIX_PROC_EN_MASK			BIT(0)
137 #define CAL_PIX_PROC_EXTRACT_MASK		GENMASK(4, 1)
138 #define CAL_PIX_PROC_EXTRACT_B6				0x0
139 #define CAL_PIX_PROC_EXTRACT_B7				0x1
140 #define CAL_PIX_PROC_EXTRACT_B8				0x2
141 #define CAL_PIX_PROC_EXTRACT_B10			0x3
142 #define CAL_PIX_PROC_EXTRACT_B10_MIPI			0x4
143 #define CAL_PIX_PROC_EXTRACT_B12			0x5
144 #define CAL_PIX_PROC_EXTRACT_B12_MIPI			0x6
145 #define CAL_PIX_PROC_EXTRACT_B14			0x7
146 #define CAL_PIX_PROC_EXTRACT_B14_MIPI			0x8
147 #define CAL_PIX_PROC_EXTRACT_B16_BE			0x9
148 #define CAL_PIX_PROC_EXTRACT_B16_LE			0xa
149 #define CAL_PIX_PROC_DPCMD_MASK			GENMASK(9, 5)
150 #define CAL_PIX_PROC_DPCMD_BYPASS			0x0
151 #define CAL_PIX_PROC_DPCMD_DPCM_10_8_1			0x2
152 #define CAL_PIX_PROC_DPCMD_DPCM_12_8_1			0x8
153 #define CAL_PIX_PROC_DPCMD_DPCM_10_7_1			0x4
154 #define CAL_PIX_PROC_DPCMD_DPCM_10_7_2			0x5
155 #define CAL_PIX_PROC_DPCMD_DPCM_10_6_1			0x6
156 #define CAL_PIX_PROC_DPCMD_DPCM_10_6_2			0x7
157 #define CAL_PIX_PROC_DPCMD_DPCM_12_7_1			0xa
158 #define CAL_PIX_PROC_DPCMD_DPCM_12_6_1			0xc
159 #define CAL_PIX_PROC_DPCMD_DPCM_14_10			0xe
160 #define CAL_PIX_PROC_DPCMD_DPCM_14_8_1			0x10
161 #define CAL_PIX_PROC_DPCMD_DPCM_16_12_1			0x12
162 #define CAL_PIX_PROC_DPCMD_DPCM_16_10_1			0x14
163 #define CAL_PIX_PROC_DPCMD_DPCM_16_8_1			0x16
164 #define CAL_PIX_PROC_DPCME_MASK			GENMASK(15, 11)
165 #define CAL_PIX_PROC_DPCME_BYPASS			0x0
166 #define CAL_PIX_PROC_DPCME_DPCM_10_8_1			0x2
167 #define CAL_PIX_PROC_DPCME_DPCM_12_8_1			0x8
168 #define CAL_PIX_PROC_DPCME_DPCM_14_10			0xe
169 #define CAL_PIX_PROC_DPCME_DPCM_14_8_1			0x10
170 #define CAL_PIX_PROC_DPCME_DPCM_16_12_1			0x12
171 #define CAL_PIX_PROC_DPCME_DPCM_16_10_1			0x14
172 #define CAL_PIX_PROC_DPCME_DPCM_16_8_1			0x16
173 #define CAL_PIX_PROC_PACK_MASK			GENMASK(18, 16)
174 #define CAL_PIX_PROC_PACK_B8				0x0
175 #define CAL_PIX_PROC_PACK_B10_MIPI			0x2
176 #define CAL_PIX_PROC_PACK_B12				0x3
177 #define CAL_PIX_PROC_PACK_B12_MIPI			0x4
178 #define CAL_PIX_PROC_PACK_B16				0x5
179 #define CAL_PIX_PROC_PACK_ARGB				0x6
180 #define CAL_PIX_PROC_CPORT_MASK			GENMASK(23, 19)
181 
182 #define CAL_CTRL_POSTED_WRITES_MASK		BIT(0)
183 #define CAL_CTRL_POSTED_WRITES_NONPOSTED		0
184 #define CAL_CTRL_POSTED_WRITES				1
185 #define CAL_CTRL_TAGCNT_MASK			GENMASK(4, 1)
186 #define CAL_CTRL_BURSTSIZE_MASK			GENMASK(6, 5)
187 #define CAL_CTRL_BURSTSIZE_BURST16			0x0
188 #define CAL_CTRL_BURSTSIZE_BURST32			0x1
189 #define CAL_CTRL_BURSTSIZE_BURST64			0x2
190 #define CAL_CTRL_BURSTSIZE_BURST128			0x3
191 #define CAL_CTRL_LL_FORCE_STATE_MASK		GENMASK(12, 7)
192 #define CAL_CTRL_MFLAGL_MASK			GENMASK(20, 13)
193 #define CAL_CTRL_PWRSCPCLK_MASK			BIT(21)
194 #define CAL_CTRL_PWRSCPCLK_AUTO				0
195 #define CAL_CTRL_PWRSCPCLK_FORCE			1
196 #define CAL_CTRL_RD_DMA_STALL_MASK		BIT(22)
197 #define CAL_CTRL_MFLAGH_MASK			GENMASK(31, 24)
198 
199 #define CAL_CTRL1_PPI_GROUPING_MASK		GENMASK(1, 0)
200 #define CAL_CTRL1_PPI_GROUPING_DISABLED			0
201 #define CAL_CTRL1_PPI_GROUPING_RESERVED			1
202 #define CAL_CTRL1_PPI_GROUPING_0			2
203 #define CAL_CTRL1_PPI_GROUPING_1			3
204 #define CAL_CTRL1_INTERLEAVE01_MASK		GENMASK(3, 2)
205 #define CAL_CTRL1_INTERLEAVE01_DISABLED			0
206 #define CAL_CTRL1_INTERLEAVE01_PIX1			1
207 #define CAL_CTRL1_INTERLEAVE01_PIX4			2
208 #define CAL_CTRL1_INTERLEAVE01_RESERVED			3
209 #define CAL_CTRL1_INTERLEAVE23_MASK		GENMASK(5, 4)
210 #define CAL_CTRL1_INTERLEAVE23_DISABLED			0
211 #define CAL_CTRL1_INTERLEAVE23_PIX1			1
212 #define CAL_CTRL1_INTERLEAVE23_PIX4			2
213 #define CAL_CTRL1_INTERLEAVE23_RESERVED			3
214 
215 #define CAL_LINE_NUMBER_EVT_CPORT_MASK		GENMASK(4, 0)
216 #define CAL_LINE_NUMBER_EVT_MASK		GENMASK(29, 16)
217 
218 #define CAL_VPORT_CTRL1_PCLK_MASK		GENMASK(16, 0)
219 #define CAL_VPORT_CTRL1_XBLK_MASK		GENMASK(24, 17)
220 #define CAL_VPORT_CTRL1_YBLK_MASK		GENMASK(30, 25)
221 #define CAL_VPORT_CTRL1_WIDTH_MASK		BIT(31)
222 #define CAL_VPORT_CTRL1_WIDTH_ONE			0
223 #define CAL_VPORT_CTRL1_WIDTH_TWO			1
224 
225 #define CAL_VPORT_CTRL2_CPORT_MASK		GENMASK(4, 0)
226 #define CAL_VPORT_CTRL2_FREERUNNING_MASK	BIT(15)
227 #define CAL_VPORT_CTRL2_FREERUNNING_GATED		0
228 #define CAL_VPORT_CTRL2_FREERUNNING_FREE		1
229 #define CAL_VPORT_CTRL2_FS_RESETS_MASK		BIT(16)
230 #define CAL_VPORT_CTRL2_FS_RESETS_NO			0
231 #define CAL_VPORT_CTRL2_FS_RESETS_YES			1
232 #define CAL_VPORT_CTRL2_FSM_RESET_MASK		BIT(17)
233 #define CAL_VPORT_CTRL2_FSM_RESET_NOEFFECT		0
234 #define CAL_VPORT_CTRL2_FSM_RESET			1
235 #define CAL_VPORT_CTRL2_RDY_THR_MASK		GENMASK(31, 18)
236 
237 #define CAL_BYS_CTRL1_PCLK_MASK			GENMASK(16, 0)
238 #define CAL_BYS_CTRL1_XBLK_MASK			GENMASK(24, 17)
239 #define CAL_BYS_CTRL1_YBLK_MASK			GENMASK(30, 25)
240 #define CAL_BYS_CTRL1_BYSINEN_MASK		BIT(31)
241 
242 #define CAL_BYS_CTRL2_CPORTIN_MASK		GENMASK(4, 0)
243 #define CAL_BYS_CTRL2_CPORTOUT_MASK		GENMASK(9, 5)
244 #define CAL_BYS_CTRL2_DUPLICATEDDATA_MASK	BIT(10)
245 #define CAL_BYS_CTRL2_DUPLICATEDDATA_NO			0
246 #define CAL_BYS_CTRL2_DUPLICATEDDATA_YES		1
247 #define CAL_BYS_CTRL2_FREERUNNING_MASK		BIT(11)
248 #define CAL_BYS_CTRL2_FREERUNNING_NO			0
249 #define CAL_BYS_CTRL2_FREERUNNING_YES			1
250 
251 #define CAL_RD_DMA_CTRL_GO_MASK			BIT(0)
252 #define CAL_RD_DMA_CTRL_GO_DIS				0
253 #define CAL_RD_DMA_CTRL_GO_EN				1
254 #define CAL_RD_DMA_CTRL_GO_IDLE				0
255 #define CAL_RD_DMA_CTRL_GO_BUSY				1
256 #define CAL_RD_DMA_CTRL_INIT_MASK		BIT(1)
257 #define CAL_RD_DMA_CTRL_BW_LIMITER_MASK		GENMASK(10, 2)
258 #define CAL_RD_DMA_CTRL_OCP_TAG_CNT_MASK	GENMASK(14, 11)
259 #define CAL_RD_DMA_CTRL_PCLK_MASK		GENMASK(31, 15)
260 
261 #define CAL_RD_DMA_PIX_ADDR_MASK		GENMASK(31, 3)
262 
263 #define CAL_RD_DMA_PIX_OFST_MASK		GENMASK(31, 4)
264 
265 #define CAL_RD_DMA_XSIZE_MASK			GENMASK(31, 19)
266 
267 #define CAL_RD_DMA_YSIZE_MASK			GENMASK(29, 16)
268 
269 #define CAL_RD_DMA_INIT_ADDR_MASK		GENMASK(31, 3)
270 
271 #define CAL_RD_DMA_INIT_OFST_MASK		GENMASK(31, 3)
272 
273 #define CAL_RD_DMA_CTRL2_CIRC_MODE_MASK		GENMASK(2, 0)
274 #define CAL_RD_DMA_CTRL2_CIRC_MODE_DIS			0
275 #define CAL_RD_DMA_CTRL2_CIRC_MODE_ONE			1
276 #define CAL_RD_DMA_CTRL2_CIRC_MODE_FOUR			2
277 #define CAL_RD_DMA_CTRL2_CIRC_MODE_SIXTEEN		3
278 #define CAL_RD_DMA_CTRL2_CIRC_MODE_SIXTYFOUR		4
279 #define CAL_RD_DMA_CTRL2_CIRC_MODE_RESERVED		5
280 #define CAL_RD_DMA_CTRL2_ICM_CSTART_MASK	BIT(3)
281 #define CAL_RD_DMA_CTRL2_PATTERN_MASK		GENMASK(5, 4)
282 #define CAL_RD_DMA_CTRL2_PATTERN_LINEAR			0
283 #define CAL_RD_DMA_CTRL2_PATTERN_YUV420			1
284 #define CAL_RD_DMA_CTRL2_PATTERN_RD2SKIP2		2
285 #define CAL_RD_DMA_CTRL2_PATTERN_RD2SKIP4		3
286 #define CAL_RD_DMA_CTRL2_BYSOUT_LE_WAIT_MASK	BIT(6)
287 #define CAL_RD_DMA_CTRL2_BYSOUT_LE_WAIT_FREERUNNING	0
288 #define CAL_RD_DMA_CTRL2_BYSOUT_LE_WAIT_WAITFORBYSOUT	1
289 #define CAL_RD_DMA_CTRL2_CIRC_SIZE_MASK		GENMASK(29, 16)
290 
291 #define CAL_WR_DMA_CTRL_MODE_MASK		GENMASK(2, 0)
292 #define CAL_WR_DMA_CTRL_MODE_DIS			0
293 #define CAL_WR_DMA_CTRL_MODE_SHD			1
294 #define CAL_WR_DMA_CTRL_MODE_CNT			2
295 #define CAL_WR_DMA_CTRL_MODE_CNT_INIT			3
296 #define CAL_WR_DMA_CTRL_MODE_CONST			4
297 #define CAL_WR_DMA_CTRL_MODE_RESERVED			5
298 #define CAL_WR_DMA_CTRL_PATTERN_MASK		GENMASK(4, 3)
299 #define CAL_WR_DMA_CTRL_PATTERN_LINEAR			0
300 #define CAL_WR_DMA_CTRL_PATTERN_WR2SKIP2		2
301 #define CAL_WR_DMA_CTRL_PATTERN_WR2SKIP4		3
302 #define CAL_WR_DMA_CTRL_PATTERN_RESERVED		1
303 #define CAL_WR_DMA_CTRL_ICM_PSTART_MASK		BIT(5)
304 #define CAL_WR_DMA_CTRL_DTAG_MASK		GENMASK(8, 6)
305 #define CAL_WR_DMA_CTRL_DTAG_ATT_HDR			0
306 #define CAL_WR_DMA_CTRL_DTAG_ATT_DAT			1
307 #define CAL_WR_DMA_CTRL_DTAG				2
308 #define CAL_WR_DMA_CTRL_DTAG_PIX_HDR			3
309 #define CAL_WR_DMA_CTRL_DTAG_PIX_DAT			4
310 #define CAL_WR_DMA_CTRL_DTAG_D5				5
311 #define CAL_WR_DMA_CTRL_DTAG_D6				6
312 #define CAL_WR_DMA_CTRL_DTAG_D7				7
313 #define CAL_WR_DMA_CTRL_CPORT_MASK		GENMASK(13, 9)
314 #define CAL_WR_DMA_CTRL_STALL_RD_MASK		BIT(14)
315 #define CAL_WR_DMA_CTRL_YSIZE_MASK		GENMASK(31, 18)
316 
317 #define CAL_WR_DMA_ADDR_MASK			GENMASK(31, 4)
318 
319 #define CAL_WR_DMA_OFST_MASK			GENMASK(18, 4)
320 #define CAL_WR_DMA_OFST_CIRC_MODE_MASK		GENMASK(23, 22)
321 #define CAL_WR_DMA_OFST_CIRC_MODE_ONE			1
322 #define CAL_WR_DMA_OFST_CIRC_MODE_FOUR			2
323 #define CAL_WR_DMA_OFST_CIRC_MODE_SIXTYFOUR		3
324 #define CAL_WR_DMA_OFST_CIRC_MODE_DISABLED		0
325 #define CAL_WR_DMA_OFST_CIRC_SIZE_MASK		GENMASK(31, 24)
326 
327 #define CAL_WR_DMA_XSIZE_XSKIP_MASK		GENMASK(15, 3)
328 #define CAL_WR_DMA_XSIZE_MASK			GENMASK(31, 19)
329 
330 #define CAL_CSI2_PPI_CTRL_IF_EN_MASK		BIT(0)
331 #define CAL_CSI2_PPI_CTRL_ECC_EN_MASK		BIT(2)
332 #define CAL_CSI2_PPI_CTRL_FRAME_MASK		BIT(3)
333 #define CAL_CSI2_PPI_CTRL_FRAME_IMMEDIATE		0
334 #define CAL_CSI2_PPI_CTRL_FRAME				1
335 
336 #define CAL_CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK	GENMASK(2, 0)
337 #define CAL_CSI2_COMPLEXIO_CFG_POSITION_5			5
338 #define CAL_CSI2_COMPLEXIO_CFG_POSITION_4			4
339 #define CAL_CSI2_COMPLEXIO_CFG_POSITION_3			3
340 #define CAL_CSI2_COMPLEXIO_CFG_POSITION_2			2
341 #define CAL_CSI2_COMPLEXIO_CFG_POSITION_1			1
342 #define CAL_CSI2_COMPLEXIO_CFG_POSITION_NOT_USED		0
343 #define CAL_CSI2_COMPLEXIO_CFG_CLOCK_POL_MASK		BIT(3)
344 #define CAL_CSI2_COMPLEXIO_CFG_POL_PLUSMINUS			0
345 #define CAL_CSI2_COMPLEXIO_CFG_POL_MINUSPLUS			1
346 #define CAL_CSI2_COMPLEXIO_CFG_DATA1_POSITION_MASK	GENMASK(6, 4)
347 #define CAL_CSI2_COMPLEXIO_CFG_DATA1_POL_MASK		BIT(7)
348 #define CAL_CSI2_COMPLEXIO_CFG_DATA2_POSITION_MASK	GENMASK(10, 8)
349 #define CAL_CSI2_COMPLEXIO_CFG_DATA2_POL_MASK		BIT(11)
350 #define CAL_CSI2_COMPLEXIO_CFG_DATA3_POSITION_MASK	GENMASK(14, 12)
351 #define CAL_CSI2_COMPLEXIO_CFG_DATA3_POL_MASK		BIT(15)
352 #define CAL_CSI2_COMPLEXIO_CFG_DATA4_POSITION_MASK	GENMASK(18, 16)
353 #define CAL_CSI2_COMPLEXIO_CFG_DATA4_POL_MASK		BIT(19)
354 #define CAL_CSI2_COMPLEXIO_CFG_PWR_AUTO_MASK		BIT(24)
355 #define CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_MASK		GENMASK(26, 25)
356 #define CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_STATE_OFF		0
357 #define CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_STATE_ON		1
358 #define CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_STATE_ULP		2
359 #define CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK		GENMASK(28, 27)
360 #define CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_OFF		0
361 #define CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ON			1
362 #define CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ULP		2
363 #define CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK		BIT(29)
364 #define CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED	1
365 #define CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETONGOING		0
366 #define CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK		BIT(30)
367 #define CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL			0
368 #define CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_OPERATIONAL		1
369 
370 #define CAL_CSI2_SHORT_PACKET_MASK	GENMASK(23, 0)
371 
372 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS1_MASK		BIT(0)
373 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS2_MASK		BIT(1)
374 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS3_MASK		BIT(2)
375 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS4_MASK		BIT(3)
376 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS5_MASK		BIT(4)
377 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS1_MASK	BIT(5)
378 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS2_MASK	BIT(6)
379 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS3_MASK	BIT(7)
380 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS4_MASK	BIT(8)
381 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS5_MASK	BIT(9)
382 #define CAL_CSI2_COMPLEXIO_IRQ_ERRESC1_MASK		BIT(10)
383 #define CAL_CSI2_COMPLEXIO_IRQ_ERRESC2_MASK		BIT(11)
384 #define CAL_CSI2_COMPLEXIO_IRQ_ERRESC3_MASK		BIT(12)
385 #define CAL_CSI2_COMPLEXIO_IRQ_ERRESC4_MASK		BIT(13)
386 #define CAL_CSI2_COMPLEXIO_IRQ_ERRESC5_MASK		BIT(14)
387 #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL1_MASK		BIT(15)
388 #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL2_MASK		BIT(16)
389 #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL3_MASK		BIT(17)
390 #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL4_MASK		BIT(18)
391 #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL5_MASK		BIT(19)
392 #define CAL_CSI2_COMPLEXIO_IRQ_LANE_ERRORS_MASK		GENMASK(19, 0)
393 #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM1_MASK		BIT(20)
394 #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM2_MASK		BIT(21)
395 #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM3_MASK		BIT(22)
396 #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM4_MASK		BIT(23)
397 #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM5_MASK		BIT(24)
398 #define CAL_CSI2_COMPLEXIO_IRQ_STATEALLULPMENTER_MASK	BIT(25)
399 #define CAL_CSI2_COMPLEXIO_IRQ_STATEALLULPMEXIT_MASK	BIT(26)
400 #define CAL_CSI2_COMPLEXIO_IRQ_FIFO_OVR_MASK		BIT(27)
401 #define CAL_CSI2_COMPLEXIO_IRQ_SHORT_PACKET_MASK	BIT(28)
402 #define CAL_CSI2_COMPLEXIO_IRQ_ECC_NO_CORRECTION_MASK	BIT(30)
403 
404 #define CAL_CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK	GENMASK(12, 0)
405 #define CAL_CSI2_TIMING_STOP_STATE_X4_IO1_MASK		BIT(13)
406 #define CAL_CSI2_TIMING_STOP_STATE_X16_IO1_MASK		BIT(14)
407 #define CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK		BIT(15)
408 
409 #define CAL_CSI2_VC_IRQ_FS_IRQ_MASK(n)			BIT(0 + ((n) * 8))
410 #define CAL_CSI2_VC_IRQ_FE_IRQ_MASK(n)			BIT(1 + ((n) * 8))
411 #define CAL_CSI2_VC_IRQ_LS_IRQ_MASK(n)			BIT(2 + ((n) * 8))
412 #define CAL_CSI2_VC_IRQ_LE_IRQ_MASK(n)			BIT(3 + ((n) * 8))
413 #define CAL_CSI2_VC_IRQ_CS_IRQ_MASK(n)			BIT(4 + ((n) * 8))
414 #define CAL_CSI2_VC_IRQ_ECC_CORRECTION_IRQ_MASK(n)	BIT(5 + ((n) * 8))
415 
416 #define CAL_CSI2_CTX_DT_MASK		GENMASK(5, 0)
417 #define CAL_CSI2_CTX_DT_DISABLED	0
418 #define CAL_CSI2_CTX_DT_ANY		1
419 #define CAL_CSI2_CTX_VC_MASK		GENMASK(7, 6)
420 #define CAL_CSI2_CTX_CPORT_MASK		GENMASK(12, 8)
421 #define CAL_CSI2_CTX_ATT_MASK		BIT(13)
422 #define CAL_CSI2_CTX_ATT_PIX			0
423 #define CAL_CSI2_CTX_ATT			1
424 #define CAL_CSI2_CTX_PACK_MODE_MASK	BIT(14)
425 #define CAL_CSI2_CTX_PACK_MODE_LINE		0
426 #define CAL_CSI2_CTX_PACK_MODE_FRAME		1
427 #define CAL_CSI2_CTX_LINES_MASK		GENMASK(29, 16)
428 
429 #define CAL_CSI2_STATUS_FRAME_MASK	GENMASK(15, 0)
430 
431 #define CAL_CSI2_PHY_REG0_THS_SETTLE_MASK	GENMASK(7, 0)
432 #define CAL_CSI2_PHY_REG0_THS_TERM_MASK		GENMASK(15, 8)
433 #define CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_MASK	BIT(24)
434 #define CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_DISABLE		1
435 #define CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_ENABLE		0
436 
437 #define CAL_CSI2_PHY_REG1_TCLK_SETTLE_MASK			GENMASK(7, 0)
438 #define CAL_CSI2_PHY_REG1_CTRLCLK_DIV_FACTOR_MASK		GENMASK(9, 8)
439 #define CAL_CSI2_PHY_REG1_DPHY_HS_SYNC_PATTERN_MASK		GENMASK(17, 10)
440 #define CAL_CSI2_PHY_REG1_TCLK_TERM_MASK			GENMASK(24, 18)
441 #define CAL_CSI2_PHY_REG1_CLOCK_MISS_DETECTOR_STATUS_MASK	BIT(25)
442 #define CAL_CSI2_PHY_REG1_CLOCK_MISS_DETECTOR_STATUS_ERROR		1
443 #define CAL_CSI2_PHY_REG1_CLOCK_MISS_DETECTOR_STATUS_SUCCESS		0
444 #define CAL_CSI2_PHY_REG1_RESET_DONE_STATUS_MASK		GENMASK(29, 28)
445 
446 #define CAL_CSI2_PHY_REG10_I933_LDO_DISABLE_MASK		BIT(6)
447 
448 #define CAL_CSI2_PHY_REG2_CCP2_SYNC_PATTERN_MASK		GENMASK(23, 0)
449 #define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC3_MASK		GENMASK(25, 24)
450 #define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC2_MASK		GENMASK(27, 26)
451 #define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC1_MASK		GENMASK(29, 28)
452 #define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC0_MASK		GENMASK(31, 30)
453 
454 #define CM_CAMERRX_CTRL_CSI1_CTRLCLKEN_MASK			BIT(0)
455 #define CM_CAMERRX_CTRL_CSI1_CAMMODE_MASK			GENMASK(2, 1)
456 #define CM_CAMERRX_CTRL_CSI1_LANEENABLE_MASK			GENMASK(4, 3)
457 #define CM_CAMERRX_CTRL_CSI1_MODE_MASK				BIT(5)
458 #define CM_CAMERRX_CTRL_CSI0_CTRLCLKEN_MASK			BIT(10)
459 #define CM_CAMERRX_CTRL_CSI0_CAMMODE_MASK			GENMASK(12, 11)
460 #define CM_CAMERRX_CTRL_CSI0_LANEENABLE_MASK			GENMASK(16, 13)
461 #define CM_CAMERRX_CTRL_CSI0_MODE_MASK				BIT(17)
462 
463 #endif
464