1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * PXA LCD Controller
4 *
5 * (C) Copyright 2001-2002
6 * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
7 */
8
9 /************************************************************************/
10 /* ** HEADER FILES */
11 /************************************************************************/
12
13 #include <common.h>
14 #include <asm/arch/pxa-regs.h>
15 #include <asm/io.h>
16 #include <lcd.h>
17 #include <linux/types.h>
18 #include <stdarg.h>
19 #include <stdio_dev.h>
20
21 /* #define DEBUG */
22
23 #ifdef CONFIG_LCD
24
25 /*----------------------------------------------------------------------*/
26 /*
27 * Define panel bpp, LCCR0, LCCR3 and panel_info video struct for
28 * your display.
29 */
30
31 #ifdef CONFIG_PXA_VGA
32 /* LCD outputs connected to a video DAC */
33 # define LCD_BPP LCD_COLOR8
34
35 /* you have to set lccr0 and lccr3 (including pcd) */
36 # define REG_LCCR0 0x003008f8
37 # define REG_LCCR3 0x0300FF01
38
39 /* 640x480x16 @ 61 Hz */
40 vidinfo_t panel_info = {
41 .vl_col = 640,
42 .vl_row = 480,
43 .vl_width = 640,
44 .vl_height = 480,
45 .vl_clkp = CONFIG_SYS_HIGH,
46 .vl_oep = CONFIG_SYS_HIGH,
47 .vl_hsp = CONFIG_SYS_HIGH,
48 .vl_vsp = CONFIG_SYS_HIGH,
49 .vl_dp = CONFIG_SYS_HIGH,
50 .vl_bpix = LCD_BPP,
51 .vl_lbw = 0,
52 .vl_splt = 0,
53 .vl_clor = 0,
54 .vl_tft = 1,
55 .vl_hpw = 40,
56 .vl_blw = 56,
57 .vl_elw = 56,
58 .vl_vpw = 20,
59 .vl_bfw = 8,
60 .vl_efw = 8,
61 };
62 #endif /* CONFIG_PXA_VIDEO */
63
64 /*----------------------------------------------------------------------*/
65 #ifdef CONFIG_SHARP_LM8V31
66
67 # define LCD_BPP LCD_COLOR8
68 # define LCD_INVERT_COLORS /* Needed for colors to be correct, but why? */
69
70 /* you have to set lccr0 and lccr3 (including pcd) */
71 # define REG_LCCR0 0x0030087C
72 # define REG_LCCR3 0x0340FF08
73
74 vidinfo_t panel_info = {
75 .vl_col = 640,
76 .vl_row = 480,
77 .vl_width = 157,
78 .vl_height = 118,
79 .vl_clkp = CONFIG_SYS_HIGH,
80 .vl_oep = CONFIG_SYS_HIGH,
81 .vl_hsp = CONFIG_SYS_HIGH,
82 .vl_vsp = CONFIG_SYS_HIGH,
83 .vl_dp = CONFIG_SYS_HIGH,
84 .vl_bpix = LCD_BPP,
85 .vl_lbw = 0,
86 .vl_splt = 1,
87 .vl_clor = 1,
88 .vl_tft = 0,
89 .vl_hpw = 1,
90 .vl_blw = 3,
91 .vl_elw = 3,
92 .vl_vpw = 1,
93 .vl_bfw = 0,
94 .vl_efw = 0,
95 };
96 #endif /* CONFIG_SHARP_LM8V31 */
97 /*----------------------------------------------------------------------*/
98 #ifdef CONFIG_VOIPAC_LCD
99
100 # define LCD_BPP LCD_COLOR8
101 # define LCD_INVERT_COLORS
102
103 /* you have to set lccr0 and lccr3 (including pcd) */
104 # define REG_LCCR0 0x043008f8
105 # define REG_LCCR3 0x0340FF08
106
107 vidinfo_t panel_info = {
108 .vl_col = 640,
109 .vl_row = 480,
110 .vl_width = 157,
111 .vl_height = 118,
112 .vl_clkp = CONFIG_SYS_HIGH,
113 .vl_oep = CONFIG_SYS_HIGH,
114 .vl_hsp = CONFIG_SYS_HIGH,
115 .vl_vsp = CONFIG_SYS_HIGH,
116 .vl_dp = CONFIG_SYS_HIGH,
117 .vl_bpix = LCD_BPP,
118 .vl_lbw = 0,
119 .vl_splt = 1,
120 .vl_clor = 1,
121 .vl_tft = 1,
122 .vl_hpw = 32,
123 .vl_blw = 144,
124 .vl_elw = 32,
125 .vl_vpw = 2,
126 .vl_bfw = 13,
127 .vl_efw = 30,
128 };
129 #endif /* CONFIG_VOIPAC_LCD */
130
131 /*----------------------------------------------------------------------*/
132 #ifdef CONFIG_HITACHI_SX14
133 /* Hitachi SX14Q004-ZZA color STN LCD */
134 #define LCD_BPP LCD_COLOR8
135
136 /* you have to set lccr0 and lccr3 (including pcd) */
137 #define REG_LCCR0 0x00301079
138 #define REG_LCCR3 0x0340FF20
139
140 vidinfo_t panel_info = {
141 .vl_col = 320,
142 .vl_row = 240,
143 .vl_width = 167,
144 .vl_height = 109,
145 .vl_clkp = CONFIG_SYS_HIGH,
146 .vl_oep = CONFIG_SYS_HIGH,
147 .vl_hsp = CONFIG_SYS_HIGH,
148 .vl_vsp = CONFIG_SYS_HIGH,
149 .vl_dp = CONFIG_SYS_HIGH,
150 .vl_bpix = LCD_BPP,
151 .vl_lbw = 1,
152 .vl_splt = 0,
153 .vl_clor = 1,
154 .vl_tft = 0,
155 .vl_hpw = 1,
156 .vl_blw = 1,
157 .vl_elw = 1,
158 .vl_vpw = 7,
159 .vl_bfw = 0,
160 .vl_efw = 0,
161 };
162 #endif /* CONFIG_HITACHI_SX14 */
163
164 /*----------------------------------------------------------------------*/
165 #ifdef CONFIG_LMS283GF05
166
167 # define LCD_BPP LCD_COLOR8
168 /*# define LCD_INVERT_COLORS*/
169
170 /* you have to set lccr0 and lccr3 (including pcd) */
171 # define REG_LCCR0 0x043008f8
172 # define REG_LCCR3 0x03b00009
173
174 vidinfo_t panel_info = {
175 .vl_col = 240,
176 .vl_row = 320,
177 .vl_rot = 3,
178 .vl_width = 240,
179 .vl_height = 320,
180 .vl_clkp = CONFIG_SYS_HIGH,
181 .vl_oep = CONFIG_SYS_LOW,
182 .vl_hsp = CONFIG_SYS_LOW,
183 .vl_vsp = CONFIG_SYS_LOW,
184 .vl_dp = CONFIG_SYS_HIGH,
185 .vl_bpix = LCD_BPP,
186 .vl_lbw = 0,
187 .vl_splt = 1,
188 .vl_clor = 1,
189 .vl_tft = 1,
190 .vl_hpw = 4,
191 .vl_blw = 4,
192 .vl_elw = 8,
193 .vl_vpw = 4,
194 .vl_bfw = 4,
195 .vl_efw = 8,
196 };
197 #endif /* CONFIG_LMS283GF05 */
198
199 /*----------------------------------------------------------------------*/
200
201 #ifdef CONFIG_ACX517AKN
202
203 # define LCD_BPP LCD_COLOR8
204
205 /* you have to set lccr0 and lccr3 (including pcd) */
206 # define REG_LCCR0 0x003008f9
207 # define REG_LCCR3 0x03700006
208
209 vidinfo_t panel_info = {
210 .vl_col = 320,
211 .vl_row = 320,
212 .vl_width = 320,
213 .vl_height = 320,
214 .vl_clkp = CONFIG_SYS_HIGH,
215 .vl_oep = CONFIG_SYS_LOW,
216 .vl_hsp = CONFIG_SYS_LOW,
217 .vl_vsp = CONFIG_SYS_LOW,
218 .vl_dp = CONFIG_SYS_HIGH,
219 .vl_bpix = LCD_BPP,
220 .vl_lbw = 0,
221 .vl_splt = 1,
222 .vl_clor = 1,
223 .vl_tft = 1,
224 .vl_hpw = 0x04,
225 .vl_blw = 0x1c,
226 .vl_elw = 0x08,
227 .vl_vpw = 0x01,
228 .vl_bfw = 0x07,
229 .vl_efw = 0x08,
230 };
231 #endif /* CONFIG_ACX517AKN */
232
233 #ifdef CONFIG_ACX544AKN
234
235 # define LCD_BPP LCD_COLOR16
236
237 /* you have to set lccr0 and lccr3 (including pcd) */
238 # define REG_LCCR0 0x003008f9
239 # define REG_LCCR3 0x04700007 /* 16bpp */
240
241 vidinfo_t panel_info = {
242 .vl_col = 320,
243 .vl_row = 320,
244 .vl_width = 320,
245 .vl_height = 320,
246 .vl_clkp = CONFIG_SYS_LOW,
247 .vl_oep = CONFIG_SYS_LOW,
248 .vl_hsp = CONFIG_SYS_LOW,
249 .vl_vsp = CONFIG_SYS_LOW,
250 .vl_dp = CONFIG_SYS_LOW,
251 .vl_bpix = LCD_BPP,
252 .vl_lbw = 0,
253 .vl_splt = 0,
254 .vl_clor = 1,
255 .vl_tft = 1,
256 .vl_hpw = 0x05,
257 .vl_blw = 0x13,
258 .vl_elw = 0x08,
259 .vl_vpw = 0x02,
260 .vl_bfw = 0x07,
261 .vl_efw = 0x05,
262 };
263 #endif /* CONFIG_ACX544AKN */
264
265 /*----------------------------------------------------------------------*/
266
267 #ifdef CONFIG_LQ038J7DH53
268
269 # define LCD_BPP LCD_COLOR8
270
271 /* you have to set lccr0 and lccr3 (including pcd) */
272 # define REG_LCCR0 0x003008f9
273 # define REG_LCCR3 0x03700004
274
275 vidinfo_t panel_info = {
276 .vl_col = 320,
277 .vl_row = 480,
278 .vl_width = 320,
279 .vl_height = 480,
280 .vl_clkp = CONFIG_SYS_HIGH,
281 .vl_oep = CONFIG_SYS_LOW,
282 .vl_hsp = CONFIG_SYS_LOW,
283 .vl_vsp = CONFIG_SYS_LOW,
284 .vl_dp = CONFIG_SYS_HIGH,
285 .vl_bpix = LCD_BPP,
286 .vl_lbw = 0,
287 .vl_splt = 1,
288 .vl_clor = 1,
289 .vl_tft = 1,
290 .vl_hpw = 0x04,
291 .vl_blw = 0x20,
292 .vl_elw = 0x01,
293 .vl_vpw = 0x01,
294 .vl_bfw = 0x04,
295 .vl_efw = 0x01,
296 };
297 #endif /* CONFIG_ACX517AKN */
298
299 /*----------------------------------------------------------------------*/
300
301 #ifdef CONFIG_LITTLETON_LCD
302 # define LCD_BPP LCD_COLOR8
303
304 /* you have to set lccr0 and lccr3 (including pcd) */
305 # define REG_LCCR0 0x003008f8
306 # define REG_LCCR3 0x0300FF04
307
308 vidinfo_t panel_info = {
309 .vl_col = 480,
310 .vl_row = 640,
311 .vl_width = 480,
312 .vl_height = 640,
313 .vl_clkp = CONFIG_SYS_HIGH,
314 .vl_oep = CONFIG_SYS_HIGH,
315 .vl_hsp = CONFIG_SYS_HIGH,
316 .vl_vsp = CONFIG_SYS_HIGH,
317 .vl_dp = CONFIG_SYS_HIGH,
318 .vl_bpix = LCD_BPP,
319 .vl_lbw = 0,
320 .vl_splt = 0,
321 .vl_clor = 0,
322 .vl_tft = 1,
323 .vl_hpw = 9,
324 .vl_blw = 8,
325 .vl_elw = 24,
326 .vl_vpw = 2,
327 .vl_bfw = 2,
328 .vl_efw = 4,
329 };
330 #endif /* CONFIG_LITTLETON_LCD */
331
332 /*----------------------------------------------------------------------*/
333
334 static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid);
335 static void pxafb_setup_gpio (vidinfo_t *vid);
336 static void pxafb_enable_controller (vidinfo_t *vid);
337 static int pxafb_init (vidinfo_t *vid);
338
339 /************************************************************************/
340 /* --------------- PXA chipset specific functions ------------------- */
341 /************************************************************************/
342
configuration_get_cmap(void)343 ushort *configuration_get_cmap(void)
344 {
345 struct pxafb_info *fbi = &panel_info.pxa;
346 return (ushort *)fbi->palette;
347 }
348
lcd_ctrl_init(void * lcdbase)349 void lcd_ctrl_init (void *lcdbase)
350 {
351 pxafb_init_mem(lcdbase, &panel_info);
352 pxafb_init(&panel_info);
353 pxafb_setup_gpio(&panel_info);
354 pxafb_enable_controller(&panel_info);
355 }
356
357 /*----------------------------------------------------------------------*/
358 #if LCD_BPP == LCD_COLOR8
359 void
lcd_setcolreg(ushort regno,ushort red,ushort green,ushort blue)360 lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
361 {
362 struct pxafb_info *fbi = &panel_info.pxa;
363 unsigned short *palette = (unsigned short *)fbi->palette;
364 u_int val;
365
366 if (regno < fbi->palette_size) {
367 val = ((red << 8) & 0xf800);
368 val |= ((green << 4) & 0x07e0);
369 val |= (blue & 0x001f);
370
371 #ifdef LCD_INVERT_COLORS
372 palette[regno] = ~val;
373 #else
374 palette[regno] = val;
375 #endif
376 }
377
378 debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n",
379 regno, &palette[regno],
380 red, green, blue,
381 palette[regno]);
382 }
383 #endif /* LCD_COLOR8 */
384
385 /*----------------------------------------------------------------------*/
lcd_enable(void)386 __weak void lcd_enable(void)
387 {
388 }
389
390 /************************************************************************/
391 /* ** PXA255 specific routines */
392 /************************************************************************/
393
394 /*
395 * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb,
396 * descriptors and palette areas.
397 */
calc_fbsize(void)398 ulong calc_fbsize (void)
399 {
400 ulong size;
401 int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
402
403 size = line_length * panel_info.vl_row;
404 size += PAGE_SIZE;
405
406 return size;
407 }
408
pxafb_init_mem(void * lcdbase,vidinfo_t * vid)409 static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid)
410 {
411 u_long palette_mem_size;
412 struct pxafb_info *fbi = &vid->pxa;
413 int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
414
415 fbi->screen = (u_long)lcdbase;
416
417 fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
418 palette_mem_size = fbi->palette_size * sizeof(u16);
419
420 debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
421 /* locate palette and descs at end of page following fb */
422 fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
423
424 return 0;
425 }
426 #ifdef CONFIG_CPU_MONAHANS
pxafb_setup_gpio(vidinfo_t * vid)427 static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
428 #else
pxafb_setup_gpio(vidinfo_t * vid)429 static void pxafb_setup_gpio (vidinfo_t *vid)
430 {
431 u_long lccr0;
432
433 /*
434 * setup is based on type of panel supported
435 */
436
437 lccr0 = vid->pxa.reg_lccr0;
438
439 /* 4 bit interface */
440 if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD))
441 {
442 debug("Setting GPIO for 4 bit data\n");
443 /* bits 58-61 */
444 writel(readl(GPDR1) | (0xf << 26), GPDR1);
445 writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20),
446 GAFR1_U);
447
448 /* bits 74-77 */
449 writel(readl(GPDR2) | (0xf << 10), GPDR2);
450 writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
451 GAFR2_L);
452 }
453
454 /* 8 bit interface */
455 else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) ||
456 (!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS)))
457 {
458 debug("Setting GPIO for 8 bit data\n");
459 /* bits 58-65 */
460 writel(readl(GPDR1) | (0x3f << 26), GPDR1);
461 writel(readl(GPDR2) | (0x3), GPDR2);
462
463 writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
464 GAFR1_U);
465 writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L);
466
467 /* bits 74-77 */
468 writel(readl(GPDR2) | (0xf << 10), GPDR2);
469 writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
470 GAFR2_L);
471 }
472
473 /* 16 bit interface */
474 else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS)))
475 {
476 debug("Setting GPIO for 16 bit data\n");
477 /* bits 58-77 */
478 writel(readl(GPDR1) | (0x3f << 26), GPDR1);
479 writel(readl(GPDR2) | 0x00003fff, GPDR2);
480
481 writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
482 GAFR1_U);
483 writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L);
484 }
485 else
486 {
487 printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
488 }
489 }
490 #endif
491
pxafb_enable_controller(vidinfo_t * vid)492 static void pxafb_enable_controller (vidinfo_t *vid)
493 {
494 debug("Enabling LCD controller\n");
495
496 /* Sequence from 11.7.10 */
497 writel(vid->pxa.reg_lccr3, LCCR3);
498 writel(vid->pxa.reg_lccr2, LCCR2);
499 writel(vid->pxa.reg_lccr1, LCCR1);
500 writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0);
501 writel(vid->pxa.fdadr0, FDADR0);
502 writel(vid->pxa.fdadr1, FDADR1);
503 writel(readl(LCCR0) | LCCR0_ENB, LCCR0);
504
505 #ifdef CONFIG_CPU_MONAHANS
506 writel(readl(CKENA) | CKENA_1_LCD, CKENA);
507 #else
508 writel(readl(CKEN) | CKEN16_LCD, CKEN);
509 #endif
510
511 debug("FDADR0 = 0x%08x\n", readl(FDADR0));
512 debug("FDADR1 = 0x%08x\n", readl(FDADR1));
513 debug("LCCR0 = 0x%08x\n", readl(LCCR0));
514 debug("LCCR1 = 0x%08x\n", readl(LCCR1));
515 debug("LCCR2 = 0x%08x\n", readl(LCCR2));
516 debug("LCCR3 = 0x%08x\n", readl(LCCR3));
517 }
518
pxafb_init(vidinfo_t * vid)519 static int pxafb_init (vidinfo_t *vid)
520 {
521 struct pxafb_info *fbi = &vid->pxa;
522
523 debug("Configuring PXA LCD\n");
524
525 fbi->reg_lccr0 = REG_LCCR0;
526 fbi->reg_lccr3 = REG_LCCR3;
527
528 debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n",
529 vid->vl_col, vid->vl_hpw,
530 vid->vl_blw, vid->vl_elw);
531 debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n",
532 vid->vl_row, vid->vl_vpw,
533 vid->vl_bfw, vid->vl_efw);
534
535 fbi->reg_lccr1 =
536 LCCR1_DisWdth(vid->vl_col) +
537 LCCR1_HorSnchWdth(vid->vl_hpw) +
538 LCCR1_BegLnDel(vid->vl_blw) +
539 LCCR1_EndLnDel(vid->vl_elw);
540
541 fbi->reg_lccr2 =
542 LCCR2_DisHght(vid->vl_row) +
543 LCCR2_VrtSnchWdth(vid->vl_vpw) +
544 LCCR2_BegFrmDel(vid->vl_bfw) +
545 LCCR2_EndFrmDel(vid->vl_efw);
546
547 fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP);
548 fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH)
549 | (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH);
550
551
552 /* setup dma descriptors */
553 fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
554 fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
555 fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
556
557 #define BYTES_PER_PANEL ((fbi->reg_lccr0 & LCCR0_SDS) ? \
558 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \
559 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8))
560
561 /* populate descriptors */
562 fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow;
563 fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL;
564 fbi->dmadesc_fblow->fidr = 0;
565 fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL;
566
567 fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */
568
569 fbi->dmadesc_fbhigh->fsadr = fbi->screen;
570 fbi->dmadesc_fbhigh->fidr = 0;
571 fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL;
572
573 fbi->dmadesc_palette->fsadr = fbi->palette;
574 fbi->dmadesc_palette->fidr = 0;
575 fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
576
577 if( NBITS(vid->vl_bpix) < 12)
578 {
579 /* assume any mode with <12 bpp is palette driven */
580 fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh;
581 fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette;
582 /* flips back and forth between pal and fbhigh */
583 fbi->fdadr0 = (u_long)fbi->dmadesc_palette;
584 }
585 else
586 {
587 /* palette shouldn't be loaded in true-color mode */
588 fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh;
589 fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */
590 }
591
592 debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow);
593 debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh);
594 debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette);
595
596 debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr);
597 debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr);
598 debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr);
599
600 debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr);
601 debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr);
602 debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr);
603
604 debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd);
605 debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd);
606 debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd);
607
608 return 0;
609 }
610
611 /************************************************************************/
612 /************************************************************************/
613
614 #endif /* CONFIG_LCD */
615