1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019  Realtek Corporation
3  */
4 
5 #ifndef __RTW_REG_DEF_H__
6 #define __RTW_REG_DEF_H__
7 
8 #define REG_SYS_FUNC_EN		0x0002
9 #define BIT_FEN_EN_25_1		BIT(13)
10 #define BIT_FEN_ELDR		BIT(12)
11 #define BIT_FEN_CPUEN		BIT(2)
12 #define BIT_FEN_BB_GLB_RST	BIT(1)
13 #define BIT_FEN_BB_RSTB		BIT(0)
14 #define BIT_R_DIS_PRST		BIT(6)
15 #define BIT_WLOCK_1C_B6		BIT(5)
16 #define REG_SYS_PW_CTRL		0x0004
17 #define BIT_PFM_WOWL		BIT(3)
18 #define REG_SYS_CLK_CTRL	0x0008
19 #define BIT_CPU_CLK_EN		BIT(14)
20 
21 #define REG_SYS_CLKR		0x0008
22 #define BIT_ANA8M		BIT(1)
23 #define BIT_WAKEPAD_EN		BIT(3)
24 #define BIT_LOADER_CLK_EN	BIT(5)
25 
26 #define REG_RSV_CTRL		0x001C
27 #define DISABLE_PI		0x3
28 #define ENABLE_PI		0x2
29 #define BITS_RFC_DIRECT		(BIT(31) | BIT(30))
30 #define BIT_WLMCU_IOIF		BIT(0)
31 #define REG_RF_CTRL		0x001F
32 #define BIT_RF_SDM_RSTB		BIT(2)
33 #define BIT_RF_RSTB		BIT(1)
34 #define BIT_RF_EN		BIT(0)
35 
36 #define REG_AFE_CTRL1		0x0024
37 #define BIT_MAC_CLK_SEL		(BIT(20) | BIT(21))
38 #define REG_EFUSE_CTRL		0x0030
39 #define BIT_EF_FLAG		BIT(31)
40 #define BIT_SHIFT_EF_ADDR	8
41 #define BIT_MASK_EF_ADDR	0x3ff
42 #define BIT_MASK_EF_DATA	0xff
43 #define BITS_EF_ADDR		(BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR)
44 #define BITS_PLL		0xf0
45 
46 #define REG_AFE_XTAL_CTRL	0x24
47 #define REG_AFE_PLL_CTRL	0x28
48 #define REG_AFE_CTRL3		0x2c
49 #define BIT_MASK_XTAL		0x00FFF000
50 #define BIT_XTAL_GMP_BIT4	BIT(28)
51 
52 #define REG_LDO_EFUSE_CTRL	0x0034
53 #define BIT_MASK_EFUSE_BANK_SEL	(BIT(8) | BIT(9))
54 
55 #define BIT_LDO25_VOLTAGE_V25	0x03
56 #define BIT_MASK_LDO25_VOLTAGE	GENMASK(6, 4)
57 #define BIT_SHIFT_LDO25_VOLTAGE	4
58 #define BIT_LDO25_EN		BIT(7)
59 
60 #define REG_GPIO_MUXCFG		0x0040
61 #define BIT_FSPI_EN		BIT(19)
62 #define BIT_EN_SIC		BIT(12)
63 
64 #define BIT_PO_BT_PTA_PINS	BIT(9)
65 #define BIT_BT_PTA_EN		BIT(5)
66 #define BIT_WLRFE_4_5_EN	BIT(2)
67 
68 #define REG_LED_CFG		0x004C
69 #define BIT_LNAON_SEL_EN	BIT(26)
70 #define BIT_PAPE_SEL_EN		BIT(25)
71 #define BIT_DPDT_WL_SEL		BIT(24)
72 #define BIT_DPDT_SEL_EN		BIT(23)
73 #define REG_LEDCFG2		0x004E
74 #define REG_PAD_CTRL1		0x0064
75 #define BIT_BT_BTG_SEL		BIT(31)
76 #define BIT_PAPE_WLBT_SEL	BIT(29)
77 #define BIT_LNAON_WLBT_SEL	BIT(28)
78 #define BIT_BTGP_JTAG_EN	BIT(24)
79 #define BIT_BTGP_SPI_EN		BIT(20)
80 #define BIT_LED1DIS		BIT(15)
81 #define BIT_SW_DPDT_SEL_DATA	BIT(0)
82 #define REG_WL_BT_PWR_CTRL	0x0068
83 #define BIT_BT_FUNC_EN		BIT(18)
84 #define BIT_BT_DIG_CLK_EN	BIT(8)
85 #define REG_SYS_SDIO_CTRL	0x0070
86 #define BIT_DBG_GNT_WL_BT	BIT(27)
87 #define BIT_LTE_MUX_CTRL_PATH	BIT(26)
88 #define REG_HCI_OPT_CTRL	0x0074
89 #define BIT_USB_SUS_DIS		BIT(8)
90 #define BIT_SDIO_PAD_E5		BIT(18)
91 
92 #define REG_AFE_CTRL_4		0x0078
93 #define BIT_CK320M_AFE_EN	BIT(4)
94 #define BIT_EN_SYN		BIT(15)
95 
96 #define REG_LDO_SWR_CTRL	0x007C
97 #define LDO_SEL			0xC3
98 #define SPS_SEL			0x83
99 #define BIT_XTA1		BIT(29)
100 #define BIT_XTA0		BIT(28)
101 
102 #define REG_MCUFW_CTRL		0x0080
103 #define BIT_ANA_PORT_EN		BIT(22)
104 #define BIT_MAC_PORT_EN		BIT(21)
105 #define BIT_BOOT_FSPI_EN	BIT(20)
106 #define BIT_ROM_DLEN		BIT(19)
107 #define BIT_ROM_PGE		GENMASK(18, 16)	/* legacy only */
108 #define BIT_SHIFT_ROM_PGE	16
109 #define BIT_FW_INIT_RDY		BIT(15)
110 #define BIT_FW_DW_RDY		BIT(14)
111 #define BIT_RPWM_TOGGLE		BIT(7)
112 #define BIT_RAM_DL_SEL		BIT(7)	/* legacy only */
113 #define BIT_DMEM_CHKSUM_OK	BIT(6)
114 #define BIT_WINTINI_RDY		BIT(6)	/* legacy only */
115 #define BIT_DMEM_DW_OK		BIT(5)
116 #define BIT_IMEM_CHKSUM_OK	BIT(4)
117 #define BIT_IMEM_DW_OK		BIT(3)
118 #define BIT_IMEM_BOOT_LOAD_CHECKSUM_OK BIT(2)
119 #define BIT_FWDL_CHK_RPT	BIT(2)	/* legacy only */
120 #define BIT_MCUFWDL_RDY		BIT(1)	/* legacy only */
121 #define BIT_MCUFWDL_EN		BIT(0)
122 #define BIT_CHECK_SUM_OK	(BIT(4) | BIT(6))
123 #define FW_READY		(BIT_FW_INIT_RDY | BIT_FW_DW_RDY |             \
124 				 BIT_IMEM_DW_OK | BIT_DMEM_DW_OK |             \
125 				 BIT_CHECK_SUM_OK)
126 #define FW_READY_LEGACY		(BIT_MCUFWDL_RDY | BIT_FWDL_CHK_RPT |	       \
127 				 BIT_WINTINI_RDY | BIT_RAM_DL_SEL)
128 #define FW_READY_MASK		0xffff
129 
130 #define REG_MCU_TST_CFG		0x84
131 #define VAL_FW_TRIGGER		0x1
132 
133 #define REG_PMC_DBG_CTRL1	0xa8
134 #define BITS_PMC_BT_IQK_STS	GENMASK(22, 21)
135 
136 #define REG_EFUSE_ACCESS	0x00CF
137 #define EFUSE_ACCESS_ON		0x69
138 #define EFUSE_ACCESS_OFF	0x00
139 
140 #define REG_WLRF1		0x00EC
141 #define REG_WIFI_BT_INFO	0x00AA
142 #define BIT_BT_INT_EN		BIT(15)
143 #define REG_SYS_CFG1		0x00F0
144 #define	BIT_RTL_ID		BIT(23)
145 #define BIT_LDO			BIT(24)
146 #define BIT_RF_TYPE_ID		BIT(27)
147 #define BIT_SHIFT_VENDOR_ID	16
148 #define BIT_MASK_VENDOR_ID	0xf
149 #define BIT_VENDOR_ID(x) (((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID)
150 #define BITS_VENDOR_ID		(BIT_MASK_VENDOR_ID << BIT_SHIFT_VENDOR_ID)
151 #define BIT_CLEAR_VENDOR_ID(x)	((x) & (~BITS_VENDOR_ID))
152 #define BIT_GET_VENDOR_ID(x) (((x) >> BIT_SHIFT_VENDOR_ID) & BIT_MASK_VENDOR_ID)
153 #define BIT_SHIFT_CHIP_VER	12
154 #define BIT_MASK_CHIP_VER	0xf
155 #define BIT_CHIP_VER(x)	 (((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER)
156 #define BITS_CHIP_VER		(BIT_MASK_CHIP_VER << BIT_SHIFT_CHIP_VER)
157 #define BIT_CLEAR_CHIP_VER(x)	((x) & (~BITS_CHIP_VER))
158 #define BIT_GET_CHIP_VER(x) (((x) >> BIT_SHIFT_CHIP_VER) & BIT_MASK_CHIP_VER)
159 #define REG_SYS_STATUS1		0x00F4
160 #define REG_SYS_STATUS2		0x00F8
161 #define REG_SYS_CFG2		0x00FC
162 #define REG_WLRF1		0x00EC
163 #define BIT_WLRF1_BBRF_EN	(BIT(24) | BIT(25) | BIT(26))
164 #define REG_CR			0x0100
165 #define BIT_32K_CAL_TMR_EN	BIT(10)
166 #define BIT_MAC_SEC_EN		BIT(9)
167 #define BIT_ENSWBCN		BIT(8)
168 #define BIT_MACRXEN		BIT(7)
169 #define BIT_MACTXEN		BIT(6)
170 #define BIT_SCHEDULE_EN		BIT(5)
171 #define BIT_PROTOCOL_EN		BIT(4)
172 #define BIT_RXDMA_EN		BIT(3)
173 #define BIT_TXDMA_EN		BIT(2)
174 #define BIT_HCI_RXDMA_EN	BIT(1)
175 #define BIT_HCI_TXDMA_EN	BIT(0)
176 #define MAC_TRX_ENABLE	(BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN | \
177 			BIT_RXDMA_EN | BIT_PROTOCOL_EN | BIT_SCHEDULE_EN | \
178 			BIT_MACTXEN | BIT_MACRXEN)
179 #define BIT_SHIFT_TXDMA_VOQ_MAP	4
180 #define BIT_MASK_TXDMA_VOQ_MAP	0x3
181 #define BIT_TXDMA_VOQ_MAP(x)                                                   \
182 	(((x) & BIT_MASK_TXDMA_VOQ_MAP) << BIT_SHIFT_TXDMA_VOQ_MAP)
183 #define BIT_SHIFT_TXDMA_VIQ_MAP	6
184 #define BIT_MASK_TXDMA_VIQ_MAP	0x3
185 #define BIT_TXDMA_VIQ_MAP(x)                                                   \
186 	(((x) & BIT_MASK_TXDMA_VIQ_MAP) << BIT_SHIFT_TXDMA_VIQ_MAP)
187 #define REG_TXDMA_PQ_MAP	0x010C
188 #define BIT_RXDMA_ARBBW_EN	BIT(0)
189 #define BIT_RXSHFT_EN		BIT(1)
190 #define BIT_RXDMA_AGG_EN	BIT(2)
191 #define BIT_TXDMA_BW_EN		BIT(3)
192 #define BIT_SHIFT_TXDMA_BEQ_MAP	8
193 #define BIT_MASK_TXDMA_BEQ_MAP	0x3
194 #define BIT_TXDMA_BEQ_MAP(x)                                                   \
195 	(((x) & BIT_MASK_TXDMA_BEQ_MAP) << BIT_SHIFT_TXDMA_BEQ_MAP)
196 #define BIT_SHIFT_TXDMA_BKQ_MAP	10
197 #define BIT_MASK_TXDMA_BKQ_MAP	0x3
198 #define BIT_TXDMA_BKQ_MAP(x)                                                   \
199 	(((x) & BIT_MASK_TXDMA_BKQ_MAP) << BIT_SHIFT_TXDMA_BKQ_MAP)
200 #define BIT_SHIFT_TXDMA_MGQ_MAP	12
201 #define BIT_MASK_TXDMA_MGQ_MAP	0x3
202 #define BIT_TXDMA_MGQ_MAP(x)                                                   \
203 	(((x) & BIT_MASK_TXDMA_MGQ_MAP) << BIT_SHIFT_TXDMA_MGQ_MAP)
204 #define BIT_SHIFT_TXDMA_HIQ_MAP	14
205 #define BIT_MASK_TXDMA_HIQ_MAP	0x3
206 #define BIT_TXDMA_HIQ_MAP(x)                                                   \
207 	(((x) & BIT_MASK_TXDMA_HIQ_MAP) << BIT_SHIFT_TXDMA_HIQ_MAP)
208 #define BIT_SHIFT_TXSC_40M	4
209 #define BIT_MASK_TXSC_40M	0xf
210 #define BIT_TXSC_40M(x)							       \
211 	(((x) & BIT_MASK_TXSC_40M) << BIT_SHIFT_TXSC_40M)
212 #define BIT_SHIFT_TXSC_20M	0
213 #define BIT_MASK_TXSC_20M	0xf
214 #define BIT_TXSC_20M(x)							       \
215 	(((x) & BIT_MASK_TXSC_20M) << BIT_SHIFT_TXSC_20M)
216 #define BIT_SHIFT_MAC_CLK_SEL	20
217 #define MAC_CLK_HW_DEF_80M	0
218 #define MAC_CLK_HW_DEF_40M	1
219 #define MAC_CLK_HW_DEF_20M	2
220 #define MAC_CLK_SPEED		80
221 
222 #define REG_CR			0x0100
223 #define REG_TRXFF_BNDY		0x0114
224 #define REG_RXFF_BNDY		0x011C
225 #define REG_FE1IMR		0x0120
226 #define BIT_FS_RXDONE		BIT(16)
227 #define REG_PKTBUF_DBG_CTRL	0x0140
228 #define REG_C2HEVT		0x01A0
229 #define REG_MCUTST_1		0x01C0
230 #define REG_MCUTST_II		0x01C4
231 #define REG_WOWLAN_WAKE_REASON	0x01C7
232 #define REG_HMETFR		0x01CC
233 #define REG_HMEBOX0		0x01D0
234 #define REG_HMEBOX1		0x01D4
235 #define REG_HMEBOX2		0x01D8
236 #define REG_HMEBOX3		0x01DC
237 #define REG_HMEBOX0_EX		0x01F0
238 #define REG_HMEBOX1_EX		0x01F4
239 #define REG_HMEBOX2_EX		0x01F8
240 #define REG_HMEBOX3_EX		0x01FC
241 
242 #define REG_RQPN		0x0200
243 #define BIT_MASK_HPQ		0xff
244 #define BIT_SHIFT_HPQ		0
245 #define BIT_RQPN_HPQ(x)		(((x) & BIT_MASK_HPQ) << BIT_SHIFT_HPQ)
246 #define BIT_MASK_LPQ		0xff
247 #define BIT_SHIFT_LPQ		8
248 #define BIT_RQPN_LPQ(x)		(((x) & BIT_MASK_LPQ) << BIT_SHIFT_LPQ)
249 #define BIT_MASK_PUBQ		0xff
250 #define BIT_SHIFT_PUBQ		16
251 #define BIT_RQPN_PUBQ(x)	(((x) & BIT_MASK_PUBQ) << BIT_SHIFT_PUBQ)
252 #define BIT_RQPN_HLP(h, l, p)	(BIT_LD_RQPN | BIT_RQPN_HPQ(h) |	       \
253 				 BIT_RQPN_LPQ(l) | BIT_RQPN_PUBQ(p))
254 
255 #define REG_FIFOPAGE_CTRL_2	0x0204
256 #define BIT_BCN_VALID_V1	BIT(15)
257 #define BIT_MASK_BCN_HEAD_1_V1	0xfff
258 #define REG_AUTO_LLT_V1		0x0208
259 #define BIT_AUTO_INIT_LLT_V1	BIT(0)
260 #define REG_DWBCN0_CTRL		0x0208
261 #define BIT_BCN_VALID		BIT(16)
262 #define REG_TXDMA_OFFSET_CHK	0x020C
263 #define BIT_DROP_DATA_EN	BIT(9)
264 #define REG_TXDMA_STATUS	0x0210
265 #define BTI_PAGE_OVF		BIT(2)
266 
267 #define REG_RQPN_NPQ		0x0214
268 #define BIT_MASK_NPQ		0xff
269 #define BIT_SHIFT_NPQ		0
270 #define BIT_MASK_EPQ		0xff
271 #define BIT_SHIFT_EPQ		16
272 #define BIT_RQPN_NPQ(x)		(((x) & BIT_MASK_NPQ) << BIT_SHIFT_NPQ)
273 #define BIT_RQPN_EPQ(x)		(((x) & BIT_MASK_EPQ) << BIT_SHIFT_EPQ)
274 #define BIT_RQPN_NE(n, e)	(BIT_RQPN_NPQ(n) | BIT_RQPN_EPQ(e))
275 
276 #define REG_AUTO_LLT		0x0224
277 #define BIT_AUTO_INIT_LLT	BIT(16)
278 #define REG_RQPN_CTRL_1		0x0228
279 #define REG_RQPN_CTRL_2		0x022C
280 #define BIT_LD_RQPN		BIT(31)
281 #define REG_FIFOPAGE_INFO_1	0x0230
282 #define REG_FIFOPAGE_INFO_2	0x0234
283 #define REG_FIFOPAGE_INFO_3	0x0238
284 #define REG_FIFOPAGE_INFO_4	0x023C
285 #define REG_FIFOPAGE_INFO_5	0x0240
286 #define REG_H2C_HEAD		0x0244
287 #define REG_H2C_TAIL		0x0248
288 #define REG_H2C_READ_ADDR	0x024C
289 #define REG_H2C_INFO		0x0254
290 #define REG_RXDMA_AGG_PG_TH	0x0280
291 #define BIT_RXDMA_AGG_PG_TH	GENMASK(7, 0)
292 #define BIT_DMA_AGG_TO_V1	GENMASK(15, 8)
293 #define BIT_EN_PRE_CALC		BIT(29)
294 #define REG_RXPKT_NUM		0x0284
295 #define BIT_RXDMA_REQ		BIT(19)
296 #define BIT_RW_RELEASE		BIT(18)
297 #define BIT_RXDMA_IDLE		BIT(17)
298 #define REG_RXDMA_STATUS	0x0288
299 #define REG_RXDMA_DPR		0x028C
300 #define REG_RXDMA_MODE		0x0290
301 #define BIT_DMA_MODE		BIT(1)
302 #define REG_RXPKTNUM		0x02B0
303 
304 #define REG_INT_MIG		0x0304
305 #define REG_HCI_MIX_CFG		0x03FC
306 #define BIT_PCIE_EMAC_PDN_AUX_TO_FAST_CLK BIT(26)
307 
308 #define REG_BCNQ_INFO		0x0418
309 #define BIT_MGQ_CPU_EMPTY	BIT(24)
310 #define REG_FWHW_TXQ_CTRL	0x0420
311 #define BIT_EN_BCNQ_DL		BIT(22)
312 #define BIT_EN_WR_FREE_TAIL	BIT(20)
313 #define REG_HWSEQ_CTRL		0x0423
314 
315 #define REG_BCNQ_BDNY_V1	0x0424
316 #define REG_BCNQ_BDNY		0x0424
317 #define REG_MGQ_BDNY		0x0425
318 #define REG_LIFETIME_EN		0x0426
319 #define BIT_BA_PARSER_EN	BIT(5)
320 #define REG_SPEC_SIFS		0x0428
321 #define REG_RETRY_LIMIT		0x042a
322 #define REG_DARFRC		0x0430
323 #define REG_DARFRCH		0x0434
324 #define REG_RARFRCH		0x043C
325 #define REG_RRSR		0x0440
326 #define BITS_RRSR_RSC		GENMASK(22, 21)
327 #define REG_ARFR0		0x0444
328 #define REG_ARFRH0		0x0448
329 #define REG_ARFR1_V1		0x044C
330 #define REG_ARFRH1_V1		0x0450
331 #define REG_CCK_CHECK		0x0454
332 #define BIT_CHECK_CCK_EN	BIT(7)
333 #define REG_AMPDU_MAX_TIME_V1	0x0455
334 #define REG_BCNQ1_BDNY_V1	0x0456
335 #define REG_AMPDU_MAX_TIME	0x0456
336 #define REG_WMAC_LBK_BF_HD	0x045D
337 #define REG_TX_HANG_CTRL	0x045E
338 #define BIT_EN_GNT_BT_AWAKE	BIT(3)
339 #define BIT_EN_EOF_V1		BIT(2)
340 #define REG_DATA_SC		0x0483
341 #define REG_ARFR4		0x049C
342 #define BIT_WL_RFK		BIT(0)
343 #define REG_ARFRH4		0x04A0
344 #define REG_ARFR5		0x04A4
345 #define REG_ARFRH5		0x04A8
346 #define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC
347 #define BIT_PRE_TX_CMD		BIT(6)
348 #define REG_QUEUE_CTRL		0x04C6
349 #define BIT_PTA_WL_TX_EN	BIT(4)
350 #define BIT_PTA_EDCCA_EN	BIT(5)
351 #define REG_SINGLE_AMPDU_CTRL	0x04C7
352 #define BIT_EN_SINGLE_APMDU	BIT(7)
353 #define REG_PROT_MODE_CTRL	0x04C8
354 #define REG_MAX_AGGR_NUM	0x04CA
355 #define REG_BAR_MODE_CTRL	0x04CC
356 #define REG_PRECNT_CTRL		0x04E5
357 #define BIT_BTCCA_CTRL		(BIT(0) | BIT(1))
358 #define BIT_EN_PRECNT		BIT(11)
359 #define REG_DUMMY_PAGE4_V1	0x04FC
360 
361 #define REG_EDCA_VO_PARAM	0x0500
362 #define REG_EDCA_VI_PARAM	0x0504
363 #define REG_EDCA_BE_PARAM	0x0508
364 #define REG_EDCA_BK_PARAM	0x050C
365 #define BIT_MASK_TXOP_LMT	GENMASK(26, 16)
366 #define BIT_MASK_CWMAX		GENMASK(15, 12)
367 #define BIT_MASK_CWMIN		GENMASK(11, 8)
368 #define BIT_MASK_AIFS		GENMASK(7, 0)
369 #define REG_PIFS		0x0512
370 #define REG_SIFS		0x0514
371 #define BIT_SHIFT_SIFS_OFDM_CTX	8
372 #define BIT_SHIFT_SIFS_CCK_TRX	16
373 #define BIT_SHIFT_SIFS_OFDM_TRX	24
374 #define REG_AGGR_BREAK_TIME	0x051A
375 #define REG_SLOT		0x051B
376 #define REG_TX_PTCL_CTRL	0x0520
377 #define BIT_DIS_EDCCA		BIT(15)
378 #define BIT_SIFS_BK_EN		BIT(12)
379 #define REG_TXPAUSE		0x0522
380 #define BIT_AC_QUEUE		GENMASK(7, 0)
381 #define BIT_HIGH_QUEUE		BIT(5)
382 #define REG_RD_CTRL		0x0524
383 #define BIT_EDCCA_MSK_CNTDOWN_EN BIT(11)
384 #define BIT_DIS_TXOP_CFE	BIT(10)
385 #define BIT_DIS_LSIG_CFE	BIT(9)
386 #define BIT_DIS_STBC_CFE	BIT(8)
387 #define REG_TBTT_PROHIBIT	0x0540
388 #define BIT_SHIFT_TBTT_HOLD_TIME_AP 8
389 #define REG_RD_NAV_NXT		0x0544
390 #define REG_NAV_PROT_LEN	0x0546
391 #define REG_BCN_CTRL		0x0550
392 #define BIT_DIS_TSF_UDT		BIT(4)
393 #define BIT_EN_BCN_FUNCTION	BIT(3)
394 #define BIT_EN_TXBCN_RPT	BIT(2)
395 #define REG_BCN_CTRL_CLINT0	0x0551
396 #define REG_DRVERLYINT		0x0558
397 #define REG_BCNDMATIM		0x0559
398 #define REG_ATIMWND		0x055A
399 #define REG_USTIME_TSF		0x055C
400 #define REG_BCN_MAX_ERR		0x055D
401 #define REG_RXTSF_OFFSET_CCK	0x055E
402 #define REG_MISC_CTRL		0x0577
403 #define BIT_EN_FREE_CNT		BIT(3)
404 #define BIT_DIS_SECOND_CCA	(BIT(0) | BIT(1))
405 #define REG_HIQ_NO_LMT_EN	0x5A7
406 #define REG_DTIM_COUNTER_ROOT	0x5A8
407 #define BIT_HIQ_NO_LMT_EN_ROOT	BIT(0)
408 #define REG_TIMER0_SRC_SEL	0x05B4
409 #define BIT_TSFT_SEL_TIMER0	(BIT(4) | BIT(5) | BIT(6))
410 
411 #define REG_TCR			0x0604
412 #define BIT_PWRMGT_HWDATA_EN	BIT(7)
413 #define BIT_TCR_UPDATE_TIMIE	BIT(5)
414 #define BIT_TCR_UPDATE_HGQMD	BIT(4)
415 #define REG_RCR			0x0608
416 #define BIT_APP_FCS		BIT(31)
417 #define BIT_APP_MIC		BIT(30)
418 #define BIT_APP_ICV		BIT(29)
419 #define BIT_APP_PHYSTS		BIT(28)
420 #define BIT_APP_BASSN		BIT(27)
421 #define BIT_VHT_DACK		BIT(26)
422 #define BIT_TCPOFLD_EN		BIT(25)
423 #define BIT_ENMBID		BIT(24)
424 #define BIT_LSIGEN		BIT(23)
425 #define BIT_MFBEN		BIT(22)
426 #define BIT_DISCHKPPDLLEN	BIT(21)
427 #define BIT_PKTCTL_DLEN		BIT(20)
428 #define BIT_DISGCLK		BIT(19)
429 #define BIT_TIM_PARSER_EN	BIT(18)
430 #define BIT_BC_MD_EN		BIT(17)
431 #define BIT_UC_MD_EN		BIT(16)
432 #define BIT_RXSK_PERPKT		BIT(15)
433 #define BIT_HTC_LOC_CTRL	BIT(14)
434 #define BIT_RPFM_CAM_ENABLE	BIT(12)
435 #define BIT_TA_BCN		BIT(11)
436 #define BIT_RCR_ADF		BIT(11)
437 #define BIT_DISDECMYPKT		BIT(10)
438 #define BIT_AICV		BIT(9)
439 #define BIT_ACRC32		BIT(8)
440 #define BIT_CBSSID_BCN		BIT(7)
441 #define BIT_CBSSID_DATA		BIT(6)
442 #define BIT_APWRMGT		BIT(5)
443 #define BIT_ADD3		BIT(4)
444 #define BIT_AB			BIT(3)
445 #define BIT_AM			BIT(2)
446 #define BIT_APM			BIT(1)
447 #define BIT_AAP			BIT(0)
448 #define REG_RX_PKT_LIMIT	0x060C
449 #define REG_RX_DRVINFO_SZ	0x060F
450 #define BIT_APP_PHYSTS		BIT(28)
451 #define REG_MAR			0x0620
452 #define REG_USTIME_EDCA		0x0638
453 #define REG_ACKTO_CCK		0x0639
454 #define REG_MAC_SPEC_SIFS	0x063A
455 #define REG_RESP_SIFS_CCK	0x063C
456 #define REG_RESP_SIFS_OFDM	0x063E
457 #define REG_ACKTO		0x0640
458 #define REG_EIFS		0x0642
459 #define REG_NAV_CTRL		0x0650
460 #define REG_WMAC_TRXPTCL_CTL	0x0668
461 #define BIT_RFMOD		(BIT(7) | BIT(8))
462 #define BIT_RFMOD_80M		BIT(8)
463 #define BIT_RFMOD_40M		BIT(7)
464 #define REG_WMAC_TRXPTCL_CTL_H	0x066C
465 #define REG_WKFMCAM_CMD		0x0698
466 #define BIT_WKFCAM_POLLING_V1	BIT(31)
467 #define BIT_WKFCAM_CLR_V1	BIT(30)
468 #define BIT_WKFCAM_WE		BIT(16)
469 #define BIT_SHIFT_WKFCAM_ADDR_V2	8
470 #define BIT_MASK_WKFCAM_ADDR_V2		0xff
471 #define BIT_WKFCAM_ADDR_V2(x)						       \
472 	(((x) & BIT_MASK_WKFCAM_ADDR_V2) << BIT_SHIFT_WKFCAM_ADDR_V2)
473 #define REG_WKFMCAM_RWD         0x069C
474 #define BIT_WKFMCAM_VALID	BIT(31)
475 #define BIT_WKFMCAM_BC		BIT(26)
476 #define BIT_WKFMCAM_MC		BIT(25)
477 #define BIT_WKFMCAM_UC		BIT(24)
478 
479 #define REG_RXFLTMAP0		0x06A0
480 #define REG_RXFLTMAP1		0x06A2
481 #define REG_RXFLTMAP2		0x06A4
482 #define REG_RXFLTMAP4		0x068A
483 #define REG_BT_COEX_TABLE0	0x06C0
484 #define REG_BT_COEX_TABLE1	0x06C4
485 #define REG_BT_COEX_BRK_TABLE	0x06C8
486 #define REG_BT_COEX_TABLE_H	0x06CC
487 #define REG_BT_COEX_TABLE_H1	0x06CD
488 #define REG_BT_COEX_TABLE_H2	0x06CE
489 #define REG_BT_COEX_TABLE_H3	0x06CF
490 #define REG_BBPSF_CTRL		0x06DC
491 
492 #define REG_BT_COEX_V2		0x0762
493 #define BIT_GNT_BT_POLARITY	BIT(12)
494 #define BIT_LTE_COEX_EN		BIT(7)
495 #define REG_BT_COEX_ENH_INTR_CTRL	0x76E
496 #define BIT_R_GRANTALL_WLMASK	BIT(3)
497 #define BIT_STATIS_BT_EN	BIT(2)
498 #define REG_BT_ACT_STATISTICS	0x0770
499 #define REG_BT_ACT_STATISTICS_1	0x0774
500 #define REG_BT_STAT_CTRL	0x0778
501 #define REG_BT_TDMA_TIME	0x0790
502 #define BIT_MASK_SAMPLE_RATE	GENMASK(5, 0)
503 #define REG_LTR_IDLE_LATENCY	0x0798
504 #define REG_LTR_ACTIVE_LATENCY	0x079C
505 #define REG_LTR_CTRL_BASIC	0x07A4
506 #define REG_WMAC_OPTION_FUNCTION 0x07D0
507 #define REG_WMAC_OPTION_FUNCTION_1 0x07D4
508 
509 #define REG_FPGA0_RFMOD		0x0800
510 #define BIT_CCKEN		BIT(24)
511 #define BIT_OFDMEN		BIT(25)
512 #define REG_RX_GAIN_EN		0x081c
513 
514 #define REG_RFE_CTRL_E		0x0974
515 #define REG_2ND_CCA_CTRL	0x0976
516 
517 #define REG_CCK0_FAREPORT	0xa2c
518 #define BIT_CCK0_2RX		BIT(18)
519 #define BIT_CCK0_MRC		BIT(22)
520 
521 #define REG_DIS_DPD		0x0a70
522 #define DIS_DPD_MASK		GENMASK(9, 0)
523 #define DIS_DPD_RATE6M		BIT(0)
524 #define DIS_DPD_RATE9M		BIT(1)
525 #define DIS_DPD_RATEMCS0	BIT(2)
526 #define DIS_DPD_RATEMCS1	BIT(3)
527 #define DIS_DPD_RATEMCS8	BIT(4)
528 #define DIS_DPD_RATEMCS9	BIT(5)
529 #define DIS_DPD_RATEVHT1SS_MCS0	BIT(6)
530 #define DIS_DPD_RATEVHT1SS_MCS1	BIT(7)
531 #define DIS_DPD_RATEVHT2SS_MCS0	BIT(8)
532 #define DIS_DPD_RATEVHT2SS_MCS1	BIT(9)
533 #define DIS_DPD_RATEALL		GENMASK(9, 0)
534 
535 #define REG_RFE_CTRL8		0x0cb4
536 #define BIT_MASK_RFE_SEL89	GENMASK(7, 0)
537 #define REG_RFE_INV8		0x0cbd
538 #define BIT_MASK_RFE_INV89	GENMASK(1, 0)
539 #define REG_RFE_INV16		0x0cbe
540 #define BIT_RFE_BUF_EN		BIT(3)
541 
542 #define REG_ANAPAR_XTAL_0	0x1040
543 #define BIT_XCAP_0		GENMASK(23, 10)
544 #define REG_CPU_DMEM_CON	0x1080
545 #define BIT_WL_PLATFORM_RST	BIT(16)
546 #define BIT_WL_SECURITY_CLK	BIT(15)
547 #define BIT_DDMA_EN		BIT(8)
548 
549 #define REG_H2C_PKT_READADDR	0x10D0
550 #define REG_H2C_PKT_WRITEADDR	0x10D4
551 #define REG_FW_DBG7		0x10FC
552 #define FW_KEY_MASK		0xffffff00
553 
554 #define REG_CR_EXT		0x1100
555 
556 #define REG_DDMA_CH0SA		0x1200
557 #define REG_DDMA_CH0DA		0x1204
558 #define REG_DDMA_CH0CTRL	0x1208
559 #define BIT_DDMACH0_OWN		BIT(31)
560 #define BIT_DDMACH0_CHKSUM_EN	BIT(29)
561 #define BIT_DDMACH0_CHKSUM_STS	BIT(27)
562 #define BIT_DDMACH0_DDMA_MODE	BIT(26)
563 #define BIT_DDMACH0_RESET_CHKSUM_STS BIT(25)
564 #define BIT_DDMACH0_CHKSUM_CONT	BIT(24)
565 #define BIT_MASK_DDMACH0_DLEN	0x3ffff
566 
567 #define REG_H2CQ_CSR		0x1330
568 #define BIT_H2CQ_FULL		BIT(31)
569 #define REG_FAST_EDCA_VOVI_SETTING 0x1448
570 #define REG_FAST_EDCA_BEBK_SETTING 0x144C
571 
572 #define REG_RXPSF_CTRL		0x1610
573 #define BIT_RXGCK_FIFOTHR_EN	BIT(28)
574 
575 #define BIT_SHIFT_RXGCK_VHT_FIFOTHR 26
576 #define BIT_MASK_RXGCK_VHT_FIFOTHR 0x3
577 #define BIT_RXGCK_VHT_FIFOTHR(x)                                               \
578 	(((x) & BIT_MASK_RXGCK_VHT_FIFOTHR) << BIT_SHIFT_RXGCK_VHT_FIFOTHR)
579 #define BITS_RXGCK_VHT_FIFOTHR                                                 \
580 	(BIT_MASK_RXGCK_VHT_FIFOTHR << BIT_SHIFT_RXGCK_VHT_FIFOTHR)
581 
582 #define BIT_SHIFT_RXGCK_HT_FIFOTHR 24
583 #define BIT_MASK_RXGCK_HT_FIFOTHR 0x3
584 #define BIT_RXGCK_HT_FIFOTHR(x)                                                \
585 	(((x) & BIT_MASK_RXGCK_HT_FIFOTHR) << BIT_SHIFT_RXGCK_HT_FIFOTHR)
586 #define BITS_RXGCK_HT_FIFOTHR                                                  \
587 	(BIT_MASK_RXGCK_HT_FIFOTHR << BIT_SHIFT_RXGCK_HT_FIFOTHR)
588 
589 #define BIT_SHIFT_RXGCK_OFDM_FIFOTHR 22
590 #define BIT_MASK_RXGCK_OFDM_FIFOTHR 0x3
591 #define BIT_RXGCK_OFDM_FIFOTHR(x)                                              \
592 	(((x) & BIT_MASK_RXGCK_OFDM_FIFOTHR) << BIT_SHIFT_RXGCK_OFDM_FIFOTHR)
593 #define BITS_RXGCK_OFDM_FIFOTHR                                                \
594 	(BIT_MASK_RXGCK_OFDM_FIFOTHR << BIT_SHIFT_RXGCK_OFDM_FIFOTHR)
595 
596 #define BIT_SHIFT_RXGCK_CCK_FIFOTHR 20
597 #define BIT_MASK_RXGCK_CCK_FIFOTHR 0x3
598 #define BIT_RXGCK_CCK_FIFOTHR(x)                                               \
599 	(((x) & BIT_MASK_RXGCK_CCK_FIFOTHR) << BIT_SHIFT_RXGCK_CCK_FIFOTHR)
600 #define BITS_RXGCK_CCK_FIFOTHR                                                 \
601 	(BIT_MASK_RXGCK_CCK_FIFOTHR << BIT_SHIFT_RXGCK_CCK_FIFOTHR)
602 
603 #define BIT_RXGCK_OFDMCCA_EN BIT(16)
604 
605 #define BIT_SHIFT_RXPSF_PKTLENTHR 13
606 #define BIT_MASK_RXPSF_PKTLENTHR 0x7
607 #define BIT_RXPSF_PKTLENTHR(x)                                                 \
608 	(((x) & BIT_MASK_RXPSF_PKTLENTHR) << BIT_SHIFT_RXPSF_PKTLENTHR)
609 #define BITS_RXPSF_PKTLENTHR                                                   \
610 	(BIT_MASK_RXPSF_PKTLENTHR << BIT_SHIFT_RXPSF_PKTLENTHR)
611 #define BIT_CLEAR_RXPSF_PKTLENTHR(x) ((x) & (~BITS_RXPSF_PKTLENTHR))
612 #define BIT_SET_RXPSF_PKTLENTHR(x, v)                                          \
613 	(BIT_CLEAR_RXPSF_PKTLENTHR(x) | BIT_RXPSF_PKTLENTHR(v))
614 
615 #define BIT_RXPSF_CTRLEN	BIT(12)
616 #define BIT_RXPSF_VHTCHKEN	BIT(11)
617 #define BIT_RXPSF_HTCHKEN	BIT(10)
618 #define BIT_RXPSF_OFDMCHKEN	BIT(9)
619 #define BIT_RXPSF_CCKCHKEN	BIT(8)
620 #define BIT_RXPSF_OFDMRST	BIT(7)
621 #define BIT_RXPSF_CCKRST	BIT(6)
622 #define BIT_RXPSF_MHCHKEN	BIT(5)
623 #define BIT_RXPSF_CONT_ERRCHKEN	BIT(4)
624 #define BIT_RXPSF_ALL_ERRCHKEN	BIT(3)
625 
626 #define BIT_SHIFT_RXPSF_ERRTHR 0
627 #define BIT_MASK_RXPSF_ERRTHR 0x7
628 #define BIT_RXPSF_ERRTHR(x)                                                    \
629 	(((x) & BIT_MASK_RXPSF_ERRTHR) << BIT_SHIFT_RXPSF_ERRTHR)
630 #define BITS_RXPSF_ERRTHR (BIT_MASK_RXPSF_ERRTHR << BIT_SHIFT_RXPSF_ERRTHR)
631 #define BIT_CLEAR_RXPSF_ERRTHR(x) ((x) & (~BITS_RXPSF_ERRTHR))
632 #define BIT_GET_RXPSF_ERRTHR(x)                                                \
633 	(((x) >> BIT_SHIFT_RXPSF_ERRTHR) & BIT_MASK_RXPSF_ERRTHR)
634 #define BIT_SET_RXPSF_ERRTHR(x, v)                                             \
635 	(BIT_CLEAR_RXPSF_ERRTHR(x) | BIT_RXPSF_ERRTHR(v))
636 
637 #define REG_RXPSF_TYPE_CTRL	0x1614
638 #define REG_GENERAL_OPTION	0x1664
639 #define BIT_DUMMY_FCS_READY_MASK_EN BIT(9)
640 
641 #define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1		0x1700
642 #define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1	0x1704
643 #define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1	0x1708
644 #define LTECOEX_READY		BIT(29)
645 #define LTECOEX_ACCESS_CTRL REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1
646 #define LTECOEX_WRITE_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1
647 #define LTECOEX_READ_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1
648 
649 #define REG_IGN_GNT_BT1	0x1860
650 
651 #define REG_RFESEL_CTRL	0x1990
652 
653 #define REG_NOMASK_TXBT	0x1ca7
654 #define REG_ANAPAR	0x1c30
655 #define BIT_ANAPAR_BTPS	BIT(22)
656 #define REG_RSTB_SEL	0x1c38
657 #define BIT_DAC_OFF_ENABLE	BIT(4)
658 #define BIT_PI_IGNORE_GNT_BT	BIT(3)
659 #define BIT_NOMASK_TXBT_ENABLE	BIT(3)
660 
661 #define REG_HRCV_MSG	0x1cf
662 
663 #define REG_EDCCA_REPORT	0x2d38
664 #define BIT_EDCCA_FLAG		BIT(24)
665 
666 #define REG_IGN_GNTBT4	0x4160
667 
668 #define RF_MODE		0x00
669 #define RF_MODOPT	0x01
670 #define RF_WLINT	0x01
671 #define RF_WLSEL	0x02
672 #define RF_DTXLOK	0x08
673 #define RF_CFGCH	0x18
674 #define BIT_BAND	GENMASK(18, 16)
675 #define RF_RCK		0x1d
676 #define RF_LUTWA	0x33
677 #define RF_LUTWD1	0x3e
678 #define RF_LUTWD0	0x3f
679 #define BIT_GAIN_EXT	BIT(12)
680 #define BIT_DATA_L	GENMASK(11, 0)
681 #define RF_T_METER	0x42
682 #define RF_BSPAD	0x54
683 #define RF_GAINTX	0x56
684 #define RF_TXATANK	0x64
685 #define RF_TRXIQ	0x66
686 #define RF_RXIQGEN	0x8d
687 #define RF_SYN_PFD	0xb0
688 #define RF_XTALX2	0xb8
689 #define RF_SYN_CTRL	0xbb
690 #define RF_MALSEL	0xbe
691 #define RF_SYN_AAC	0xc9
692 #define RF_AAC_CTRL	0xca
693 #define RF_FAST_LCK	0xcc
694 #define RF_RCKD		0xde
695 #define RF_TXADBG	0xde
696 #define RF_LUTDBG	0xdf
697 #define BIT_TXA_TANK	BIT(4)
698 #define RF_LUTWE2	0xee
699 #define RF_LUTWE	0xef
700 
701 #define LTE_COEX_CTRL	0x38
702 #define LTE_WL_TRX_CTRL	0xa0
703 #define LTE_BT_TRX_CTRL	0xa4
704 
705 #endif
706