| /openbmc/qemu/target/arm/ |
| H A D | cpu.h | 837 struct ArchCPU { struct
838 CPUState parent_obj;
840 CPUARMState env;
843 GHashTable *cp_regs;
851 uint64_t *cpreg_indexes;
853 uint64_t *cpreg_values;
855 int32_t cpreg_array_len;
860 uint64_t *cpreg_vmstate_indexes;
861 uint64_t *cpreg_vmstate_values;
862 int32_t cpreg_vmstate_array_len;
[all …]
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| /openbmc/qemu/target/hexagon/ |
| H A D | cpu.h | 123 struct ArchCPU { struct
124 CPUState parent_obj;
126 CPUHexagonState env;
128 bool lldb_compat;
129 target_ulong lldb_stack_adjust;
130 bool short_circuit;
156 typedef HexagonCPU ArchCPU; typedef
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| /openbmc/qemu/target/i386/ |
| H A D | cpu.h | 2069 struct ArchCPU { struct
2070 CPUState parent_obj;
2072 CPUX86State env;
2073 VMChangeStateEntry *vmsentry;
2075 uint64_t ucode_rev;
2077 uint32_t hyperv_spinlock_attempts;
2078 char *hyperv_vendor;
2079 bool hyperv_synic_kvm_only;
2080 uint64_t hyperv_features;
2081 bool hyperv_passthrough;
[all …]
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| /openbmc/qemu/target/avr/ |
| H A D | cpu.h | 142 struct ArchCPU { struct
143 CPUState parent_obj;
145 CPUAVRState env;
148 uint32_t init_sp;
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| /openbmc/qemu/target/loongarch/ |
| H A D | cpu.h | 399 struct ArchCPU { struct
415 * LoongArchCPUClass: argument
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| /openbmc/qemu/target/microblaze/ |
| H A D | cpu.h | 342 struct ArchCPU { struct
343 CPUState parent_obj;
345 CPUMBState env;
347 bool ns_axi_dp;
348 bool ns_axi_ip;
349 bool ns_axi_dc;
350 bool ns_axi_ic;
352 MicroBlazeCPUConfig cfg;
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| /openbmc/qemu/target/rx/ |
| H A D | cpu.h | 109 struct ArchCPU { struct
110 CPUState parent_obj;
112 CPURXState env;
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| /openbmc/qemu/target/riscv/ |
| H A D | cpu.h | 497 struct ArchCPU { struct
498 CPUState parent_obj;
500 CPURISCVState env;
502 GDBFeature dyn_csr_feature;
503 GDBFeature dyn_vreg_feature;
506 RISCVCPUConfig cfg;
508 QEMUTimer *pmu_timer;
510 uint32_t pmu_avail_ctrs;
512 GHashTable *pmu_event_ctr_map;
513 const GPtrArray *decoders;
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| /openbmc/qemu/target/tricore/ |
| H A D | cpu.h | 65 struct ArchCPU { struct
66 CPUState parent_obj;
68 CPUTriCoreState env;
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| /openbmc/qemu/target/hppa/ |
| H A D | cpu.h | 274 struct ArchCPU { struct
275 CPUState parent_obj;
277 CPUHPPAState env;
278 QEMUTimer *alarm_timer;
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| /openbmc/qemu/target/alpha/ |
| H A D | cpu.h | 258 struct ArchCPU { struct
259 CPUState parent_obj;
261 CPUAlphaState env;
264 QEMUTimer *alarm_timer;
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| /openbmc/qemu/target/openrisc/ |
| H A D | cpu.h | 294 struct ArchCPU { struct
295 CPUState parent_obj;
297 CPUOpenRISCState env;
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| /openbmc/qemu/target/sh4/ |
| H A D | cpu.h | 216 struct ArchCPU { struct
217 CPUState parent_obj;
219 CPUSH4State env;
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| /openbmc/qemu/target/s390x/ |
| H A D | cpu.h | 170 struct ArchCPU { struct
171 CPUState parent_obj;
173 CPUS390XState env;
174 S390CPUModel *model;
176 void *irqstate;
177 uint32_t irqstate_saved_size;
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| /openbmc/qemu/include/qemu/ |
| H A D | typedefs.h | 29 typedef struct ArchCPU ArchCPU; typedef
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| /openbmc/qemu/target/m68k/ |
| H A D | cpu.h | 166 struct ArchCPU { struct
167 CPUState parent_obj;
169 CPUM68KState env;
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| /openbmc/qemu/target/xtensa/ |
| H A D | cpu.h | 558 struct ArchCPU { struct
559 CPUState parent_obj;
561 CPUXtensaState env;
562 Clock *clock;
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| /openbmc/qemu/target/mips/ |
| H A D | cpu.h | 1204 struct ArchCPU { struct
1205 CPUState parent_obj;
1207 CPUMIPSState env;
1209 Clock *clock;
1210 Clock *count_div; /* Divider for CP0_Count clock */
1213 bool is_big_endian;
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| /openbmc/qemu/target/ppc/ |
| H A D | cpu.h | 1448 struct ArchCPU { struct
1449 CPUState parent_obj;
1451 CPUPPCState env;
1453 int vcpu_id;
1454 uint32_t compat_pvr;
1455 PPCVirtualHypervisor *vhyp;
1456 PPCVirtualHypervisorClass *vhyp_class;
1457 void *machine_data;
1458 int32_t node_id; /* NUMA node this CPU belongs to */
1459 PPCHash64Options *hash64_opts;
[all …]
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| /openbmc/qemu/target/sparc/ |
| H A D | cpu.h | 559 struct ArchCPU { struct
560 CPUState parent_obj;
562 CPUSPARCState env;
|