xref: /openbmc/linux/drivers/spi/spi-au1550.c (revision 0c35cc59)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * au1550 psc spi controller driver
4  * may work also with au1200, au1210, au1250
5  * will not work on au1000, au1100 and au1500 (no full spi controller there)
6  *
7  * Copyright (c) 2006 ATRON electronic GmbH
8  * Author: Jan Nikitenko <jan.nikitenko@gmail.com>
9  */
10 
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/slab.h>
14 #include <linux/errno.h>
15 #include <linux/module.h>
16 #include <linux/device.h>
17 #include <linux/platform_device.h>
18 #include <linux/resource.h>
19 #include <linux/spi/spi.h>
20 #include <linux/spi/spi_bitbang.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/completion.h>
23 #include <asm/mach-au1x00/au1000.h>
24 #include <asm/mach-au1x00/au1xxx_psc.h>
25 #include <asm/mach-au1x00/au1xxx_dbdma.h>
26 
27 #include <asm/mach-au1x00/au1550_spi.h>
28 
29 static unsigned int usedma = 1;
30 module_param(usedma, uint, 0644);
31 
32 /*
33 #define AU1550_SPI_DEBUG_LOOPBACK
34 */
35 
36 
37 #define AU1550_SPI_DBDMA_DESCRIPTORS 1
38 #define AU1550_SPI_DMA_RXTMP_MINSIZE 2048U
39 
40 struct au1550_spi {
41 	struct spi_bitbang bitbang;
42 
43 	volatile psc_spi_t __iomem *regs;
44 	int irq;
45 
46 	unsigned int len;
47 	unsigned int tx_count;
48 	unsigned int rx_count;
49 	const u8 *tx;
50 	u8 *rx;
51 
52 	void (*rx_word)(struct au1550_spi *hw);
53 	void (*tx_word)(struct au1550_spi *hw);
54 	int (*txrx_bufs)(struct spi_device *spi, struct spi_transfer *t);
55 	irqreturn_t (*irq_callback)(struct au1550_spi *hw);
56 
57 	struct completion host_done;
58 
59 	unsigned int usedma;
60 	u32 dma_tx_id;
61 	u32 dma_rx_id;
62 	u32 dma_tx_ch;
63 	u32 dma_rx_ch;
64 
65 	u8 *dma_rx_tmpbuf;
66 	unsigned int dma_rx_tmpbuf_size;
67 	u32 dma_rx_tmpbuf_addr;
68 
69 	struct spi_controller *host;
70 	struct device *dev;
71 	struct au1550_spi_info *pdata;
72 	struct resource *ioarea;
73 };
74 
75 
76 /* we use an 8-bit memory device for dma transfers to/from spi fifo */
77 static dbdev_tab_t au1550_spi_mem_dbdev = {
78 	.dev_id			= DBDMA_MEM_CHAN,
79 	.dev_flags		= DEV_FLAGS_ANYUSE|DEV_FLAGS_SYNC,
80 	.dev_tsize		= 0,
81 	.dev_devwidth		= 8,
82 	.dev_physaddr		= 0x00000000,
83 	.dev_intlevel		= 0,
84 	.dev_intpolarity	= 0
85 };
86 
87 static int ddma_memid;	/* id to above mem dma device */
88 
89 static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw);
90 
91 
92 /*
93  *  compute BRG and DIV bits to setup spi clock based on main input clock rate
94  *  that was specified in platform data structure
95  *  according to au1550 datasheet:
96  *    psc_tempclk = psc_mainclk / (2 << DIV)
97  *    spiclk = psc_tempclk / (2 * (BRG + 1))
98  *    BRG valid range is 4..63
99  *    DIV valid range is 0..3
100  */
au1550_spi_baudcfg(struct au1550_spi * hw,unsigned int speed_hz)101 static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned int speed_hz)
102 {
103 	u32 mainclk_hz = hw->pdata->mainclk_hz;
104 	u32 div, brg;
105 
106 	for (div = 0; div < 4; div++) {
107 		brg = mainclk_hz / speed_hz / (4 << div);
108 		/* now we have BRG+1 in brg, so count with that */
109 		if (brg < (4 + 1)) {
110 			brg = (4 + 1);	/* speed_hz too big */
111 			break;		/* set lowest brg (div is == 0) */
112 		}
113 		if (brg <= (63 + 1))
114 			break;		/* we have valid brg and div */
115 	}
116 	if (div == 4) {
117 		div = 3;		/* speed_hz too small */
118 		brg = (63 + 1);		/* set highest brg and div */
119 	}
120 	brg--;
121 	return PSC_SPICFG_SET_BAUD(brg) | PSC_SPICFG_SET_DIV(div);
122 }
123 
au1550_spi_mask_ack_all(struct au1550_spi * hw)124 static inline void au1550_spi_mask_ack_all(struct au1550_spi *hw)
125 {
126 	hw->regs->psc_spimsk =
127 		  PSC_SPIMSK_MM | PSC_SPIMSK_RR | PSC_SPIMSK_RO
128 		| PSC_SPIMSK_RU | PSC_SPIMSK_TR | PSC_SPIMSK_TO
129 		| PSC_SPIMSK_TU | PSC_SPIMSK_SD | PSC_SPIMSK_MD;
130 	wmb(); /* drain writebuffer */
131 
132 	hw->regs->psc_spievent =
133 		  PSC_SPIEVNT_MM | PSC_SPIEVNT_RR | PSC_SPIEVNT_RO
134 		| PSC_SPIEVNT_RU | PSC_SPIEVNT_TR | PSC_SPIEVNT_TO
135 		| PSC_SPIEVNT_TU | PSC_SPIEVNT_SD | PSC_SPIEVNT_MD;
136 	wmb(); /* drain writebuffer */
137 }
138 
au1550_spi_reset_fifos(struct au1550_spi * hw)139 static void au1550_spi_reset_fifos(struct au1550_spi *hw)
140 {
141 	u32 pcr;
142 
143 	hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC;
144 	wmb(); /* drain writebuffer */
145 	do {
146 		pcr = hw->regs->psc_spipcr;
147 		wmb(); /* drain writebuffer */
148 	} while (pcr != 0);
149 }
150 
151 /*
152  * dma transfers are used for the most common spi word size of 8-bits
153  * we cannot easily change already set up dma channels' width, so if we wanted
154  * dma support for more than 8-bit words (up to 24 bits), we would need to
155  * setup dma channels from scratch on each spi transfer, based on bits_per_word
156  * instead we have pre set up 8 bit dma channels supporting spi 4 to 8 bits
157  * transfers, and 9 to 24 bits spi transfers will be done in pio irq based mode
158  * callbacks to handle dma or pio are set up in au1550_spi_bits_handlers_set()
159  */
au1550_spi_chipsel(struct spi_device * spi,int value)160 static void au1550_spi_chipsel(struct spi_device *spi, int value)
161 {
162 	struct au1550_spi *hw = spi_controller_get_devdata(spi->controller);
163 	unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
164 	u32 cfg, stat;
165 
166 	switch (value) {
167 	case BITBANG_CS_INACTIVE:
168 		if (hw->pdata->deactivate_cs)
169 			hw->pdata->deactivate_cs(hw->pdata, spi_get_chipselect(spi, 0),
170 					cspol);
171 		break;
172 
173 	case BITBANG_CS_ACTIVE:
174 		au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
175 
176 		cfg = hw->regs->psc_spicfg;
177 		wmb(); /* drain writebuffer */
178 		hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
179 		wmb(); /* drain writebuffer */
180 
181 		if (spi->mode & SPI_CPOL)
182 			cfg |= PSC_SPICFG_BI;
183 		else
184 			cfg &= ~PSC_SPICFG_BI;
185 		if (spi->mode & SPI_CPHA)
186 			cfg &= ~PSC_SPICFG_CDE;
187 		else
188 			cfg |= PSC_SPICFG_CDE;
189 
190 		if (spi->mode & SPI_LSB_FIRST)
191 			cfg |= PSC_SPICFG_MLF;
192 		else
193 			cfg &= ~PSC_SPICFG_MLF;
194 
195 		if (hw->usedma && spi->bits_per_word <= 8)
196 			cfg &= ~PSC_SPICFG_DD_DISABLE;
197 		else
198 			cfg |= PSC_SPICFG_DD_DISABLE;
199 		cfg = PSC_SPICFG_CLR_LEN(cfg);
200 		cfg |= PSC_SPICFG_SET_LEN(spi->bits_per_word);
201 
202 		cfg = PSC_SPICFG_CLR_BAUD(cfg);
203 		cfg &= ~PSC_SPICFG_SET_DIV(3);
204 		cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz);
205 
206 		hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE;
207 		wmb(); /* drain writebuffer */
208 		do {
209 			stat = hw->regs->psc_spistat;
210 			wmb(); /* drain writebuffer */
211 		} while ((stat & PSC_SPISTAT_DR) == 0);
212 
213 		if (hw->pdata->activate_cs)
214 			hw->pdata->activate_cs(hw->pdata, spi_get_chipselect(spi, 0),
215 					cspol);
216 		break;
217 	}
218 }
219 
au1550_spi_setupxfer(struct spi_device * spi,struct spi_transfer * t)220 static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
221 {
222 	struct au1550_spi *hw = spi_controller_get_devdata(spi->controller);
223 	unsigned int bpw, hz;
224 	u32 cfg, stat;
225 
226 	if (t) {
227 		bpw = t->bits_per_word;
228 		hz = t->speed_hz;
229 	} else {
230 		bpw = spi->bits_per_word;
231 		hz = spi->max_speed_hz;
232 	}
233 
234 	if (!hz)
235 		return -EINVAL;
236 
237 	au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
238 
239 	cfg = hw->regs->psc_spicfg;
240 	wmb(); /* drain writebuffer */
241 	hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
242 	wmb(); /* drain writebuffer */
243 
244 	if (hw->usedma && bpw <= 8)
245 		cfg &= ~PSC_SPICFG_DD_DISABLE;
246 	else
247 		cfg |= PSC_SPICFG_DD_DISABLE;
248 	cfg = PSC_SPICFG_CLR_LEN(cfg);
249 	cfg |= PSC_SPICFG_SET_LEN(bpw);
250 
251 	cfg = PSC_SPICFG_CLR_BAUD(cfg);
252 	cfg &= ~PSC_SPICFG_SET_DIV(3);
253 	cfg |= au1550_spi_baudcfg(hw, hz);
254 
255 	hw->regs->psc_spicfg = cfg;
256 	wmb(); /* drain writebuffer */
257 
258 	if (cfg & PSC_SPICFG_DE_ENABLE) {
259 		do {
260 			stat = hw->regs->psc_spistat;
261 			wmb(); /* drain writebuffer */
262 		} while ((stat & PSC_SPISTAT_DR) == 0);
263 	}
264 
265 	au1550_spi_reset_fifos(hw);
266 	au1550_spi_mask_ack_all(hw);
267 	return 0;
268 }
269 
270 /*
271  * for dma spi transfers, we have to setup rx channel, otherwise there is
272  * no reliable way how to recognize that spi transfer is done
273  * dma complete callbacks are called before real spi transfer is finished
274  * and if only tx dma channel is set up (and rx fifo overflow event masked)
275  * spi host done event irq is not generated unless rx fifo is empty (emptied)
276  * so we need rx tmp buffer to use for rx dma if user does not provide one
277  */
au1550_spi_dma_rxtmp_alloc(struct au1550_spi * hw,unsigned int size)278 static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned int size)
279 {
280 	hw->dma_rx_tmpbuf = kmalloc(size, GFP_KERNEL);
281 	if (!hw->dma_rx_tmpbuf)
282 		return -ENOMEM;
283 	hw->dma_rx_tmpbuf_size = size;
284 	hw->dma_rx_tmpbuf_addr = dma_map_single(hw->dev, hw->dma_rx_tmpbuf,
285 			size, DMA_FROM_DEVICE);
286 	if (dma_mapping_error(hw->dev, hw->dma_rx_tmpbuf_addr)) {
287 		kfree(hw->dma_rx_tmpbuf);
288 		hw->dma_rx_tmpbuf = 0;
289 		hw->dma_rx_tmpbuf_size = 0;
290 		return -EFAULT;
291 	}
292 	return 0;
293 }
294 
au1550_spi_dma_rxtmp_free(struct au1550_spi * hw)295 static void au1550_spi_dma_rxtmp_free(struct au1550_spi *hw)
296 {
297 	dma_unmap_single(hw->dev, hw->dma_rx_tmpbuf_addr,
298 			hw->dma_rx_tmpbuf_size, DMA_FROM_DEVICE);
299 	kfree(hw->dma_rx_tmpbuf);
300 	hw->dma_rx_tmpbuf = 0;
301 	hw->dma_rx_tmpbuf_size = 0;
302 }
303 
au1550_spi_dma_txrxb(struct spi_device * spi,struct spi_transfer * t)304 static int au1550_spi_dma_txrxb(struct spi_device *spi, struct spi_transfer *t)
305 {
306 	struct au1550_spi *hw = spi_controller_get_devdata(spi->controller);
307 	dma_addr_t dma_tx_addr;
308 	dma_addr_t dma_rx_addr;
309 	u32 res;
310 
311 	hw->len = t->len;
312 	hw->tx_count = 0;
313 	hw->rx_count = 0;
314 
315 	hw->tx = t->tx_buf;
316 	hw->rx = t->rx_buf;
317 	dma_tx_addr = t->tx_dma;
318 	dma_rx_addr = t->rx_dma;
319 
320 	/*
321 	 * check if buffers are already dma mapped, map them otherwise:
322 	 * - first map the TX buffer, so cache data gets written to memory
323 	 * - then map the RX buffer, so that cache entries (with
324 	 *   soon-to-be-stale data) get removed
325 	 * use rx buffer in place of tx if tx buffer was not provided
326 	 * use temp rx buffer (preallocated or realloc to fit) for rx dma
327 	 */
328 	if (t->tx_buf) {
329 		if (t->tx_dma == 0) {	/* if DMA_ADDR_INVALID, map it */
330 			dma_tx_addr = dma_map_single(hw->dev,
331 					(void *)t->tx_buf,
332 					t->len, DMA_TO_DEVICE);
333 			if (dma_mapping_error(hw->dev, dma_tx_addr))
334 				dev_err(hw->dev, "tx dma map error\n");
335 		}
336 	}
337 
338 	if (t->rx_buf) {
339 		if (t->rx_dma == 0) {	/* if DMA_ADDR_INVALID, map it */
340 			dma_rx_addr = dma_map_single(hw->dev,
341 					(void *)t->rx_buf,
342 					t->len, DMA_FROM_DEVICE);
343 			if (dma_mapping_error(hw->dev, dma_rx_addr))
344 				dev_err(hw->dev, "rx dma map error\n");
345 		}
346 	} else {
347 		if (t->len > hw->dma_rx_tmpbuf_size) {
348 			int ret;
349 
350 			au1550_spi_dma_rxtmp_free(hw);
351 			ret = au1550_spi_dma_rxtmp_alloc(hw, max(t->len,
352 					AU1550_SPI_DMA_RXTMP_MINSIZE));
353 			if (ret < 0)
354 				return ret;
355 		}
356 		hw->rx = hw->dma_rx_tmpbuf;
357 		dma_rx_addr = hw->dma_rx_tmpbuf_addr;
358 		dma_sync_single_for_device(hw->dev, dma_rx_addr,
359 			t->len, DMA_FROM_DEVICE);
360 	}
361 
362 	if (!t->tx_buf) {
363 		dma_sync_single_for_device(hw->dev, dma_rx_addr,
364 				t->len, DMA_BIDIRECTIONAL);
365 		hw->tx = hw->rx;
366 	}
367 
368 	/* put buffers on the ring */
369 	res = au1xxx_dbdma_put_dest(hw->dma_rx_ch, virt_to_phys(hw->rx),
370 				    t->len, DDMA_FLAGS_IE);
371 	if (!res)
372 		dev_err(hw->dev, "rx dma put dest error\n");
373 
374 	res = au1xxx_dbdma_put_source(hw->dma_tx_ch, virt_to_phys(hw->tx),
375 				      t->len, DDMA_FLAGS_IE);
376 	if (!res)
377 		dev_err(hw->dev, "tx dma put source error\n");
378 
379 	au1xxx_dbdma_start(hw->dma_rx_ch);
380 	au1xxx_dbdma_start(hw->dma_tx_ch);
381 
382 	/* by default enable nearly all events interrupt */
383 	hw->regs->psc_spimsk = PSC_SPIMSK_SD;
384 	wmb(); /* drain writebuffer */
385 
386 	/* start the transfer */
387 	hw->regs->psc_spipcr = PSC_SPIPCR_MS;
388 	wmb(); /* drain writebuffer */
389 
390 	wait_for_completion(&hw->host_done);
391 
392 	au1xxx_dbdma_stop(hw->dma_tx_ch);
393 	au1xxx_dbdma_stop(hw->dma_rx_ch);
394 
395 	if (!t->rx_buf) {
396 		/* using the temporal preallocated and premapped buffer */
397 		dma_sync_single_for_cpu(hw->dev, dma_rx_addr, t->len,
398 			DMA_FROM_DEVICE);
399 	}
400 	/* unmap buffers if mapped above */
401 	if (t->rx_buf && t->rx_dma == 0)
402 		dma_unmap_single(hw->dev, dma_rx_addr, t->len,
403 			DMA_FROM_DEVICE);
404 	if (t->tx_buf && t->tx_dma == 0)
405 		dma_unmap_single(hw->dev, dma_tx_addr, t->len,
406 			DMA_TO_DEVICE);
407 
408 	return min(hw->rx_count, hw->tx_count);
409 }
410 
au1550_spi_dma_irq_callback(struct au1550_spi * hw)411 static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw)
412 {
413 	u32 stat, evnt;
414 
415 	stat = hw->regs->psc_spistat;
416 	evnt = hw->regs->psc_spievent;
417 	wmb(); /* drain writebuffer */
418 	if ((stat & PSC_SPISTAT_DI) == 0) {
419 		dev_err(hw->dev, "Unexpected IRQ!\n");
420 		return IRQ_NONE;
421 	}
422 
423 	if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
424 				| PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
425 				| PSC_SPIEVNT_TU | PSC_SPIEVNT_SD))
426 			!= 0) {
427 		/*
428 		 * due to an spi error we consider transfer as done,
429 		 * so mask all events until before next transfer start
430 		 * and stop the possibly running dma immediately
431 		 */
432 		au1550_spi_mask_ack_all(hw);
433 		au1xxx_dbdma_stop(hw->dma_rx_ch);
434 		au1xxx_dbdma_stop(hw->dma_tx_ch);
435 
436 		/* get number of transferred bytes */
437 		hw->rx_count = hw->len - au1xxx_get_dma_residue(hw->dma_rx_ch);
438 		hw->tx_count = hw->len - au1xxx_get_dma_residue(hw->dma_tx_ch);
439 
440 		au1xxx_dbdma_reset(hw->dma_rx_ch);
441 		au1xxx_dbdma_reset(hw->dma_tx_ch);
442 		au1550_spi_reset_fifos(hw);
443 
444 		if (evnt == PSC_SPIEVNT_RO)
445 			dev_err(hw->dev,
446 				"dma transfer: receive FIFO overflow!\n");
447 		else
448 			dev_err(hw->dev,
449 				"dma transfer: unexpected SPI error (event=0x%x stat=0x%x)!\n",
450 				evnt, stat);
451 
452 		complete(&hw->host_done);
453 		return IRQ_HANDLED;
454 	}
455 
456 	if ((evnt & PSC_SPIEVNT_MD) != 0) {
457 		/* transfer completed successfully */
458 		au1550_spi_mask_ack_all(hw);
459 		hw->rx_count = hw->len;
460 		hw->tx_count = hw->len;
461 		complete(&hw->host_done);
462 	}
463 	return IRQ_HANDLED;
464 }
465 
466 
467 /* routines to handle different word sizes in pio mode */
468 #define AU1550_SPI_RX_WORD(size, mask)					\
469 static void au1550_spi_rx_word_##size(struct au1550_spi *hw)		\
470 {									\
471 	u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask);		\
472 	wmb(); /* drain writebuffer */					\
473 	if (hw->rx) {							\
474 		*(u##size *)hw->rx = (u##size)fifoword;			\
475 		hw->rx += (size) / 8;					\
476 	}								\
477 	hw->rx_count += (size) / 8;					\
478 }
479 
480 #define AU1550_SPI_TX_WORD(size, mask)					\
481 static void au1550_spi_tx_word_##size(struct au1550_spi *hw)		\
482 {									\
483 	u32 fifoword = 0;						\
484 	if (hw->tx) {							\
485 		fifoword = *(u##size *)hw->tx & (u32)(mask);		\
486 		hw->tx += (size) / 8;					\
487 	}								\
488 	hw->tx_count += (size) / 8;					\
489 	if (hw->tx_count >= hw->len)					\
490 		fifoword |= PSC_SPITXRX_LC;				\
491 	hw->regs->psc_spitxrx = fifoword;				\
492 	wmb(); /* drain writebuffer */					\
493 }
494 
495 AU1550_SPI_RX_WORD(8, 0xff)
496 AU1550_SPI_RX_WORD(16, 0xffff)
497 AU1550_SPI_RX_WORD(32, 0xffffff)
498 AU1550_SPI_TX_WORD(8, 0xff)
499 AU1550_SPI_TX_WORD(16, 0xffff)
500 AU1550_SPI_TX_WORD(32, 0xffffff)
501 
au1550_spi_pio_txrxb(struct spi_device * spi,struct spi_transfer * t)502 static int au1550_spi_pio_txrxb(struct spi_device *spi, struct spi_transfer *t)
503 {
504 	u32 stat, mask;
505 	struct au1550_spi *hw = spi_controller_get_devdata(spi->controller);
506 
507 	hw->tx = t->tx_buf;
508 	hw->rx = t->rx_buf;
509 	hw->len = t->len;
510 	hw->tx_count = 0;
511 	hw->rx_count = 0;
512 
513 	/* by default enable nearly all events after filling tx fifo */
514 	mask = PSC_SPIMSK_SD;
515 
516 	/* fill the transmit FIFO */
517 	while (hw->tx_count < hw->len) {
518 
519 		hw->tx_word(hw);
520 
521 		if (hw->tx_count >= hw->len) {
522 			/* mask tx fifo request interrupt as we are done */
523 			mask |= PSC_SPIMSK_TR;
524 		}
525 
526 		stat = hw->regs->psc_spistat;
527 		wmb(); /* drain writebuffer */
528 		if (stat & PSC_SPISTAT_TF)
529 			break;
530 	}
531 
532 	/* enable event interrupts */
533 	hw->regs->psc_spimsk = mask;
534 	wmb(); /* drain writebuffer */
535 
536 	/* start the transfer */
537 	hw->regs->psc_spipcr = PSC_SPIPCR_MS;
538 	wmb(); /* drain writebuffer */
539 
540 	wait_for_completion(&hw->host_done);
541 
542 	return min(hw->rx_count, hw->tx_count);
543 }
544 
au1550_spi_pio_irq_callback(struct au1550_spi * hw)545 static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw)
546 {
547 	int busy;
548 	u32 stat, evnt;
549 
550 	stat = hw->regs->psc_spistat;
551 	evnt = hw->regs->psc_spievent;
552 	wmb(); /* drain writebuffer */
553 	if ((stat & PSC_SPISTAT_DI) == 0) {
554 		dev_err(hw->dev, "Unexpected IRQ!\n");
555 		return IRQ_NONE;
556 	}
557 
558 	if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
559 				| PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
560 				| PSC_SPIEVNT_SD))
561 			!= 0) {
562 		/*
563 		 * due to an error we consider transfer as done,
564 		 * so mask all events until before next transfer start
565 		 */
566 		au1550_spi_mask_ack_all(hw);
567 		au1550_spi_reset_fifos(hw);
568 		dev_err(hw->dev,
569 			"pio transfer: unexpected SPI error (event=0x%x stat=0x%x)!\n",
570 			evnt, stat);
571 		complete(&hw->host_done);
572 		return IRQ_HANDLED;
573 	}
574 
575 	/*
576 	 * while there is something to read from rx fifo
577 	 * or there is a space to write to tx fifo:
578 	 */
579 	do {
580 		busy = 0;
581 		stat = hw->regs->psc_spistat;
582 		wmb(); /* drain writebuffer */
583 
584 		/*
585 		 * Take care to not let the Rx FIFO overflow.
586 		 *
587 		 * We only write a byte if we have read one at least. Initially,
588 		 * the write fifo is full, so we should read from the read fifo
589 		 * first.
590 		 * In case we miss a word from the read fifo, we should get a
591 		 * RO event and should back out.
592 		 */
593 		if (!(stat & PSC_SPISTAT_RE) && hw->rx_count < hw->len) {
594 			hw->rx_word(hw);
595 			busy = 1;
596 
597 			if (!(stat & PSC_SPISTAT_TF) && hw->tx_count < hw->len)
598 				hw->tx_word(hw);
599 		}
600 	} while (busy);
601 
602 	hw->regs->psc_spievent = PSC_SPIEVNT_RR | PSC_SPIEVNT_TR;
603 	wmb(); /* drain writebuffer */
604 
605 	/*
606 	 * Restart the SPI transmission in case of a transmit underflow.
607 	 * This seems to work despite the notes in the Au1550 data book
608 	 * of Figure 8-4 with flowchart for SPI host operation:
609 	 *
610 	 * """Note 1: An XFR Error Interrupt occurs, unless masked,
611 	 * for any of the following events: Tx FIFO Underflow,
612 	 * Rx FIFO Overflow, or Multiple-host Error
613 	 *    Note 2: In case of a Tx Underflow Error, all zeroes are
614 	 * transmitted."""
615 	 *
616 	 * By simply restarting the spi transfer on Tx Underflow Error,
617 	 * we assume that spi transfer was paused instead of zeroes
618 	 * transmittion mentioned in the Note 2 of Au1550 data book.
619 	 */
620 	if (evnt & PSC_SPIEVNT_TU) {
621 		hw->regs->psc_spievent = PSC_SPIEVNT_TU | PSC_SPIEVNT_MD;
622 		wmb(); /* drain writebuffer */
623 		hw->regs->psc_spipcr = PSC_SPIPCR_MS;
624 		wmb(); /* drain writebuffer */
625 	}
626 
627 	if (hw->rx_count >= hw->len) {
628 		/* transfer completed successfully */
629 		au1550_spi_mask_ack_all(hw);
630 		complete(&hw->host_done);
631 	}
632 	return IRQ_HANDLED;
633 }
634 
au1550_spi_txrx_bufs(struct spi_device * spi,struct spi_transfer * t)635 static int au1550_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
636 {
637 	struct au1550_spi *hw = spi_controller_get_devdata(spi->controller);
638 
639 	return hw->txrx_bufs(spi, t);
640 }
641 
au1550_spi_irq(int irq,void * dev)642 static irqreturn_t au1550_spi_irq(int irq, void *dev)
643 {
644 	struct au1550_spi *hw = dev;
645 
646 	return hw->irq_callback(hw);
647 }
648 
au1550_spi_bits_handlers_set(struct au1550_spi * hw,int bpw)649 static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw)
650 {
651 	if (bpw <= 8) {
652 		if (hw->usedma) {
653 			hw->txrx_bufs = &au1550_spi_dma_txrxb;
654 			hw->irq_callback = &au1550_spi_dma_irq_callback;
655 		} else {
656 			hw->rx_word = &au1550_spi_rx_word_8;
657 			hw->tx_word = &au1550_spi_tx_word_8;
658 			hw->txrx_bufs = &au1550_spi_pio_txrxb;
659 			hw->irq_callback = &au1550_spi_pio_irq_callback;
660 		}
661 	} else if (bpw <= 16) {
662 		hw->rx_word = &au1550_spi_rx_word_16;
663 		hw->tx_word = &au1550_spi_tx_word_16;
664 		hw->txrx_bufs = &au1550_spi_pio_txrxb;
665 		hw->irq_callback = &au1550_spi_pio_irq_callback;
666 	} else {
667 		hw->rx_word = &au1550_spi_rx_word_32;
668 		hw->tx_word = &au1550_spi_tx_word_32;
669 		hw->txrx_bufs = &au1550_spi_pio_txrxb;
670 		hw->irq_callback = &au1550_spi_pio_irq_callback;
671 	}
672 }
673 
au1550_spi_setup_psc_as_spi(struct au1550_spi * hw)674 static void au1550_spi_setup_psc_as_spi(struct au1550_spi *hw)
675 {
676 	u32 stat, cfg;
677 
678 	/* set up the PSC for SPI mode */
679 	hw->regs->psc_ctrl = PSC_CTRL_DISABLE;
680 	wmb(); /* drain writebuffer */
681 	hw->regs->psc_sel = PSC_SEL_PS_SPIMODE;
682 	wmb(); /* drain writebuffer */
683 
684 	hw->regs->psc_spicfg = 0;
685 	wmb(); /* drain writebuffer */
686 
687 	hw->regs->psc_ctrl = PSC_CTRL_ENABLE;
688 	wmb(); /* drain writebuffer */
689 
690 	do {
691 		stat = hw->regs->psc_spistat;
692 		wmb(); /* drain writebuffer */
693 	} while ((stat & PSC_SPISTAT_SR) == 0);
694 
695 
696 	cfg = hw->usedma ? 0 : PSC_SPICFG_DD_DISABLE;
697 	cfg |= PSC_SPICFG_SET_LEN(8);
698 	cfg |= PSC_SPICFG_RT_FIFO8 | PSC_SPICFG_TT_FIFO8;
699 	/* use minimal allowed brg and div values as initial setting: */
700 	cfg |= PSC_SPICFG_SET_BAUD(4) | PSC_SPICFG_SET_DIV(0);
701 
702 #ifdef AU1550_SPI_DEBUG_LOOPBACK
703 	cfg |= PSC_SPICFG_LB;
704 #endif
705 
706 	hw->regs->psc_spicfg = cfg;
707 	wmb(); /* drain writebuffer */
708 
709 	au1550_spi_mask_ack_all(hw);
710 
711 	hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE;
712 	wmb(); /* drain writebuffer */
713 
714 	do {
715 		stat = hw->regs->psc_spistat;
716 		wmb(); /* drain writebuffer */
717 	} while ((stat & PSC_SPISTAT_DR) == 0);
718 
719 	au1550_spi_reset_fifos(hw);
720 }
721 
722 
au1550_spi_probe(struct platform_device * pdev)723 static int au1550_spi_probe(struct platform_device *pdev)
724 {
725 	struct au1550_spi *hw;
726 	struct spi_controller *host;
727 	struct resource *r;
728 	int err = 0;
729 
730 	host = spi_alloc_host(&pdev->dev, sizeof(struct au1550_spi));
731 	if (host == NULL) {
732 		dev_err(&pdev->dev, "No memory for spi_controller\n");
733 		err = -ENOMEM;
734 		goto err_nomem;
735 	}
736 
737 	/* the spi->mode bits understood by this driver: */
738 	host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
739 	host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 24);
740 
741 	hw = spi_controller_get_devdata(host);
742 
743 	hw->host = host;
744 	hw->pdata = dev_get_platdata(&pdev->dev);
745 	hw->dev = &pdev->dev;
746 
747 	if (hw->pdata == NULL) {
748 		dev_err(&pdev->dev, "No platform data supplied\n");
749 		err = -ENOENT;
750 		goto err_no_pdata;
751 	}
752 
753 	r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
754 	if (!r) {
755 		dev_err(&pdev->dev, "no IRQ\n");
756 		err = -ENODEV;
757 		goto err_no_iores;
758 	}
759 	hw->irq = r->start;
760 
761 	hw->usedma = 0;
762 	r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
763 	if (r) {
764 		hw->dma_tx_id = r->start;
765 		r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
766 		if (r) {
767 			hw->dma_rx_id = r->start;
768 			if (usedma && ddma_memid) {
769 				if (pdev->dev.dma_mask == NULL)
770 					dev_warn(&pdev->dev, "no dma mask\n");
771 				else
772 					hw->usedma = 1;
773 			}
774 		}
775 	}
776 
777 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
778 	if (!r) {
779 		dev_err(&pdev->dev, "no mmio resource\n");
780 		err = -ENODEV;
781 		goto err_no_iores;
782 	}
783 
784 	hw->ioarea = request_mem_region(r->start, sizeof(psc_spi_t),
785 					pdev->name);
786 	if (!hw->ioarea) {
787 		dev_err(&pdev->dev, "Cannot reserve iomem region\n");
788 		err = -ENXIO;
789 		goto err_no_iores;
790 	}
791 
792 	hw->regs = (psc_spi_t __iomem *)ioremap(r->start, sizeof(psc_spi_t));
793 	if (!hw->regs) {
794 		dev_err(&pdev->dev, "cannot ioremap\n");
795 		err = -ENXIO;
796 		goto err_ioremap;
797 	}
798 
799 	platform_set_drvdata(pdev, hw);
800 
801 	init_completion(&hw->host_done);
802 
803 	hw->bitbang.master = hw->host;
804 	hw->bitbang.setup_transfer = au1550_spi_setupxfer;
805 	hw->bitbang.chipselect = au1550_spi_chipsel;
806 	hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs;
807 
808 	if (hw->usedma) {
809 		hw->dma_tx_ch = au1xxx_dbdma_chan_alloc(ddma_memid,
810 			hw->dma_tx_id, NULL, (void *)hw);
811 		if (hw->dma_tx_ch == 0) {
812 			dev_err(&pdev->dev,
813 				"Cannot allocate tx dma channel\n");
814 			err = -ENXIO;
815 			goto err_no_txdma;
816 		}
817 		au1xxx_dbdma_set_devwidth(hw->dma_tx_ch, 8);
818 		if (au1xxx_dbdma_ring_alloc(hw->dma_tx_ch,
819 			AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
820 			dev_err(&pdev->dev,
821 				"Cannot allocate tx dma descriptors\n");
822 			err = -ENXIO;
823 			goto err_no_txdma_descr;
824 		}
825 
826 
827 		hw->dma_rx_ch = au1xxx_dbdma_chan_alloc(hw->dma_rx_id,
828 			ddma_memid, NULL, (void *)hw);
829 		if (hw->dma_rx_ch == 0) {
830 			dev_err(&pdev->dev,
831 				"Cannot allocate rx dma channel\n");
832 			err = -ENXIO;
833 			goto err_no_rxdma;
834 		}
835 		au1xxx_dbdma_set_devwidth(hw->dma_rx_ch, 8);
836 		if (au1xxx_dbdma_ring_alloc(hw->dma_rx_ch,
837 			AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
838 			dev_err(&pdev->dev,
839 				"Cannot allocate rx dma descriptors\n");
840 			err = -ENXIO;
841 			goto err_no_rxdma_descr;
842 		}
843 
844 		err = au1550_spi_dma_rxtmp_alloc(hw,
845 			AU1550_SPI_DMA_RXTMP_MINSIZE);
846 		if (err < 0) {
847 			dev_err(&pdev->dev,
848 				"Cannot allocate initial rx dma tmp buffer\n");
849 			goto err_dma_rxtmp_alloc;
850 		}
851 	}
852 
853 	au1550_spi_bits_handlers_set(hw, 8);
854 
855 	err = request_irq(hw->irq, au1550_spi_irq, 0, pdev->name, hw);
856 	if (err) {
857 		dev_err(&pdev->dev, "Cannot claim IRQ\n");
858 		goto err_no_irq;
859 	}
860 
861 	host->bus_num = pdev->id;
862 	host->num_chipselect = hw->pdata->num_chipselect;
863 
864 	/*
865 	 *  precompute valid range for spi freq - from au1550 datasheet:
866 	 *    psc_tempclk = psc_mainclk / (2 << DIV)
867 	 *    spiclk = psc_tempclk / (2 * (BRG + 1))
868 	 *    BRG valid range is 4..63
869 	 *    DIV valid range is 0..3
870 	 *  round the min and max frequencies to values that would still
871 	 *  produce valid brg and div
872 	 */
873 	{
874 		int min_div = (2 << 0) * (2 * (4 + 1));
875 		int max_div = (2 << 3) * (2 * (63 + 1));
876 
877 		host->max_speed_hz = hw->pdata->mainclk_hz / min_div;
878 		host->min_speed_hz =
879 				hw->pdata->mainclk_hz / (max_div + 1) + 1;
880 	}
881 
882 	au1550_spi_setup_psc_as_spi(hw);
883 
884 	err = spi_bitbang_start(&hw->bitbang);
885 	if (err) {
886 		dev_err(&pdev->dev, "Failed to register SPI host\n");
887 		goto err_register;
888 	}
889 
890 	dev_info(&pdev->dev,
891 		"spi host registered: bus_num=%d num_chipselect=%d\n",
892 		host->bus_num, host->num_chipselect);
893 
894 	return 0;
895 
896 err_register:
897 	free_irq(hw->irq, hw);
898 
899 err_no_irq:
900 	au1550_spi_dma_rxtmp_free(hw);
901 
902 err_dma_rxtmp_alloc:
903 err_no_rxdma_descr:
904 	if (hw->usedma)
905 		au1xxx_dbdma_chan_free(hw->dma_rx_ch);
906 
907 err_no_rxdma:
908 err_no_txdma_descr:
909 	if (hw->usedma)
910 		au1xxx_dbdma_chan_free(hw->dma_tx_ch);
911 
912 err_no_txdma:
913 	iounmap((void __iomem *)hw->regs);
914 
915 err_ioremap:
916 	release_mem_region(r->start, sizeof(psc_spi_t));
917 
918 err_no_iores:
919 err_no_pdata:
920 	spi_controller_put(hw->host);
921 
922 err_nomem:
923 	return err;
924 }
925 
au1550_spi_remove(struct platform_device * pdev)926 static void au1550_spi_remove(struct platform_device *pdev)
927 {
928 	struct au1550_spi *hw = platform_get_drvdata(pdev);
929 
930 	dev_info(&pdev->dev, "spi host remove: bus_num=%d\n",
931 		hw->host->bus_num);
932 
933 	spi_bitbang_stop(&hw->bitbang);
934 	free_irq(hw->irq, hw);
935 	iounmap((void __iomem *)hw->regs);
936 	release_mem_region(hw->ioarea->start, sizeof(psc_spi_t));
937 
938 	if (hw->usedma) {
939 		au1550_spi_dma_rxtmp_free(hw);
940 		au1xxx_dbdma_chan_free(hw->dma_rx_ch);
941 		au1xxx_dbdma_chan_free(hw->dma_tx_ch);
942 	}
943 
944 	spi_controller_put(hw->host);
945 }
946 
947 /* work with hotplug and coldplug */
948 MODULE_ALIAS("platform:au1550-spi");
949 
950 static struct platform_driver au1550_spi_drv = {
951 	.probe = au1550_spi_probe,
952 	.remove_new = au1550_spi_remove,
953 	.driver = {
954 		.name = "au1550-spi",
955 	},
956 };
957 
au1550_spi_init(void)958 static int __init au1550_spi_init(void)
959 {
960 	/*
961 	 * create memory device with 8 bits dev_devwidth
962 	 * needed for proper byte ordering to spi fifo
963 	 */
964 	switch (alchemy_get_cputype()) {
965 	case ALCHEMY_CPU_AU1550:
966 	case ALCHEMY_CPU_AU1200:
967 	case ALCHEMY_CPU_AU1300:
968 		break;
969 	default:
970 		return -ENODEV;
971 	}
972 
973 	if (usedma) {
974 		ddma_memid = au1xxx_ddma_add_device(&au1550_spi_mem_dbdev);
975 		if (!ddma_memid)
976 			printk(KERN_ERR "au1550-spi: cannot add memory dbdma device\n");
977 	}
978 	return platform_driver_register(&au1550_spi_drv);
979 }
980 module_init(au1550_spi_init);
981 
au1550_spi_exit(void)982 static void __exit au1550_spi_exit(void)
983 {
984 	if (usedma && ddma_memid)
985 		au1xxx_ddma_del_device(ddma_memid);
986 	platform_driver_unregister(&au1550_spi_drv);
987 }
988 module_exit(au1550_spi_exit);
989 
990 MODULE_DESCRIPTION("Au1550 PSC SPI Driver");
991 MODULE_AUTHOR("Jan Nikitenko <jan.nikitenko@gmail.com>");
992 MODULE_LICENSE("GPL");
993