1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) ASPEED Technology Inc.
4 */
5 #include <common.h>
6 #include <asm/io.h>
7 #include <dm.h>
8 #include <dm/uclass.h>
9
10 DECLARE_GLOBAL_DATA_PTR;
11
12 #define AST_GPIO_BASE (0x1E780000)
13 #define AST_GPIOABCD_DRCTN (AST_GPIO_BASE + 0x004)
14 #define AST_GPIOEFGH_DRCTN (AST_GPIO_BASE + 0x024)
15 #define AST_GPIOMNOP_DRCTN (AST_GPIO_BASE + 0x07C)
16 #define AST_GPIOQRST_DRCTN (AST_GPIO_BASE + 0x084)
17 #define AST_GPIOUVWX_DRCTN (AST_GPIO_BASE + 0x08C)
18 #define AST_GPIOYZ_DRCTN (AST_GPIO_BASE + 0x1E4)
19
board_init(void)20 int board_init(void)
21 {
22 u32 direction;
23
24 struct udevice *dev;
25 int i;
26 int ret;
27
28 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
29
30 /*
31 * Loop over all MISC uclass drivers to call the comphy code
32 * and init all CP110 devices enabled in the DT
33 */
34 i = 0;
35 while (1) {
36 /* Call the comphy code via the MISC uclass driver */
37 ret = uclass_get_device(UCLASS_MISC, i++, &dev);
38
39 /* We're done, once no further CP110 device is found */
40 if (ret)
41 break;
42 }
43
44 /*
45 * in FT/SLT board, 4 MDIO channels are all connected to a single PHY
46 * chip. So only one MDIO channel can access the PHY chip at a time and
47 * the pins of the channels that are not under testing will be set to
48 * GPIO input. So simply the test program in Linux kernel, we configure
49 * GPIO setting here.
50 *
51 * GPIOS[1:0] -> MDC1 & MDIO1
52 * GPIOB[5:4] -> MDC2 & MDIO2
53 * GPIOA[1:0] -> MDC3 & MDIO3
54 * GPIOA[3:2] -> MDC4 & MDIO4
55 */
56 /* GPIOS[1:0] */
57 direction = readl(AST_GPIOQRST_DRCTN);
58 direction &= ~GENMASK(17, 16);
59 writel(direction, AST_GPIOQRST_DRCTN);
60
61 /* GPIOA[3:0] and GPIOB[5:4] */
62 direction = readl(AST_GPIOABCD_DRCTN);
63 direction &= ~(GENMASK(3, 0) | GENMASK(13, 12));
64 writel(direction, AST_GPIOABCD_DRCTN);
65
66 /*
67 * set 32 GPIO ouput pins for ATE report
68 * GPIOV[7:0] -> ATE[7:0]
69 * GPIOY[3:0] -> ATE[11:8]
70 * GPIOM[3:0] -> ATE[15:12]
71 * GPIOH[3:0] -> ATE[19:16]
72 * GPIOB[3:0] -> ATE[23:20]
73 * GPIOM[5:4] -> ATE[25:24]
74 * GPION[5:0] -> ATE[31:26]
75 */
76 /* GPIOB[3:0] */
77 direction = readl(AST_GPIOABCD_DRCTN);
78 direction |= 0xF00;
79 writel(direction, AST_GPIOABCD_DRCTN);
80
81 /* GPIOH[3:0] */
82 direction = readl(AST_GPIOEFGH_DRCTN);
83 direction |= 0xF000000;
84 writel(direction, AST_GPIOEFGH_DRCTN);
85
86 /* GPIOM[3:0], GPIOM[5:4], GPION[5:0] */
87 direction = readl(AST_GPIOMNOP_DRCTN);
88 direction |= 0x3F3F;
89 writel(direction, AST_GPIOMNOP_DRCTN);
90
91 /* GPIOV[7:0] */
92 direction = readl(AST_GPIOUVWX_DRCTN);
93 direction |= 0xFF00;
94 writel(direction, AST_GPIOUVWX_DRCTN);
95
96 /* GPIOY[3:0] */
97 direction = readl(AST_GPIOYZ_DRCTN);
98 direction |= 0xF;
99 writel(direction, AST_GPIOYZ_DRCTN);
100
101 return 0;
102 }
103