1 /*
2 * (C) Copyright ASPEED Technology Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6 #include <common.h>
7 #include <debug_uart.h>
8 #include <spl.h>
9 #include <dm.h>
10 #include <mmc.h>
11 #include <xyzModem.h>
12 #include <asm/io.h>
13
14 DECLARE_GLOBAL_DATA_PTR;
15
16 #define AST_BOOTMODE_SPI 0
17 #define AST_BOOTMODE_EMMC 1
18 #define AST_BOOTMODE_UART 2
19
20 #define SCU_BASE 0x1e6e2000
21 #define SCU_SMP_SEC_ENTRY (SCU_BASE + 0x1bc)
22 #define SCU_WPROT2 (SCU_BASE + 0xf04)
23
24 u32 aspeed_bootmode(void);
25 void aspeed_mmc_init(void);
26 static void spl_boot_from_uart_wdt_disable(void);
27
board_init_f(ulong dummy)28 void board_init_f(ulong dummy)
29 {
30 #ifndef CONFIG_SPL_TINY
31 struct udevice *dev;
32 spl_early_init();
33 timer_init();
34 uclass_get_device(UCLASS_PINCTRL, 0, &dev);
35 preloader_console_init();
36 dram_init();
37 aspeed_mmc_init();
38 spl_boot_from_uart_wdt_disable();
39 #endif
40 }
41
42 #ifdef CONFIG_SPL_BOARD_INIT
spl_board_init(void)43 void spl_board_init(void)
44 {
45 struct udevice *dev;
46
47 if ((IS_ENABLED(CONFIG_ASPEED_HACE_V1) || IS_ENABLED(CONFIG_ASPEED_HACE)) &&
48 uclass_get_device_by_driver(UCLASS_MISC,
49 DM_GET_DRIVER(aspeed_hace),
50 &dev)) {
51 debug("Warning: HACE initialization failure\n");
52 }
53 }
54 #endif
55
spl_boot_device(void)56 u32 spl_boot_device(void)
57 {
58 switch (aspeed_bootmode()) {
59 case AST_BOOTMODE_EMMC:
60 return BOOT_DEVICE_MMC1;
61 case AST_BOOTMODE_SPI:
62 return BOOT_DEVICE_RAM;
63 case AST_BOOTMODE_UART:
64 return BOOT_DEVICE_UART;
65 default:
66 break;
67 }
68
69 return BOOT_DEVICE_NONE;
70 }
71
board_boot_order(u32 * spl_boot_list)72 void board_boot_order(u32 *spl_boot_list)
73 {
74 spl_boot_list[0] = spl_boot_device();
75 spl_boot_list[1] = BOOT_DEVICE_UART;
76 }
77
78 #ifdef CONFIG_SPL_OS_BOOT
spl_start_uboot(void)79 int spl_start_uboot(void)
80 {
81 /* boot linux */
82 return 0;
83 }
84 #endif
85
board_fit_image_post_process(const void * fit,int node,void ** p_image,size_t * p_size)86 void board_fit_image_post_process(const void *fit, int node, void **p_image, size_t *p_size)
87 {
88 ulong s_ep;
89 uint8_t os;
90
91 fit_image_get_os(fit, node, &os);
92
93 /* skip if no TEE */
94 if (os != IH_OS_TEE)
95 return;
96
97 fit_image_get_entry(fit, node, &s_ep);
98
99 /* set & lock secure entrypoint for secondary cores */
100 writel(s_ep, SCU_SMP_SEC_ENTRY);
101 writel(BIT(17) | BIT(18) | BIT(19), SCU_WPROT2);
102 }
103
board_fit_config_name_match(const char * name)104 int board_fit_config_name_match(const char *name)
105 {
106 /* we always use the default configuration */
107 debug("%s: %s\n", __func__, name);
108 return 0;
109 }
110
spl_get_load_buffer(ssize_t offset,size_t size)111 struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
112 {
113 return (struct image_header *)(CONFIG_SYS_LOAD_ADDR);
114 }
115
spl_boot_from_uart_wdt_disable(void)116 static void spl_boot_from_uart_wdt_disable(void)
117 {
118 int boot_mode = aspeed_bootmode();
119
120 /* Disable ABR WDT for SPI flash and eMMC ABR. */
121 if (boot_mode == AST_BOOTMODE_UART) {
122 writel(0, 0x1e620064);
123 writel(0, 0x1e6f20a0);
124 }
125 }
126