1/*
2 *  This program is distributed in the hope that it will be useful,
3 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
4 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5 *  GNU General Public License for more details.
6 *
7 *  You should have received a copy of the GNU General Public License
8 *  along with this program; if not, write to the Free Software
9 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
10 */
11/*
12 * Board specific setup info
13 *
14 ******************************************************************************
15 * ASPEED Technology Inc.
16 * AST25x0 DDR3/DDR4 SDRAM controller initialization sequence
17 *
18 * Gary Hsu, <gary_hsu@aspeedtech.com>
19 *
20 * Version     : 18
21 * Release date: 2017.10.27
22 *
23 * Priority of fix item:
24 * [P1] = critical
25 * [P2] = nice to have
26 * [P3] = minor
27 *
28 * Change List :
29 * V2 |2014.07.25 : 1.[P1] Modify HPLL config sequence
30 * V2 |2014.07.30 : 1.[P1] Modify DDR3 AC parameters table
31 *    |             2.[P1] Turn on ZQCS mode
32 * V2 |2014.08.13 : 1.[P1] Add disable XDMA
33 * V2 |2014.09.09 : 1.[P1] Disable CKE dynamic power down
34 * V2 |2014.10.31 : 1.[P2] Enable VGA wide screen support (SCU40[0]=1)
35 * V2 |2015.03.26 : 1.[P1] Revise AC timing table
36 *    |             2.[P1] Add check code to bypass A0 patch
37 *    |             3.[P1] Add MPLL parameter of A1
38 *    |             4.[P1] Set X-DMA into VGA memory domain
39 * V2 |2015.04.24 : 1.[P1] Add disabling all DRAM requests during PHY init
40 *    |             2.[P1] Set MCR1C & MCR38
41 * V3 |2015.05.13 : 1.[P1] Modify DDR4 PHY Vref training algorithm
42 *    |             2.[P2] Enable CKE dynamic power down
43 * V4 |2015.06.15 : 1.[P1] Add MAC timing setting
44 * V5 |2015.07.09 : 1.[P1] Modify MHCLK divider ratio
45 *    |             2.[P2] Add DDR read margin report
46 * V6 |2015.08.13 : 1.[P3] Disable MMC password before exit
47 * V6 |2015.08.24 : 1.[P1] Fix SCU160 parameter value for CLKIN=25MHz condition
48 * V7 |2015.09.18 : 1.[P1] Clear AHB bus lock condition at power up time
49 *    |             2.[P1] Add reset MMC controller to solve init DRAM again during VGA ON
50 * V7 |2015.09.22 : 1.[P1] Add watchdog full reset for resolving reset incomplete issue at fast reset condition
51 *    |             2.[P1] Add DRAM stress test after train complete, and redo DRAM initial if stress fail
52 *    |             3.[P2] Enable JTAG master mode
53 *    |             4.[P2] Add DDR4 Vref trainig retry timeout
54 * V8 |2015.11.02 : 1.[P2] Clear software strap flag before doing watchdog full reset
55 *    |2015.12.10 : 1.[P1] Add USB PHY initial code
56 *    |2016.01.27 : 1.[P3] Modify the first reset from full chip reset to SOC reset
57 *    |             2.[P3] Remove HPLL/MPLL patch code for revision A0
58 *    |             3.[P2] Move the reset_mmc code to be after MPLL initialized
59 * V9 |2016.02.19 : 1.[P3] Remove definition "CONFIG_FIRMWARE_2ND_BOOT"
60 * V10|2016.04.21 : 1.[P1] Add USB PHY initial code - port B, to prevent wrong state on USB pins
61 * V11|2016.05.10 : 1.[P3] Add DRAM Extended temperature range support
62 * V12|2016.06.24 : 1.[P1] Modify LPC Reset input source when eSPI mode enabled
63 *    |2016.07.12 : 2.[P1] Modify DDR4 read path ODT from 60 ohm to 48 ohm, at address 0x1e6e0204
64 *    |           : 3.[P1] Modify DDR4 Ron calibration to manual mode to fix Vix issue, set Ron_pu = 0
65 *    |           : 4.[P2] Modify read timing margin report policy, change DDR4 min value from 0.35 to 0.3. Add "Warning" while violated.
66 * V13|2016.08.29 : 1.[P3] Add option to route debug message output port from UART5 to UART1
67 *    |2016.09.02 : 2.[P2] Add range control for cache function when ECC enabled
68 *    |2016.09.06 : 3.[P1] Enable full mask setting for first SOC reset, since the coverage of original default setting is not enough
69 * V14|2016.10.25 : 1.[P2] Change Ron manual calibration to default OFF, customer can enable it to do fine-tuning of the Vix issue
70 *    |2016.11.07 : 2.[P3] Add log information of DDR4 PHY Vref training
71 * V15|2017.04.06 : 1.[P1] Modify USB portA initial sequence, this is to prevent DMA lock condition of USB Virtual Hub device for some chips.
72 *    |2017.04.13 : 2.[P2] Add initial sequence for LPC controller
73 * V16|2017.06.15 : 1.[P1] Add margin check/retry for DDR4 Vref training margin.
74 *    |2017.06.15 : 2.[P1] Add margin check/retry for DDR3/DDR4 read timing training margin.
75 *    |2017.06.19 : 3.[P2] Add initial sequence for LPC controller
76 *    |2017.06.19 : 4.[P2] Add initial full-chip reset option
77 *    |2017.06.19 : 5.[P3] Add 10ms delay after DDR reset
78 * V17|2017.09.25 : 1.[P1] Modify DDR4 side ODT value from 60ohm to 48ohm.
79 *    |2017.09.25 : 2.[P1] Add Hynix DDR4 frequency slow down option.
80 * V18|2017.10.26 : 1.[P3] Include the modification of DDR4 side ODT value in V17 into the option of Hynix DDR4 configuration.
81 *    |2017.10.26 : 2.[P2] Enhance initial sequence for LPC controller
82 * Note: Read timing report is only a reference, it is not a solid rule for stability.
83 *
84 * Optional define variable
85 * 1. DRAM Speed                  //
86 *    CONFIG_DRAM_1333            //
87 *    CONFIG_DRAM_1600            // (default)
88 * 2. ECC Function enable
89 *    CONFIG_DRAM_ECC             // define to enable ECC function
90 *    CONFIG_DRAM_ECC_SIZE        // define the ECC protected memory size
91 * 3. UART5 message output        //
92 *    CONFIG_DRAM_UART_38400      // set the UART baud rate to 38400, default is 115200
93 *    CONFIG_DRAM_UART_TO_UART1   // route UART5 to UART port1
94 * 4. DRAM Type
95 *    CONFIG_DDR3_8GSTACK         // DDR3 8Gbit Stack die
96 *    CONFIG_DDR4_4GX8            // DDR4 4Gbit X8 dual part
97 * 5. Firmware 2nd boot flash
98 *    CONFIG_FIRMWARE_2ND_BOOT (Removed)
99 * 6. Enable DRAM extended temperature range mode
100 *    CONFIG_DRAM_EXT_TEMP
101 * 7. Select WDT_Full mode for power up initial reset
102 *    ASTMMC_INIT_RESET_MODE_FULL
103 * 8. Hynix DDR4 options
104 *    CONFIG_DDR4_SUPPORT_HYNIX   // Enable this when Hynix DDR4 included in the BOM
105 *    CONFIG_DDR4_HYNIX_SET_1536
106 *    CONFIG_DDR4_HYNIX_SET_1488
107 *    CONFIG_DDR4_HYNIX_SET_1440  // Default
108 ******************************************************************************
109 */
110
111#include <config.h>
112#include <version.h>
113
114/******************************************************************************
115  r4 : return program counter
116  r5 : DDR speed timing table base address
117  Free registers:
118  r0, r1, r2, r3, r6, r7, r8, r9, r10, r11
119 ******************************************************************************/
120#define ASTMMC_INIT_VER      0x12                @ 8bit verison number
121#define ASTMMC_INIT_DATE     0x20171027          @ Release date
122
123/******************************************************************************
124  BMC side DDR IO driving manual mode fine-tuning, used to improve CK/CKN Vix violation.
125  Default disabled, the driver setting is hardware auto tuned.
126
127  ASTMMC_DDR4_MANUAL_RPU | ASTMMC_DDR4_MANUAL_RPD
128  -----------------------+-----------------------
129            No           |           x          : manual mode disabled
130            Yes          |          No          : enable Rpu     manual setting
131            Yes          |          Yes         : enable Rpu/Rpd manual setting
132 ******************************************************************************/
133//#define ASTMMC_DDR4_MANUAL_RPU 0x0             @ 0x0-0xF, larger value means weaker driving
134//#define ASTMMC_DDR4_MANUAL_RPD 0x0             @ 0x0-0xF, larger value means stronger driving
135
136/******************************************************************************
137  Select initial reset mode as WDT_Full
138  WDT_Full is a more complete reset mode than WDT_SOC.
139  But if FW has other initial code executed before platform.S, then it should use WDT_SOC mode.
140  Use WDT_Full may clear the initial result of prior initial code.
141 ******************************************************************************/
142//#define ASTMMC_INIT_RESET_MODE_FULL
143
144/******************************************************************************
145  There is a compatibility issue for Hynix DDR4 SDRAM.
146  Hynix DDR4 SDRAM is more weak on noise margin compared to Micron and Samsung DDR4.
147  To well support Hynix DDR4, it requlres to slow down the DDR4 operating frequency
148  from 1600Mbps to 1536/1488/1440 Mbps. The target frequency that can be used depends
149  on the MB layout. Customer can find the appropriate frequency for their products.
150  Below are the new defined parameters for the Hynix DDR4 supporting.
151 ******************************************************************************/
152#define CONFIG_DDR4_SUPPORT_HYNIX              @ Enable this when Hynix DDR4 included in the BOM
153//#define CONFIG_DDR4_HYNIX_SET_1536
154//#define CONFIG_DDR4_HYNIX_SET_1488
155#define CONFIG_DDR4_HYNIX_SET_1440
156
157#define ASTMMC_REGIDX_010    0x00
158#define ASTMMC_REGIDX_014    0x04
159#define ASTMMC_REGIDX_018    0x08
160#define ASTMMC_REGIDX_020    0x0C
161#define ASTMMC_REGIDX_024    0x10
162#define ASTMMC_REGIDX_02C    0x14
163#define ASTMMC_REGIDX_030    0x18
164#define ASTMMC_REGIDX_214    0x1C
165#define ASTMMC_REGIDX_2E0    0x20
166#define ASTMMC_REGIDX_2E4    0x24
167#define ASTMMC_REGIDX_2E8    0x28
168#define ASTMMC_REGIDX_2EC    0x2C
169#define ASTMMC_REGIDX_2F0    0x30
170#define ASTMMC_REGIDX_2F4    0x34
171#define ASTMMC_REGIDX_2F8    0x38
172#define ASTMMC_REGIDX_RFC    0x3C
173#define ASTMMC_REGIDX_PLL    0x40
174
175TIME_TABLE_DDR3_1333:
176    .word   0x53503C37       @ 0x010
177    .word   0xF858D47F       @ 0x014
178    .word   0x00010000       @ 0x018
179    .word   0x00000000       @ 0x020
180    .word   0x00000000       @ 0x024
181    .word   0x02101C60       @ 0x02C
182    .word   0x00000040       @ 0x030
183    .word   0x00000020       @ 0x214
184    .word   0x02001000       @ 0x2E0
185    .word   0x0C000085       @ 0x2E4
186    .word   0x000BA018       @ 0x2E8
187    .word   0x2CB92104       @ 0x2EC
188    .word   0x07090407       @ 0x2F0
189    .word   0x81000700       @ 0x2F4
190    .word   0x0C400800       @ 0x2F8
191    .word   0x7F5E3A27       @ tRFC
192    .word   0x00005B80       @ PLL
193TIME_TABLE_DDR3_1600:
194    .word   0x64604D38       @ 0x010
195    .word   0x29690599       @ 0x014
196    .word   0x00000300       @ 0x018
197    .word   0x00000000       @ 0x020
198    .word   0x00000000       @ 0x024
199    .word   0x02181E70       @ 0x02C
200    .word   0x00000040       @ 0x030
201    .word   0x00000024       @ 0x214
202    .word   0x02001300       @ 0x2E0
203    .word   0x0E0000A0       @ 0x2E4
204    .word   0x000E001B       @ 0x2E8
205    .word   0x35B8C105       @ 0x2EC
206    .word   0x08090408       @ 0x2F0
207    .word   0x9B000800       @ 0x2F4
208    .word   0x0E400A00       @ 0x2F8
209    .word   0x9971452F       @ tRFC
210    .word   0x000071C1       @ PLL
211
212TIME_TABLE_DDR4_1333:
213    .word   0x53503D26       @ 0x010
214    .word   0xE878D87F       @ 0x014
215    .word   0x00019000       @ 0x018
216    .word   0x08000000       @ 0x020
217    .word   0x00000400       @ 0x024
218    .word   0x00000200       @ 0x02C
219    .word   0x00000101       @ 0x030
220    .word   0x00000020       @ 0x214
221    .word   0x03002200       @ 0x2E0
222    .word   0x0C000085       @ 0x2E4
223    .word   0x000BA01A       @ 0x2E8
224    .word   0x2CB92106       @ 0x2EC
225    .word   0x07060606       @ 0x2F0
226    .word   0x81000700       @ 0x2F4
227    .word   0x0C400800       @ 0x2F8
228    .word   0x7F5E3A3A       @ tRFC
229    .word   0x00005B80       @ PLL
230TIME_TABLE_DDR4_1600:
231    .word   0x63604E37       @ 0x010
232    .word   0xE97AFA99       @ 0x014
233    .word   0x00019000       @ 0x018
234    .word   0x08000000       @ 0x020
235    .word   0x00000400       @ 0x024
236    .word   0x00000410       @ 0x02C
237#ifdef CONFIG_DDR4_SUPPORT_HYNIX
238    .word   0x00000501       @ 0x030             @ ODT = 48 ohm
239#else
240    .word   0x00000101       @ 0x030             @ ODT = 60 ohm
241#endif
242    .word   0x00000024       @ 0x214
243    .word   0x03002900       @ 0x2E0
244    .word   0x0E0000A0       @ 0x2E4
245    .word   0x000E001C       @ 0x2E8
246    .word   0x35B8C106       @ 0x2EC
247    .word   0x08080607       @ 0x2F0
248    .word   0x9B000900       @ 0x2F4
249    .word   0x0E400A00       @ 0x2F8
250    .word   0x99714545       @ tRFC
251    .word   0x000071C1       @ PLL
252
253    .macro init_delay_timer
254    ldr   r0, =0x1e782024                        @ Set Timer3 Reload
255    str   r2, [r0]
256
257    ldr   r0, =0x1e6c0038                        @ Clear Timer3 ISR
258    ldr   r1, =0x00040000
259    str   r1, [r0]
260
261    ldr   r0, =0x1e782030                        @ Enable Timer3
262    mov   r2, #7
263    mov   r1, r2, lsl #8
264    str   r1, [r0]
265
266    ldr   r0, =0x1e6c0090                        @ Check ISR for Timer3 timeout
267    .endm
268
269    .macro check_delay_timer
270    ldr   r1, [r0]
271    bic   r1, r1, #0xFFFBFFFF
272    mov   r2, r1, lsr #18
273    cmp   r2, #0x01
274    .endm
275
276    .macro clear_delay_timer
277    ldr   r0, =0x1e78203C                        @ Disable Timer3
278    mov   r2, #0xF
279    mov   r1, r2, lsl #8
280    str   r1, [r0]
281
282    ldr   r0, =0x1e6c0038                        @ Clear Timer3 ISR
283    ldr   r1, =0x00040000
284    str   r1, [r0]
285    .endm
286
287    .macro init_spi_checksum
288    ldr   r0, =0x1e620084
289    ldr   r1, =0x20010000
290    str   r1, [r0]
291    ldr   r0, =0x1e62008C
292    ldr   r1, =0x20000200
293    str   r1, [r0]
294    ldr   r0, =0x1e620080
295    ldr   r1, =0x0000000D
296    orr   r2, r2, r7
297    orr   r1, r1, r2, lsl #8
298    and   r2, r6, #0xF
299    orr   r1, r1, r2, lsl #4
300    str   r1, [r0]
301    ldr   r0, =0x1e620008
302    ldr   r2, =0x00000800
303    .endm
304
305    .macro print_hex_char
306    and   r1, r1, #0xF
307    cmp   r1, #9
308    addgt r1, r1, #0x37
309    addle r1, r1, #0x30
310    str   r1, [r0]
311    .endm
312
313/******************************************************************************
314 Calibration Macro End
315 ******************************************************************************/
316
317.globl lowlevel_init
318lowlevel_init:
319
320init_dram:
321    /********************************************
322       Initial Reset Procedure : Begin
323     *******************************************/
324    /* Clear AHB bus lock condition */
325    ldr   r0, =0x1e600000
326    ldr   r1, =0xAEED1A03
327    str   r1, [r0]
328    ldr   r0, =0x1e600084
329    ldr   r1, =0x00010000
330    str   r1, [r0]
331    add   r0, r0, #0x4
332    mov   r1, #0x0
333    str   r1, [r0]
334
335    ldr   r0, =0x1e6e2000
336    ldr   r1, =0x1688a8a8
337    str   r1, [r0]
338
339    /* Reset again */
340    ldr   r0, =0x1e6e2070                        @ check fast reset flag
341    ldr   r2, =0x08000000
342    ldr   r1, [r0]
343    tst   r1, r2
344    beq   bypass_first_reset
345
346    ldr   r0, =0x1e785010
347    ldr   r3, [r0]
348    cmp   r3, #0x0
349    beq   start_first_reset
350    add   r0, r0, #0x04
351    mov   r3, #0x77
352    str   r3, [r0]
353    ldr   r0, =0x1e720004                        @ Copy initial strap register to 0x1e720004
354    str   r1, [r0]
355    add   r0, r0, #0x04                          @ Copy initial strap register to 0x1e720008
356    str   r1, [r0]
357    add   r0, r0, #0x04                          @ Copy initial strap register to 0x1e72000c
358    str   r1, [r0]
359    ldr   r0, =0x1e6e207c                        @ clear fast reset flag
360    str   r2, [r0]
361    ldr   r0, =0x1e6e203c                        @ clear watchdog reset flag
362    ldr   r1, [r0]
363    and   r1, r1, #0x01
364    str   r1, [r0]
365    ldr   r0, =0x1e78501c                        @ restore normal mask setting
366    ldr   r1, =0x023FFFF3                        @ added 2016.09.06
367    str   r1, [r0]
368    b     bypass_first_reset
369
370start_first_reset:
371#ifdef ASTMMC_INIT_RESET_MODE_FULL
372    ldr   r0, =0x1e785004
373    ldr   r1, =0x00000001
374    str   r1, [r0]
375    ldr   r0, =0x1e785008
376    ldr   r1, =0x00004755
377    str   r1, [r0]
378    ldr   r0, =0x1e78500c                        @ enable Full reset
379    ldr   r1, =0x00000033
380    str   r1, [r0]
381#else
382    /***** Clear LPC status : Begin *****/
383    mov   r2, #0                                 @ set r2 = 0, freezed
384    ldr   r0, =0x1e787008
385    mov   r1, #0x7
386    str   r1, [r0]
387    ldr   r0, =0x1e78700c
388    mov   r1, #0x3
389    str   r1, [r0]
390    ldr   r0, =0x1e787020
391    str   r2, [r0]
392    ldr   r0, =0x1e787034
393    str   r2, [r0]
394    ldr   r0, =0x1e787004
395    str   r2, [r0]
396    ldr   r0, =0x1e787010
397    str   r2, [r0]
398    ldr   r0, =0x1e78701c
399    str   r2, [r0]
400    ldr   r0, =0x1e787014                        @ read clear
401    ldr   r1, [r0]
402    ldr   r0, =0x1e787018                        @ read clear
403    ldr   r1, [r0]
404    ldr   r0, =0x1e787008                        @ read clear
405    ldr   r1, [r0]
406    ldr   r0, =0x1e78301c                        @ read clear
407    ldr   r1, [r0]
408    ldr   r0, =0x1e78d01c                        @ read clear
409    ldr   r1, [r0]
410    ldr   r0, =0x1e78e01c                        @ read clear
411    ldr   r1, [r0]
412    ldr   r0, =0x1e78f01c                        @ read clear
413    ldr   r1, [r0]
414    ldr   r0, =0x1e788020
415    str   r2, [r0]
416    ldr   r0, =0x1e788034
417    str   r2, [r0]
418    ldr   r0, =0x1e78800c
419    str   r2, [r0]
420    ldr   r0, =0x1e789008
421    str   r2, [r0]
422    ldr   r0, =0x1e789010
423    mov   r1, #0x40
424    str   r1, [r0]
425    ldr   r0, =0x1e789024                        @ read clear
426    ldr   r1, [r0]
427    ldr   r0, =0x1e789028                        @ read clear
428    ldr   r1, [r0]
429    ldr   r0, =0x1e78902c                        @ read clear
430    ldr   r1, [r0]
431    ldr   r0, =0x1e789114                        @ read clear
432    ldr   r1, [r0]
433    ldr   r0, =0x1e789124                        @ read clear
434    ldr   r1, [r0]
435    ldr   r0, =0x1e78903c
436    str   r2, [r0]
437    ldr   r0, =0x1e789040
438    str   r2, [r0]
439    ldr   r0, =0x1e789044
440    str   r2, [r0]
441    ldr   r0, =0x1e78911c
442    str   r2, [r0]
443    ldr   r0, =0x1e78912c
444    ldr   r1, =0x200
445    str   r1, [r0]
446    ldr   r0, =0x1e789104
447    ldr   r1, =0xcc00
448    str   r1, [r0]
449    ldr   r0, =0x1e789108
450    str   r2, [r0]
451    ldr   r0, =0x1e78910c
452    ldr   r1, =0x1f0
453    str   r1, [r0]
454    ldr   r0, =0x1e789170
455    str   r2, [r0]
456    ldr   r0, =0x1e789174
457    str   r2, [r0]
458    ldr   r0, =0x1e7890a0
459    ldr   r1, =0xff00
460    str   r1, [r0]
461    ldr   r0, =0x1e7890a4
462    str   r2, [r0]
463    ldr   r0, =0x1e789080
464    ldr   r1, =0x400
465    str   r1, [r0]
466    ldr   r0, =0x1e789084
467    ldr   r1, =0x0001000f
468    str   r1, [r0]
469    ldr   r0, =0x1e789088
470    ldr   r1, =0x3000fff8
471    str   r1, [r0]
472    ldr   r0, =0x1e78908c
473    ldr   r1, =0xfff8f007
474    str   r1, [r0]
475    ldr   r0, =0x1e789098
476    ldr   r1, =0x00000a30
477    str   r1, [r0]
478    ldr   r0, =0x1e78909c
479    str   r2, [r0]
480    ldr   r0, =0x1e789100
481    str   r2, [r0]
482    ldr   r0, =0x1e789130
483    ldr   r1, =0x00000080
484    str   r1, [r0]
485    ldr   r0, =0x1e789138
486    ldr   r1, =0x00010198
487    str   r1, [r0]
488    ldr   r0, =0x1e789140
489    ldr   r1, =0x0000a000
490    str   r1, [r0]
491    ldr   r0, =0x1e789158
492    ldr   r1, =0x00000080
493    str   r1, [r0]
494    ldr   r0, =0x1e789180
495    ldr   r1, =0xb6db1bff
496    str   r1, [r0]
497    ldr   r0, =0x1e789184
498    str   r2, [r0]
499    ldr   r0, =0x1e789188
500    str   r2, [r0]
501    ldr   r0, =0x1e78918c
502    str   r2, [r0]
503    ldr   r0, =0x1e789190
504    ldr   r1, =0x05020100
505    str   r1, [r0]
506    ldr   r0, =0x1e789194
507    ldr   r1, =0x07000706
508    str   r1, [r0]
509    ldr   r0, =0x1e789198
510    str   r2, [r0]
511    ldr   r0, =0x1e78919c
512    ldr   r1, =0x30
513    str   r1, [r0]
514    ldr   r0, =0x1e7891a0
515    ldr   r1, =0x00008100
516    str   r1, [r0]
517    ldr   r0, =0x1e7891a4
518    ldr   r1, =0x2000
519    str   r1, [r0]
520    ldr   r0, =0x1e7891a8
521    ldr   r1, =0x3ff
522    str   r1, [r0]
523    ldr   r0, =0x1e7891ac
524    str   r2, [r0]
525    ldr   r0, =0x1e789240
526    mov   r1, #0xff
527    str   r1, [r0]
528    ldr   r0, =0x1e789244
529    str   r1, [r0]
530    ldr   r0, =0x1e789248
531    mov   r1, #0x80
532    str   r1, [r0]
533    ldr   r0, =0x1e789250
534    str   r2, [r0]
535    ldr   r0, =0x1e789254
536    str   r2, [r0]
537    /***** Clear LPC status : End *****/
538
539    ldr   r0, =0x1e62009c                        @ clear software strap flag for doing again after reset
540    ldr   r1, =0xAEEDFC20
541    str   r1, [r0]
542    ldr   r0, =0x1e785004
543    ldr   r1, =0x00000001
544    str   r1, [r0]
545    ldr   r0, =0x1e785008
546    ldr   r1, =0x00004755
547    str   r1, [r0]
548    ldr   r0, =0x1e78501c                        @ enable full mask of SOC reset
549    ldr   r1, =0x03FFFFFF                        @ added 2016.09.06
550    str   r1, [r0]
551    ldr   r0, =0x1e78500c                        @ enable SOC reset
552    ldr   r1, =0x00000013
553    str   r1, [r0]
554#endif
555wait_first_reset:
556    b     wait_first_reset
557
558    /********************************************
559       Initial Reset Procedure : End
560     *******************************************/
561
562bypass_first_reset:
563    /* Enable Timer separate clear mode */
564    ldr   r0, =0x1e782038
565    mov   r1, #0xAE
566    str   r1, [r0]
567
568/* Test - DRAM initial time */
569    ldr   r0, =0x1e78203c
570    ldr   r1, =0x0000F000
571    str   r1, [r0]
572
573    ldr   r0, =0x1e782044
574    ldr   r1, =0xFFFFFFFF
575    str   r1, [r0]
576
577    ldr   r0, =0x1e782030
578    mov   r2, #3
579    mov   r1, r2, lsl #12
580    str   r1, [r0]
581/* Test - DRAM initial time */
582
583    /*Set Scratch register Bit 7 before initialize*/
584    ldr   r0, =0x1e6e2000
585    ldr   r1, =0x1688a8a8
586    str   r1, [r0]
587
588    ldr   r0, =0x1e6e2040
589    ldr   r1, [r0]
590    orr   r1, r1, #0x80
591    str   r1, [r0]
592
593    /* Change LPC reset source to PERST# when eSPI mode enabled */
594    ldr   r0, =0x1e6e2070
595    ldr   r1, [r0]
596    ldr   r0, =0x1e6e207c
597    ldr   r2, =0x02000000
598    ldr   r3, =0x00004000
599    tst   r1, r2
600    strne r3, [r0]
601
602    /* Configure USB ports to the correct pin state */
603    ldr   r0, =0x1e6e200c                        @ enable portA clock
604    ldr   r2, =0x00004000
605    ldr   r1, [r0]
606    orr   r1, r1, r2
607    str   r1, [r0]
608    ldr   r0, =0x1e6e2090                        @ set portA as host mode
609    ldr   r1, =0x2000A000
610    str   r1, [r0]
611    ldr   r0, =0x1e6e2094                        @ set portB as host mode
612    ldr   r1, =0x00004000
613    str   r1, [r0]
614    ldr   r0, =0x1e6e2070
615    ldr   r2, =0x00800000
616    ldr   r1, [r0]
617    tst   r1, r2
618    beq   bypass_USB_init
619    ldr   r0, =0x1e6e207c
620    str   r2, [r0]
621
622    /* Delay about 1ms */
623    clear_delay_timer
624    ldr   r2, =0x000003E8                        @ Set Timer3 Reload = 1 ms
625    init_delay_timer
626wait_usb_init:
627    check_delay_timer
628    bne   wait_usb_init
629    clear_delay_timer
630    /* end delay 1ms */
631
632    ldr   r0, =0x1e6e2070
633    ldr   r1, =0x00800000
634    str   r1, [r0]
635
636bypass_USB_init:
637    /* Enable AXI_P */
638    ldr   r0, =0x00000016
639    mrc   p15, 0, r1, c15, c2, 4
640    mcr   p15, 0, r0, c15, c2, 4
641
642/******************************************************************************
643 Disable WDT2 for 2nd boot function
644 ******************************************************************************/
645/*
646#ifndef CONFIG_FIRMWARE_2ND_BOOT
647    ldr   r0, =0x1e78502c
648    mov   r1, #0
649    str   r1, [r0]
650#endif
651*/
652/******************************************************************************
653 Disable WDT3 for SPI Address mode (3 or 4 bytes) detection function
654 ******************************************************************************/
655    ldr   r0, =0x1e78504c
656    mov   r1, #0
657    str   r1, [r0]
658
659    ldr   r0, =0x1e6e0000
660    ldr   r1, =0xFC600309
661    str   r1, [r0]
662
663#ifdef CONFIG_RAM
664	mov   pc, lr
665#endif
666
667    /* Check Scratch Register Bit 6 */
668    ldr   r0, =0x1e6e2040
669    ldr   r1, [r0]
670    bic   r1, r1, #0xFFFFFFBF
671    mov   r2, r1, lsr #6
672    cmp   r2, #0x01
673    beq   platform_exit
674
675    /* Disable VGA display */
676    ldr   r0, =0x1e6e202c
677    ldr   r1, [r0]
678    orr   r1, r1, #0x40
679    str   r1, [r0]
680
681    ldr   r0, =0x1e6e2070                        @ Load strap register
682    ldr   r3, [r0]
683
684    /* Set M-PLL */
685#if   defined (CONFIG_DRAM_1333)
686    ldr   r2, =0xC48066C0                        @ load PLL parameter for 24Mhz CLKIN (330)
687#else
688    ldr   r2, =0x93002400                        @ load PLL parameter for 24Mhz CLKIN (396)
689#if   defined (CONFIG_DDR4_SUPPORT_HYNIX)
690    mov   r1, r3, lsr #24                        @ Check DDR4
691    tst   r1, #0x01
692    beq   bypass_mpll_hynix_mode_1
693#if   defined (CONFIG_DDR4_HYNIX_SET_1536)
694    ldr   r2, =0x930023E0                        @ load PLL parameter for 24Mhz CLKIN (384)
695#elif defined (CONFIG_DDR4_HYNIX_SET_1488)
696    ldr   r2, =0x930023C0                        @ load PLL parameter for 24Mhz CLKIN (372)
697#else
698    ldr   r2, =0x930023A0                        @ load PLL parameter for 24Mhz CLKIN (360)
699#endif
700bypass_mpll_hynix_mode_1:
701#endif
702#endif
703
704    mov   r1, r3, lsr #23                        @ Check CLKIN = 25MHz
705    tst   r1, #0x01
706    beq   set_MPLL
707#if   defined (CONFIG_DRAM_1333)
708    ldr   r2, =0xC4806680                        @ load PLL parameter for 25Mhz CLKIN (331)
709#else
710    ldr   r2, =0x930023E0                        @ load PLL parameter for 25Mhz CLKIN (400)
711#if   defined (CONFIG_DDR4_SUPPORT_HYNIX)
712    mov   r1, r3, lsr #24                        @ Check DDR4
713    tst   r1, #0x01
714    beq   bypass_mpll_hynix_mode_2
715#if   defined (CONFIG_DDR4_HYNIX_SET_1536)
716    ldr   r2, =0x930023C0                        @ load PLL parameter for 24Mhz CLKIN (387.5)
717#elif defined (CONFIG_DDR4_HYNIX_SET_1488)
718    ldr   r2, =0x930023A0                        @ load PLL parameter for 24Mhz CLKIN (375)
719#else
720    ldr   r2, =0x93002380                        @ load PLL parameter for 24Mhz CLKIN (362.5)
721#endif
722bypass_mpll_hynix_mode_2:
723#endif
724#endif
725    ldr   r0, =0x1e6e2160                        @ set 24M Jitter divider (HPLL=825MHz)
726    ldr   r1, =0x00011320
727    str   r1, [r0]
728
729set_MPLL:
730    ldr   r0, =0x1e6e2020                        @ M-PLL (DDR SDRAM) Frequency
731    str   r2, [r0]
732
733    clear_delay_timer
734
735    /* Delay about 3ms */
736    ldr   r2, =0x00000BB8                        @ Set Timer3 Reload = 3 ms
737    init_delay_timer
738wait_mpll_init:
739    check_delay_timer
740    bne   wait_mpll_init
741    clear_delay_timer
742    /* end delay 3ms */
743
744    /* Reset MMC */
745reset_mmc:
746    ldr   r0, =0x1e78505c
747    ldr   r1, =0x00000004
748    str   r1, [r0]
749    ldr   r0, =0x1e785044
750    ldr   r1, =0x00000001
751    str   r1, [r0]
752    ldr   r0, =0x1e785048
753    ldr   r1, =0x00004755
754    str   r1, [r0]
755    ldr   r0, =0x1e78504c
756    ldr   r1, =0x00000013
757    str   r1, [r0]
758wait_mmc_reset:
759    ldr   r1, [r0]
760    tst   r1, #0x02
761    bne   wait_mmc_reset
762
763    ldr   r0, =0x1e78505c
764    ldr   r1, =0x023FFFF3
765    str   r1, [r0]
766    ldr   r0, =0x1e785044
767    ldr   r1, =0x000F4240
768    str   r1, [r0]
769    ldr   r0, =0x1e785048
770    ldr   r1, =0x00004755
771    str   r1, [r0]
772    ldr   r0, =0x1e785054
773    ldr   r1, =0x00000077
774    str   r1, [r0]
775
776    ldr   r0, =0x1e6e0000
777    ldr   r1, =0xFC600309
778wait_mmc_reset_done:
779    str   r1, [r0]
780    ldr   r2, [r0]
781    cmp   r2, #0x1
782    bne   wait_mmc_reset_done
783
784    ldr   r0, =0x1e6e0034                        @ disable MMC request
785    ldr   r1, =0x00020000
786    str   r1, [r0]
787
788    /* Delay about 10ms */
789    ldr   r2, =0x00002710                        @ Set Timer3 Reload = 10 ms
790    init_delay_timer
791wait_ddr_reset:
792    check_delay_timer
793    bne   wait_ddr_reset
794    clear_delay_timer
795    /* end delay 10ms */
796
797/* Debug - UART console message */
798#ifdef CONFIG_DRAM_UART_TO_UART1
799    ldr   r0, =0x1e78909c                        @ route UART5 to UART Port1, 2016.08.29
800    ldr   r1, =0x10000004
801    str   r1, [r0]
802
803    ldr   r0, =0x1e6e2084
804    ldr   r1, [r0]
805    mov   r2, #0xC0                              @ Enable pinmux of TXD1/RXD1
806    orr   r1, r1, r2, lsl #16
807    str   r1, [r0]
808#endif
809
810    ldr   r0, =0x1e78400c
811    mov   r1, #0x83
812    str   r1, [r0]
813
814    ldr   r0, =0x1e6e202c
815    ldr   r2, [r0]
816    mov   r2, r2, lsr #12
817    tst   r2, #0x01
818    ldr   r0, =0x1e784000
819    moveq r1, #0x0D                              @ Baudrate 115200
820    movne r1, #0x01                              @ Baudrate 115200, div13
821#ifdef CONFIG_DRAM_UART_38400
822    moveq r1, #0x27                              @ Baudrate 38400
823    movne r1, #0x03                              @ Baudrate 38400 , div13
824#endif
825    str   r1, [r0]
826
827    ldr   r0, =0x1e784004
828    mov   r1, #0x00
829    str   r1, [r0]
830
831    ldr   r0, =0x1e78400c
832    mov   r1, #0x03
833    str   r1, [r0]
834
835    ldr   r0, =0x1e784008
836    mov   r1, #0x07
837    str   r1, [r0]
838
839    ldr   r0, =0x1e784000
840    mov   r1, #0x0D                              @ '\r'
841    str   r1, [r0]
842    mov   r1, #0x0A                              @ '\n'
843    str   r1, [r0]
844    mov   r1, #0x44                              @ 'D'
845    str   r1, [r0]
846    mov   r1, #0x52                              @ 'R'
847    str   r1, [r0]
848    mov   r1, #0x41                              @ 'A'
849    str   r1, [r0]
850    mov   r1, #0x4D                              @ 'M'
851    str   r1, [r0]
852    mov   r1, #0x20                              @ ' '
853    str   r1, [r0]
854    mov   r1, #0x49                              @ 'I'
855    str   r1, [r0]
856    mov   r1, #0x6E                              @ 'n'
857    str   r1, [r0]
858    mov   r1, #0x69                              @ 'i'
859    str   r1, [r0]
860    mov   r1, #0x74                              @ 't'
861    str   r1, [r0]
862    mov   r1, #0x2D                              @ '-'
863    str   r1, [r0]
864    mov   r1, #0x56                              @ 'V'
865    str   r1, [r0]
866    mov   r1, #ASTMMC_INIT_VER
867    mov   r1, r1, lsr #4
868    print_hex_char
869    mov   r1, #ASTMMC_INIT_VER
870    print_hex_char
871    mov   r1, #0x2D                              @ '-'
872    str   r1, [r0]
873    ldr   r0, =0x1e784014
874wait_print:
875    ldr   r1, [r0]
876    tst   r1, #0x40
877    beq   wait_print
878    ldr   r0, =0x1e784000
879    mov   r1, #0x44                              @ 'D'
880    str   r1, [r0]
881    mov   r1, #0x44                              @ 'D'
882    str   r1, [r0]
883    mov   r1, #0x52                              @ 'R'
884    str   r1, [r0]
885/* Debug - UART console message */
886
887/******************************************************************************
888 Init DRAM common registers
889 ******************************************************************************/
890    ldr   r0, =0x1e6e0034                        @ disable SDRAM reset
891    ldr   r1, =0x00020080
892    str   r1, [r0]
893
894    ldr   r0, =0x1e6e0008
895    ldr   r1, =0x2003000F                        /* VGA */
896    str   r1, [r0]
897
898    ldr   r0, =0x1e6e0038                        @ disable all DRAM requests except CPU during PHY init
899    ldr   r1, =0xFFFFEBFF
900    str   r1, [r0]
901
902    ldr   r0, =0x1e6e0040
903    ldr   r1, =0x88448844
904    str   r1, [r0]
905
906    ldr   r0, =0x1e6e0044
907    ldr   r1, =0x24422288
908    str   r1, [r0]
909
910    ldr   r0, =0x1e6e0048
911    ldr   r1, =0x22222222
912    str   r1, [r0]
913
914    ldr   r0, =0x1e6e004c
915    ldr   r1, =0x22222222
916    str   r1, [r0]
917
918    ldr   r0, =0x1e6e0050
919    ldr   r1, =0x80000000
920    str   r1, [r0]
921
922    ldr   r1, =0x00000000
923    ldr   r0, =0x1e6e0208                        @ PHY Setting
924    str   r1, [r0]
925    ldr   r0, =0x1e6e0218
926    str   r1, [r0]
927    ldr   r0, =0x1e6e0220
928    str   r1, [r0]
929    ldr   r0, =0x1e6e0228
930    str   r1, [r0]
931    ldr   r0, =0x1e6e0230
932    str   r1, [r0]
933    ldr   r0, =0x1e6e02a8
934    str   r1, [r0]
935    ldr   r0, =0x1e6e02b0
936    str   r1, [r0]
937
938    ldr   r0, =0x1e6e0240
939    ldr   r1, =0x86000000
940    str   r1, [r0]
941
942    ldr   r0, =0x1e6e0244
943    ldr   r1, =0x00008600
944    str   r1, [r0]
945
946    ldr   r0, =0x1e6e0248
947    ldr   r1, =0x80000000
948    str   r1, [r0]
949
950    ldr   r0, =0x1e6e024c
951    ldr   r1, =0x80808080
952    str   r1, [r0]
953
954    /* Check DRAM Type by H/W Trapping */
955    ldr   r0, =0x1e6e2070
956    ldr   r1, [r0]
957    ldr   r2, =0x01000000                        @ bit[24]=1 => DDR4
958    tst   r1, r2
959    bne   ddr4_init
960    b     ddr3_init
961.LTORG
962
963/******************************************************************************
964 DDR3 Init
965 ******************************************************************************/
966ddr3_init:
967/* Debug - UART console message */
968    ldr   r0, =0x1e784000
969    mov   r1, #0x33                              @ '3'
970    str   r1, [r0]
971    mov   r1, #0x0D                              @ '\r'
972    str   r1, [r0]
973    mov   r1, #0x0A                              @ '\n'
974    str   r1, [r0]
975/* Debug - UART console message */
976
977#if   defined (CONFIG_DRAM_1333)
978    adrl  r5, TIME_TABLE_DDR3_1333               @ Init DRAM parameter table
979#else
980    adrl  r5, TIME_TABLE_DDR3_1600
981#endif
982
983    ldr   r0, =0x1e6e0004
984#ifdef CONFIG_DDR3_8GSTACK
985    ldr   r1, =0x00000323                        @ Init to 8GB stack
986#else
987    ldr   r1, =0x00000303                        @ Init to 8GB
988#endif
989    str   r1, [r0]
990
991    ldr   r0, =0x1e6e0010
992    ldr   r1, [r5, #ASTMMC_REGIDX_010]
993    str   r1, [r0]
994
995    ldr   r0, =0x1e6e0014
996    ldr   r1, [r5, #ASTMMC_REGIDX_014]
997    str   r1, [r0]
998
999    ldr   r0, =0x1e6e0018
1000    ldr   r1, [r5, #ASTMMC_REGIDX_018]
1001    str   r1, [r0]
1002
1003    /* DRAM Mode Register Setting */
1004    ldr   r0, =0x1e6e0020                        @ MRS_4/6
1005    ldr   r1, [r5, #ASTMMC_REGIDX_020]
1006    str   r1, [r0]
1007
1008    ldr   r0, =0x1e6e0024                        @ MRS_5
1009    ldr   r1, [r5, #ASTMMC_REGIDX_024]
1010    str   r1, [r0]
1011
1012    ldr   r0, =0x1e6e002c                        @ MRS_0/2
1013    ldr   r1, [r5, #ASTMMC_REGIDX_02C]
1014    mov   r2, #0x1
1015    orr   r1, r1, r2, lsl #8
1016    str   r1, [r0]
1017
1018    ldr   r0, =0x1e6e0030                        @ MRS_1/3
1019    ldr   r1, [r5, #ASTMMC_REGIDX_030]
1020    str   r1, [r0]
1021
1022    /* Start DDR PHY Setting */
1023    ldr   r0, =0x1e6e0200
1024    ldr   r1, =0x02492AAE
1025    str   r1, [r0]
1026
1027    ldr   r0, =0x1e6e0204
1028#ifdef CONFIG_DDR3_8GSTACK
1029    ldr   r1, =0x10001001
1030#else
1031    ldr   r1, =0x00001001
1032#endif
1033    str   r1, [r0]
1034
1035    ldr   r0, =0x1e6e020c
1036    ldr   r1, =0x55E00B0B
1037    str   r1, [r0]
1038
1039    ldr   r0, =0x1e6e0210
1040    ldr   r1, =0x20000000
1041    str   r1, [r0]
1042
1043    ldr   r0, =0x1e6e0214
1044    ldr   r1, [r5, #ASTMMC_REGIDX_214]
1045    str   r1, [r0]
1046
1047    ldr   r0, =0x1e6e02e0
1048    ldr   r1, [r5, #ASTMMC_REGIDX_2E0]
1049    str   r1, [r0]
1050
1051    ldr   r0, =0x1e6e02e4
1052    ldr   r1, [r5, #ASTMMC_REGIDX_2E4]
1053    str   r1, [r0]
1054
1055    ldr   r0, =0x1e6e02e8
1056    ldr   r1, [r5, #ASTMMC_REGIDX_2E8]
1057    str   r1, [r0]
1058
1059    ldr   r0, =0x1e6e02ec
1060    ldr   r1, [r5, #ASTMMC_REGIDX_2EC]
1061    str   r1, [r0]
1062
1063    ldr   r0, =0x1e6e02f0
1064    ldr   r1, [r5, #ASTMMC_REGIDX_2F0]
1065    str   r1, [r0]
1066
1067    ldr   r0, =0x1e6e02f4
1068    ldr   r1, [r5, #ASTMMC_REGIDX_2F4]
1069    str   r1, [r0]
1070
1071    ldr   r0, =0x1e6e02f8
1072    ldr   r1, [r5, #ASTMMC_REGIDX_2F8]
1073    str   r1, [r0]
1074
1075    ldr   r0, =0x1e6e0290
1076    ldr   r1, =0x00100008
1077    str   r1, [r0]
1078
1079    ldr   r0, =0x1e6e02c0
1080    ldr   r1, =0x00000006
1081    str   r1, [r0]
1082
1083    /* Controller Setting */
1084    ldr   r0, =0x1e6e0060                        @ Fire DDRPHY Init
1085    ldr   r1, =0x00000005
1086    str   r1, [r0]
1087
1088    ldr   r0, =0x1e6e0034
1089    ldr   r1, =0x00020091
1090    str   r1, [r0]
1091
1092/* Debug - UART console message */
1093    ldr   r0, =0x1e784000
1094    mov   r1, #0x30                              @ '0'
1095    str   r1, [r0]
1096/* Debug - UART console message */
1097
1098    ldr   r0, =0x1e6e0120
1099    mov   r1, #0x00
1100    str   r1, [r0]
1101    b     ddr_phy_init_process
1102
1103ddr3_phyinit_done:
1104
1105    /********************************************
1106     Check Read training margin
1107    ********************************************/
1108    ldr   r0, =0x1e6e03a0                        @ check Gate Training Pass Window
1109    ldr   r1, [r0]
1110    ldr   r2, =0x150
1111    bic   r0, r1, #0xFF000000
1112    bic   r0, r0, #0x00FF0000
1113    cmp   r0, r2
1114    blt   ddr_test_fail
1115    mov   r0, r1, lsr #16
1116    cmp   r0, r2
1117    blt   ddr_test_fail
1118
1119    ldr   r0, =0x1e6e03d0                        @ check Read Data Eye Training Pass Window
1120    ldr   r1, [r0]
1121    ldr   r2, =0x90
1122    bic   r0, r1, #0x0000FF00
1123    cmp   r0, r2
1124    blt   ddr_test_fail
1125    mov   r0, r1, lsr #8
1126    cmp   r0, r2
1127    blt   ddr_test_fail
1128    /*******************************************/
1129
1130/* Debug - UART console message */
1131    ldr   r0, =0x1e784000
1132    mov   r1, #0x31                              @ '1'
1133    str   r1, [r0]
1134/* Debug - UART console message */
1135
1136    ldr   r0, =0x1e6e000c
1137    ldr   r1, =0x00000040
1138    str   r1, [r0]
1139
1140#ifdef CONFIG_DDR3_8GSTACK
1141    ldr   r0, =0x1e6e0028
1142    ldr   r1, =0x00000025
1143    str   r1, [r0]
1144
1145    ldr   r0, =0x1e6e0028
1146    ldr   r1, =0x00000027
1147    str   r1, [r0]
1148
1149    ldr   r0, =0x1e6e0028
1150    ldr   r1, =0x00000023
1151    str   r1, [r0]
1152
1153    ldr   r0, =0x1e6e0028
1154    ldr   r1, =0x00000021
1155    str   r1, [r0]
1156#endif
1157
1158    ldr   r0, =0x1e6e0028
1159    ldr   r1, =0x00000005
1160    str   r1, [r0]
1161
1162    ldr   r0, =0x1e6e0028
1163    ldr   r1, =0x00000007
1164    str   r1, [r0]
1165
1166    ldr   r0, =0x1e6e0028
1167    ldr   r1, =0x00000003
1168    str   r1, [r0]
1169
1170    ldr   r0, =0x1e6e0028
1171    ldr   r1, =0x00000011
1172    str   r1, [r0]
1173
1174    ldr   r0, =0x1e6e000c
1175    ldr   r1, =0x00005C41
1176    str   r1, [r0]
1177
1178    ldr   r0, =0x1e6e0034
1179    ldr   r2, =0x70000000
1180ddr3_check_dllrdy:
1181    ldr   r1, [r0]
1182    tst   r1, r2
1183    bne   ddr3_check_dllrdy
1184
1185    ldr   r0, =0x1e6e000c
1186#ifdef CONFIG_DRAM_EXT_TEMP
1187    ldr   r1, =0x42AA2F81
1188#else
1189    ldr   r1, =0x42AA5C81
1190#endif
1191    str   r1, [r0]
1192
1193    ldr   r0, =0x1e6e0034
1194    ldr   r1, =0x0001AF93
1195    str   r1, [r0]
1196
1197    ldr   r0, =0x1e6e0120                        @ VGA Compatible Mode
1198    ldr   r1, [r5, #ASTMMC_REGIDX_PLL]
1199    str   r1, [r0]
1200
1201    b     Calibration_End
1202.LTORG
1203/******************************************************************************
1204 End DDR3 Init
1205 ******************************************************************************/
1206/******************************************************************************
1207 DDR4 Init
1208 ******************************************************************************/
1209ddr4_init:
1210/* Debug - UART console message */
1211    ldr   r0, =0x1e784000
1212    mov   r1, #0x34                              @ '4'
1213    str   r1, [r0]
1214    mov   r1, #0x0D                              @ '\r'
1215    str   r1, [r0]
1216    mov   r1, #0x0A                              @ '\n'
1217    str   r1, [r0]
1218/* Debug - UART console message */
1219
1220#if   defined (CONFIG_DRAM_1333)
1221    adrl  r5, TIME_TABLE_DDR4_1333               @ Init DRAM parameter table
1222#else
1223    adrl  r5, TIME_TABLE_DDR4_1600
1224#endif
1225
1226    ldr   r0, =0x1e6e0004
1227#ifdef CONFIG_DDR4_4GX8
1228    ldr   r1, =0x00002313                        @ Init to 8GB
1229#else
1230    ldr   r1, =0x00000313                        @ Init to 8GB
1231#endif
1232    str   r1, [r0]
1233
1234    ldr   r0, =0x1e6e0010
1235    ldr   r1, [r5, #ASTMMC_REGIDX_010]
1236    str   r1, [r0]
1237
1238    ldr   r0, =0x1e6e0014
1239    ldr   r1, [r5, #ASTMMC_REGIDX_014]
1240    str   r1, [r0]
1241
1242    ldr   r0, =0x1e6e0018
1243    ldr   r1, [r5, #ASTMMC_REGIDX_018]
1244    str   r1, [r0]
1245
1246    /* DRAM Mode Register Setting */
1247    ldr   r0, =0x1e6e0020                        @ MRS_4/6
1248    ldr   r1, [r5, #ASTMMC_REGIDX_020]
1249    str   r1, [r0]
1250
1251    ldr   r0, =0x1e6e0024                        @ MRS_5
1252    ldr   r1, [r5, #ASTMMC_REGIDX_024]
1253    str   r1, [r0]
1254
1255    ldr   r0, =0x1e6e002c                        @ MRS_0/2
1256    ldr   r1, [r5, #ASTMMC_REGIDX_02C]
1257    mov   r2, #0x1
1258    orr   r1, r1, r2, lsl #8
1259    str   r1, [r0]
1260
1261    ldr   r0, =0x1e6e0030                        @ MRS_1/3
1262    ldr   r1, [r5, #ASTMMC_REGIDX_030]
1263    str   r1, [r0]
1264
1265    /* Start DDR PHY Setting */
1266    ldr   r0, =0x1e6e0200
1267    ldr   r1, =0x42492AAE
1268    str   r1, [r0]
1269
1270    ldr   r0, =0x1e6e0204
1271    ldr   r1, =0x09002800
1272    str   r1, [r0]
1273
1274    ldr   r0, =0x1e6e020c
1275    ldr   r1, =0x55E00B0B
1276    str   r1, [r0]
1277
1278    ldr   r0, =0x1e6e0210
1279    ldr   r1, =0x20000000
1280    str   r1, [r0]
1281
1282    ldr   r0, =0x1e6e0214
1283    ldr   r1, [r5, #ASTMMC_REGIDX_214]
1284    str   r1, [r0]
1285
1286    ldr   r0, =0x1e6e02e0
1287    ldr   r1, [r5, #ASTMMC_REGIDX_2E0]
1288    str   r1, [r0]
1289
1290    ldr   r0, =0x1e6e02e4
1291    ldr   r1, [r5, #ASTMMC_REGIDX_2E4]
1292    str   r1, [r0]
1293
1294    ldr   r0, =0x1e6e02e8
1295    ldr   r1, [r5, #ASTMMC_REGIDX_2E8]
1296    str   r1, [r0]
1297
1298    ldr   r0, =0x1e6e02ec
1299    ldr   r1, [r5, #ASTMMC_REGIDX_2EC]
1300    str   r1, [r0]
1301
1302    ldr   r0, =0x1e6e02f0
1303    ldr   r1, [r5, #ASTMMC_REGIDX_2F0]
1304    str   r1, [r0]
1305
1306    ldr   r0, =0x1e6e02f4
1307    ldr   r1, [r5, #ASTMMC_REGIDX_2F4]
1308    str   r1, [r0]
1309
1310    ldr   r0, =0x1e6e02f8
1311    ldr   r1, [r5, #ASTMMC_REGIDX_2F8]
1312    str   r1, [r0]
1313
1314    ldr   r0, =0x1e6e0290
1315    ldr   r1, =0x00100008
1316    str   r1, [r0]
1317
1318    ldr   r0, =0x1e6e02c4
1319    ldr   r1, =0x3C183C3C
1320    str   r1, [r0]
1321
1322    ldr   r0, =0x1e6e02c8
1323    ldr   r1, =0x00631E0E
1324    str   r1, [r0]
1325
1326    ldr   r0, =0x1e6e0034
1327    ldr   r1, =0x0001A991
1328    str   r1, [r0]
1329
1330/* Debug - UART console message */
1331    ldr   r0, =0x1e784000
1332    mov   r1, #0x30                              @ '0'
1333    str   r1, [r0]
1334/* Debug - UART console message */
1335
1336    /********************************************
1337     Set Ron value to manual mode
1338     Target to fix DDR CK Vix issue
1339     Set Ron_pu = 0, Ron_pd = trained value
1340     *******************************************/
1341#ifdef ASTMMC_DDR4_MANUAL_RPU
1342    ldr   r0, =0x1e6e02c0
1343    ldr   r1, =0x00001806
1344    str   r1, [r0]
1345    ldr   r0, =0x1e6e02cc
1346    ldr   r1, =0x00005050
1347    str   r1, [r0]
1348    ldr   r0, =0x1e6e0120
1349    mov   r1, #0x04
1350    str   r1, [r0]
1351    ldr   r0, =0x1e6e0060                        @ Fire DDRPHY Init
1352    mov   r1, #0x05
1353    str   r1, [r0]
1354    b     ddr_phy_init_process
1355
1356ddr4_ron_phyinit_done:
1357
1358    ldr   r0, =0x1e6e0300                        @ read calibrated Ron_pd
1359    ldr   r3, [r0]
1360    bic   r3, r3, #0xFFFFFF0F
1361    ldr   r0, =0x1e6e0240
1362    ldr   r1, [r0]
1363    bic   r1, r1, #0xFF000000
1364    mov   r2, #ASTMMC_DDR4_MANUAL_RPU
1365    orr   r1, r1, r2, lsl #24
1366#ifdef ASTMMC_DDR4_MANUAL_RPD
1367    mov   r2, #ASTMMC_DDR4_MANUAL_RPD
1368    orr   r1, r1, r2, lsl #28
1369#else
1370    orr   r1, r1, r3, lsl #24
1371#endif
1372    orr   r1, r1, #0x02
1373    str   r1, [r0]
1374
1375    ldr   r0, =0x1e6e0060                        @ Reset PHY
1376    mov   r1, #0x00
1377    str   r1, [r0]
1378#endif
1379    /********************************************
1380     PHY Vref Scan
1381     r6 : recorded vref value
1382     r7 : max read eye pass window
1383     r8 : passcnt
1384     r9 : CBRtest result
1385     r10: loopcnt
1386     r11: free
1387    ********************************************/
1388    ldr   r0, =0x1e720000                        @ retry count
1389    mov   r1, #0x5
1390    str   r1, [r0]
1391ddr4_vref_phy_cal_start:
1392    mov   r7, #0x0
1393    mov   r8, #0x0
1394    mov   r10, #0x3F
1395
1396    ldr   r0, =0x1e720000
1397    ldr   r1, [r0]
1398    subs  r1, r1, #0x01
1399    beq   ddr_test_fail
1400    str   r1, [r0]
1401
1402    ldr   r0, =0x1e6e0120
1403    ldr   r1, =0x00000001
1404    str   r1, [r0]
1405
1406/* Debug - UART console message */
1407    ldr   r0, =0x1e784000
1408    mov   r1, #0x61                              @ 'a'
1409    str   r1, [r0]
1410/* Debug - UART console message */
1411
1412    ldr   r0, =0x1e6e02c0
1413    ldr   r1, =0x00001C06
1414    str   r1, [r0]
1415
1416ddr4_vref_phy_loop:
1417    ldr   r0, =0x1e6e0060
1418    ldr   r1, =0x00000000
1419    str   r1, [r0]
1420
1421    add   r10, r10, #0x01
1422    cmp   r10, #0x80
1423    beq   ddr4_vref_phy_test_fail                @ no valid margin and retry
1424
1425    ldr   r0, =0x1e6e02cc
1426    orr   r1, r10, r10, lsl #8
1427    str   r1, [r0]
1428
1429    ldr   r0, =0x1e6e0060
1430    ldr   r1, =0x00000005
1431    str   r1, [r0]
1432    b     ddr_phy_init_process
1433
1434ddr4_vref_phy_phyinit_done:
1435
1436    b     cbr_test_start
1437
1438ddr4_vref_phy_cbrtest_done:
1439    ldr   r0, =0x1e6e03d0                        @ read eye pass window
1440    ldr   r1, [r0]
1441    ldr   r0, =0x1e720000
1442    add   r0, r0, r10, lsl #2
1443    str   r1, [r0]
1444    cmp   r9, #0x01
1445    bne   ddr4_vref_phy_test_fail
1446    add   r8, r8, #0x01
1447    ldr   r0, =0x1e6e03d0                        @ read eye pass window
1448    ldr   r1, [r0]
1449    mov   r2, r1, lsr #8                         @ r2 = DQH
1450    and   r1, r1, #0xFF                          @ r1 = DQL
1451    cmp   r1, r2
1452    movgt r1, r2                                 @ r1 = smaller one
1453    cmp   r1, r7
1454    movgt r6, r10
1455    movgt r7, r1
1456    b     ddr4_vref_phy_loop
1457
1458ddr4_vref_phy_test_fail:
1459    cmp   r8, #0x0
1460    bne   ddr4_vref_phy_loop_end
1461    cmp   r10, #0x80
1462    beq   ddr4_vref_phy_cal_start
1463    b     ddr4_vref_phy_loop
1464
1465ddr4_vref_phy_loop_end:
1466    cmp   r8, #16                                @ check phyvref margin >= 16
1467    blt   ddr_test_fail
1468    ldr   r0, =0x1e6e02cc
1469    orr   r1, r6, r6, lsl #8
1470    str   r1, [r0]
1471    ldr   r0, =0x1e720010
1472    orr   r1, r6, r7, lsl #8
1473    orr   r1, r1, r8, lsl #16
1474    str   r1, [r0]
1475
1476    /********************************************
1477     DDR Vref Scan
1478     r6 : min
1479     r7 : max
1480     r8 : passcnt
1481     r9 : CBRtest result
1482     r10: loopcnt
1483     r11: free
1484    ********************************************/
1485    ldr   r0, =0x1e720000                        @ retry count
1486    mov   r1, #0x5
1487    str   r1, [r0]
1488ddr4_vref_ddr_cal_start:
1489    mov   r6, #0xFF
1490    mov   r7, #0x0
1491    mov   r8, #0x0
1492    mov   r10, #0x0
1493
1494    ldr   r0, =0x1e720000
1495    ldr   r1, [r0]
1496    subs  r1, r1, #0x01
1497    beq   ddr_test_fail
1498    str   r1, [r0]
1499
1500    ldr   r0, =0x1e6e0120
1501    ldr   r1, =0x00000002
1502    str   r1, [r0]
1503
1504/* Debug - UART console message */
1505    ldr   r0, =0x1e784000
1506    mov   r1, #0x62                              @ 'b'
1507    str   r1, [r0]
1508/* Debug - UART console message */
1509
1510ddr4_vref_ddr_loop:
1511    ldr   r0, =0x1e6e0060
1512    ldr   r1, =0x00000000
1513    str   r1, [r0]
1514
1515    add   r10, r10, #0x01
1516    cmp   r10, #0x40
1517    beq   ddr4_vref_ddr_test_fail                @ no valid margin and retry
1518
1519    ldr   r0, =0x1e6e02c0
1520    mov   r1, #0x06
1521    orr   r1, r1, r10, lsl #8
1522    str   r1, [r0]
1523
1524    ldr   r0, =0x1e6e0060
1525    ldr   r1, =0x00000005
1526    str   r1, [r0]
1527    b     ddr_phy_init_process
1528
1529ddr4_vref_ddr_phyinit_done:
1530
1531    b     cbr_test_start
1532
1533ddr4_vref_ddr_cbrtest_done:
1534    cmp   r9, #0x01
1535    bne   ddr4_vref_ddr_test_fail
1536    add   r8, r8, #0x01
1537    cmp   r6, r10
1538    movgt r6, r10
1539    cmp   r7, r10
1540    movlt r7, r10
1541    b     ddr4_vref_ddr_loop
1542
1543ddr4_vref_ddr_test_fail:
1544    cmp   r8, #0x0
1545    bne   ddr4_vref_ddr_loop_end
1546    cmp   r10, #0x40
1547    beq   ddr4_vref_ddr_cal_start
1548    b     ddr4_vref_ddr_loop
1549
1550ddr4_vref_ddr_loop_end:
1551    ldr   r0, =0x1e6e0060
1552    ldr   r1, =0x00000000
1553    str   r1, [r0]
1554
1555    cmp   r8, #16                                @ check ddrvref margin >= 16
1556    blt   ddr_test_fail
1557    ldr   r0, =0x1e6e02c0
1558    add   r1, r6, r7
1559    add   r1, r1, #0x01
1560    mov   r2, r1, lsr #1
1561    mov   r1, r2, lsl #8
1562    orr   r1, r1, #0x06
1563    str   r1, [r0]
1564    ldr   r0, =0x1e720014
1565    orr   r1, r6, r7, lsl #8
1566    orr   r1, r1, r8, lsl #16
1567    str   r1, [r0]
1568
1569/* Debug - UART console message */
1570    ldr   r0, =0x1e784000
1571    mov   r1, #0x63                              @ 'c'
1572    str   r1, [r0]
1573/* Debug - UART console message */
1574
1575    ldr   r0, =0x1e6e0120
1576    ldr   r1, =0x00000003
1577    str   r1, [r0]
1578
1579    ldr   r0, =0x1e6e0060                        @ Fire DDRPHY Init
1580    ldr   r1, =0x00000005
1581    str   r1, [r0]
1582    b     ddr_phy_init_process
1583
1584ddr4_phyinit_done:
1585
1586    /********************************************
1587     Check Read training margin
1588    ********************************************/
1589    ldr   r0, =0x1e6e03a0                        @ check Gate Training Pass Window
1590    ldr   r1, [r0]
1591    ldr   r2, =0x150
1592    bic   r0, r1, #0xFF000000
1593    bic   r0, r0, #0x00FF0000
1594    cmp   r0, r2
1595    blt   ddr_test_fail
1596    mov   r0, r1, lsr #16
1597    cmp   r0, r2
1598    blt   ddr_test_fail
1599
1600    ldr   r0, =0x1e6e03d0                        @ check Read Data Eye Training Pass Window
1601    ldr   r1, [r0]
1602    ldr   r2, =0x90
1603    bic   r0, r1, #0x0000FF00
1604    cmp   r0, r2
1605    blt   ddr_test_fail
1606    mov   r0, r1, lsr #8
1607    cmp   r0, r2
1608    blt   ddr_test_fail
1609    /*******************************************/
1610
1611    /*******************************************/
1612/* Debug - UART console message */
1613    ldr   r0, =0x1e784000
1614    mov   r1, #0x31                              @ '1'
1615    str   r1, [r0]
1616/* Debug - UART console message */
1617
1618    ldr   r0, =0x1e6e000c
1619#ifdef CONFIG_DRAM_EXT_TEMP
1620    ldr   r1, =0x42AA2F81
1621#else
1622    ldr   r1, =0x42AA5C81
1623#endif
1624    str   r1, [r0]
1625
1626    ldr   r0, =0x1e6e0034
1627    ldr   r1, =0x0001AF93
1628    str   r1, [r0]
1629
1630    ldr   r0, =0x1e6e0120                        @ VGA Compatible Mode
1631    ldr   r1, [r5, #ASTMMC_REGIDX_PLL]
1632    str   r1, [r0]
1633
1634    b     Calibration_End
1635
1636.LTORG
1637/******************************************************************************
1638 End DDR4 Init
1639 ******************************************************************************/
1640/******************************************************************************
1641 Global Process
1642 ******************************************************************************/
1643    /********************************************
1644     DDRPHY Init Process
1645    ********************************************/
1646ddr_phy_init_process:
1647    clear_delay_timer
1648    /* Wait DDR PHY init done - timeout 300 ms */
1649    ldr   r2, =0x000493E0                        @ Set Timer3 Reload = 300 ms
1650    init_delay_timer
1651    ldr   r3, =0x1e6e0060
1652ddr_phy_init:
1653    check_delay_timer
1654    beq   ddr_phy_init_timeout
1655    ldr   r1, [r3]
1656    tst   r1, #0x01
1657    bne   ddr_phy_init
1658
1659    /* Check DDR PHY init status */
1660    ldr   r0, =0x1e6e0300
1661    ldr   r2, =0x000A0000
1662    ldr   r1, [r0]
1663    tst   r1, r2
1664    beq   ddr_phy_init_success
1665
1666ddr_phy_init_timeout:
1667    ldr   r0, =0x1e6e0060                        @ Reset PHY
1668    mov   r1, #0x00
1669    str   r1, [r0]
1670
1671/* Debug - UART console message */
1672    ldr   r0, =0x1e784000
1673    mov   r1, #0x2E                              @ '.'
1674    str   r1, [r0]
1675/* Debug - UART console message */
1676
1677    clear_delay_timer
1678    /* Delay about 10us */
1679    ldr   r2, =0x0000000A                        @ Set Timer3 Reload = 10 us
1680    init_delay_timer
1681ddr_phy_init_delay_0:
1682    check_delay_timer
1683    bne   ddr_phy_init_delay_0
1684    clear_delay_timer
1685    /* end delay 10us */
1686
1687    ldr   r0, =0x1e6e0060                        @ Fire PHY Init
1688    mov   r1, #0x05
1689    str   r1, [r0]
1690    b     ddr_phy_init_process
1691
1692ddr_phy_init_success:
1693    clear_delay_timer
1694    ldr   r0, =0x1e6e0060
1695    mov   r1, #0x06
1696    str   r1, [r0]
1697
1698    ldr   r0, =0x1e6e0120
1699    ldr   r1, [r0]
1700    cmp   r1, #0
1701    beq   ddr3_phyinit_done
1702    cmp   r1, #1
1703    beq   ddr4_vref_phy_phyinit_done
1704    cmp   r1, #2
1705    beq   ddr4_vref_ddr_phyinit_done
1706#ifdef ASTMMC_DDR4_MANUAL_RPU
1707    cmp   r1, #4
1708    beq   ddr4_ron_phyinit_done
1709#endif
1710    b     ddr4_phyinit_done
1711
1712    /********************************************
1713     CBRTest
1714    ********************************************/
1715cbr_test_start:
1716    ldr   r0, =0x1e6e000c
1717    ldr   r1, =0x00005C01
1718    str   r1, [r0]
1719    ldr   r0, =0x1e6e0074
1720    ldr   r1, =0x0000FFFF                        @ test size = 64KB
1721    str   r1, [r0]
1722    ldr   r0, =0x1e6e007c
1723    ldr   r1, =0xFF00FF00
1724    str   r1, [r0]
1725
1726cbr_test_single:
1727    ldr   r0, =0x1e6e0070
1728    ldr   r1, =0x00000000
1729    str   r1, [r0]
1730    ldr   r1, =0x00000085
1731    str   r1, [r0]
1732    ldr   r3, =0x3000
1733    ldr   r11, =0x50000
1734cbr_wait_engine_idle_0:
1735    subs  r11, r11, #1
1736    beq   cbr_test_fail
1737    ldr   r2, [r0]
1738    tst   r2, r3                                 @ D[12] = idle bit
1739    beq   cbr_wait_engine_idle_0
1740
1741    ldr   r0, =0x1e6e0070                        @ read fail bit status
1742    ldr   r3, =0x2000
1743    ldr   r2, [r0]
1744    tst   r2, r3                                 @ D[13] = fail bit
1745    bne   cbr_test_fail
1746
1747cbr_test_burst:
1748    mov   r1, #0x00                              @ initialize loop index, r1 is loop index
1749cbr_test_burst_loop:
1750    ldr   r0, =0x1e6e0070
1751    ldr   r2, =0x00000000
1752    str   r2, [r0]
1753    mov   r2, r1, lsl #3
1754    orr   r2, r2, #0xC1                          @ test command = 0xC1 | (datagen << 3)
1755    str   r2, [r0]
1756    ldr   r3, =0x3000
1757    ldr   r11, =0x20000
1758cbr_wait_engine_idle_1:
1759    subs  r11, r11, #1
1760    beq   cbr_test_fail
1761    ldr   r2, [r0]
1762    tst   r2, r3                                 @ D[12] = idle bit
1763    beq   cbr_wait_engine_idle_1
1764
1765    ldr   r0, =0x1e6e0070                        @ read fail bit status
1766    ldr   r3, =0x2000
1767    ldr   r2, [r0]
1768    tst   r2, r3                                 @ D[13] = fail bit
1769    bne   cbr_test_fail
1770
1771    add   r1, r1, #1                             @ increase the test mode index
1772    cmp   r1, #0x04                              @ test 4 modes
1773    bne   cbr_test_burst_loop
1774
1775    ldr   r0, =0x1e6e0070
1776    ldr   r1, =0x00000000
1777    str   r1, [r0]
1778    mov   r9, #0x1
1779    b     cbr_test_pattern_end                   @ CBRTest() return(1)
1780
1781cbr_test_fail:
1782    ldr   r0, =0x1e6e0070
1783    ldr   r1, =0x00000000
1784    str   r1, [r0]
1785    mov   r9, #0x0                               @ CBRTest() return(0)
1786
1787cbr_test_pattern_end:
1788    ldr   r0, =0x1e6e000c
1789    ldr   r1, =0x00000000
1790    str   r1, [r0]
1791    ldr   r0, =0x1e6e0120
1792    ldr   r1, [r0]
1793    cmp   r1, #1
1794    beq   ddr4_vref_phy_cbrtest_done
1795    b     ddr4_vref_ddr_cbrtest_done
1796
1797.LTORG
1798/******************************************************************************
1799 Other features configuration
1800 *****************************************************************************/
1801Calibration_End:
1802    /*******************************
1803     Check DRAM Size
1804     1Gb : 0x80000000 ~ 0x87FFFFFF
1805     2Gb : 0x80000000 ~ 0x8FFFFFFF
1806     4Gb : 0x80000000 ~ 0x9FFFFFFF
1807     8Gb : 0x80000000 ~ 0xBFFFFFFF
1808    *******************************/
1809    ldr   r0, =0x1e6e0004
1810    ldr   r6, [r0]
1811    bic   r6, r6, #0x00000003                    @ record MCR04
1812    ldr   r7, [r5, #ASTMMC_REGIDX_RFC]
1813
1814check_dram_size:
1815    ldr   r0, =0xA0100000
1816    ldr   r1, =0x41424344
1817    str   r1, [r0]
1818    ldr   r0, =0x90100000
1819    ldr   r1, =0x35363738
1820    str   r1, [r0]
1821    ldr   r0, =0x88100000
1822    ldr   r1, =0x292A2B2C
1823    str   r1, [r0]
1824    ldr   r0, =0x80100000
1825    ldr   r1, =0x1D1E1F10
1826    str   r1, [r0]
1827    ldr   r0, =0xA0100000
1828    ldr   r1, =0x41424344
1829    ldr   r2, [r0]
1830    cmp   r2, r1                                 @ == 8Gbit
1831    orreq r6, r6, #0x03
1832    moveq r7, r7, lsr #24
1833    mov   r3, #0x38                              @ '8'
1834    beq   check_dram_size_end
1835    ldr   r0, =0x90100000
1836    ldr   r1, =0x35363738
1837    ldr   r2, [r0]
1838    cmp   r2, r1                                 @ == 4Gbit
1839    orreq r6, r6, #0x02
1840    moveq r7, r7, lsr #16
1841    mov   r3, #0x34                              @ '4'
1842    beq   check_dram_size_end
1843    ldr   r0, =0x88100000
1844    ldr   r1, =0x292A2B2C
1845    ldr   r2, [r0]
1846    cmp   r2, r1                                 @ == 2Gbit
1847    orreq r6, r6, #0x01
1848    moveq r7, r7, lsr #8
1849    mov   r3, #0x32                              @ '2'
1850    beq   check_dram_size_end
1851    mov   r3, #0x31                              @ '1'
1852
1853check_dram_size_end:
1854    ldr   r0, =0x1e6e0004
1855    str   r6, [r0]
1856    ldr   r0, =0x1e6e0014
1857    ldr   r1, [r0]
1858    bic   r1, r1, #0x000000FF
1859    and   r7, r7, #0xFF
1860    orr   r1, r1, r7
1861    str   r1, [r0]
1862
1863    /* Version Number */
1864    ldr   r0, =0x1e6e0004
1865    ldr   r1, [r0]
1866    mov   r2, #ASTMMC_INIT_VER
1867    orr   r1, r1, r2, lsl #20
1868    str   r1, [r0]
1869
1870    ldr   r0, =0x1e6e0088
1871    ldr   r1, =ASTMMC_INIT_DATE
1872    str   r1, [r0]
1873
1874/* Debug - UART console message */
1875    ldr   r0, =0x1e784000
1876    mov   r1, #0x2D                              @ '-'
1877    str   r1, [r0]
1878    str   r3, [r0]
1879    mov   r1, #0x47                              @ 'G'
1880    str   r1, [r0]
1881    mov   r1, #0x62                              @ 'b'
1882    str   r1, [r0]
1883    mov   r1, #0x2D                              @ '-'
1884    str   r1, [r0]
1885/* Debug - UART console message */
1886
1887    /* Enable DRAM Cache */
1888    ldr   r0, =0x1e6e0004
1889    ldr   r1, [r0]
1890    mov   r2, #1
1891    orr   r2, r1, r2, lsl #12
1892    str   r2, [r0]
1893    ldr   r3, =0x00080000
1894dram_cache_init:
1895    ldr   r2, [r0]
1896    tst   r2, r3
1897    beq   dram_cache_init
1898    mov   r2, #1
1899    orr   r1, r1, r2, lsl #10
1900    str   r1, [r0]
1901
1902    /* Set DRAM requests threshold */
1903    ldr   r0, =0x1e6e001c
1904    ldr   r1, =0x00000008
1905    str   r1, [r0]
1906    ldr   r0, =0x1e6e0038
1907    ldr   r1, =0xFFFFFF00
1908    str   r1, [r0]
1909
1910    /********************************************
1911     DDRTest
1912    ********************************************/
1913ddr_test_start:
1914    ldr   r0, =0x1e6e0074
1915    ldr   r1, =0x0000FFFF                        @ test size = 64KB
1916    str   r1, [r0]
1917    ldr   r0, =0x1e6e007c
1918    ldr   r1, =0xFF00FF00
1919    str   r1, [r0]
1920
1921ddr_test_burst:
1922    mov   r1, #0x00                              @ initialize loop index, r1 is loop index
1923ddr_test_burst_loop:
1924    ldr   r0, =0x1e6e0070
1925    ldr   r2, =0x00000000
1926    str   r2, [r0]
1927    mov   r2, r1, lsl #3
1928    orr   r2, r2, #0xC1                          @ test command = 0xC1 | (datagen << 3)
1929    str   r2, [r0]
1930    ldr   r3, =0x3000
1931    ldr   r11, =0x20000
1932ddr_wait_engine_idle_1:
1933    subs  r11, r11, #1
1934    beq   ddr_test_fail
1935    ldr   r2, [r0]
1936    tst   r2, r3                                 @ D[12] = idle bit
1937    beq   ddr_wait_engine_idle_1
1938
1939    ldr   r0, =0x1e6e0070                        @ read fail bit status
1940    ldr   r3, =0x2000
1941    ldr   r2, [r0]
1942    tst   r2, r3                                 @ D[13] = fail bit
1943    bne   ddr_test_fail
1944
1945    add   r1, r1, #1                             @ increase the test mode index
1946    cmp   r1, #0x01                              @ test 1 modes
1947    bne   ddr_test_burst_loop
1948
1949    ldr   r0, =0x1e6e0070
1950    ldr   r1, =0x00000000
1951    str   r1, [r0]
1952    b     set_scratch                            @ CBRTest() return(1)
1953
1954ddr_test_fail:
1955/* Debug - UART console message */
1956    ldr   r0, =0x1e784000
1957    mov   r1, #0x46                              @ 'F'
1958    str   r1, [r0]
1959    mov   r1, #0x61                              @ 'a'
1960    str   r1, [r0]
1961    mov   r1, #0x69                              @ 'i'
1962    str   r1, [r0]
1963    mov   r1, #0x6C                              @ 'l'
1964    str   r1, [r0]
1965    mov   r1, #0x0D                              @ '\r'
1966    str   r1, [r0]
1967    mov   r1, #0x0A                              @ '\n'
1968    str   r1, [r0]
1969    ldr   r0, =0x1e784014
1970wait_print_0:
1971    ldr   r1, [r0]
1972    tst   r1, #0x40
1973    beq   wait_print_0
1974/* Debug - UART console message */
1975    b     reset_mmc
1976
1977set_scratch:
1978    /*Set Scratch register Bit 6 after ddr initial finished */
1979    ldr   r0, =0x1e6e2040
1980    ldr   r1, [r0]
1981    orr   r1, r1, #0x41
1982    str   r1, [r0]
1983
1984/* Debug - UART console message */
1985    ldr   r0, =0x1e784000
1986    mov   r1, #0x44                              @ 'D'
1987    str   r1, [r0]
1988    mov   r1, #0x6F                              @ 'o'
1989    str   r1, [r0]
1990    mov   r1, #0x6E                              @ 'n'
1991    str   r1, [r0]
1992    mov   r1, #0x65                              @ 'e'
1993    str   r1, [r0]
1994    mov   r1, #0x0D                              @ '\r'
1995    str   r1, [r0]
1996    mov   r1, #0x0A                              @ '\n'
1997    str   r1, [r0]
1998/* Debug - UART console message */
1999
2000    /* Enable VGA display */
2001    ldr   r0, =0x1e6e202c
2002    ldr   r1, [r0]
2003    bic   r1, r1, #0x40
2004    str   r1, [r0]
2005
2006/* Debug - UART console message */
2007   /* Print PHY timing information */
2008    ldr   r0, =0x1e784014
2009wait_print_1:
2010    ldr   r1, [r0]
2011    tst   r1, #0x40
2012    beq   wait_print_1
2013
2014    ldr   r0, =0x1e784000
2015    mov   r1, #0x52                              @ 'R'
2016    str   r1, [r0]
2017    mov   r1, #0x65                              @ 'e'
2018    str   r1, [r0]
2019    mov   r1, #0x61                              @ 'a'
2020    str   r1, [r0]
2021    mov   r1, #0x64                              @ 'd'
2022    str   r1, [r0]
2023    mov   r1, #0x20                              @ ' '
2024    str   r1, [r0]
2025    mov   r1, #0x6D                              @ 'm'
2026    str   r1, [r0]
2027    mov   r1, #0x61                              @ 'a'
2028    str   r1, [r0]
2029    mov   r1, #0x72                              @ 'r'
2030    str   r1, [r0]
2031    mov   r1, #0x67                              @ 'g'
2032    str   r1, [r0]
2033    mov   r1, #0x69                              @ 'i'
2034    str   r1, [r0]
2035    mov   r1, #0x6E                              @ 'n'
2036    str   r1, [r0]
2037    mov   r1, #0x2D                              @ '-'
2038    str   r1, [r0]
2039    mov   r1, #0x44                              @ 'D'
2040    str   r1, [r0]
2041    mov   r1, #0x4C                              @ 'L'
2042    str   r1, [r0]
2043    mov   r1, #0x3A                              @ ':'
2044    str   r1, [r0]
2045
2046    ldr   r0, =0x1e784014
2047wait_print_2:
2048    ldr   r1, [r0]
2049    tst   r1, #0x40
2050    beq   wait_print_2
2051
2052    ldr   r7, =0x000001FE                        @ divide by 510
2053    mov   r8, #10                                @ multiply by 10
2054    mov   r9, #0                                 @ record violation
2055    ldr   r0, =0x1e6e0004
2056    ldr   r1, [r0]
2057    tst   r1, #0x10                              @ bit[4]=1 => DDR4
2058    movne r10, #0x9A                             @ DDR4 min = 0x99 (0.30)
2059    moveq r10, #0xB3                             @ DDR3 min = 0xB3 (0.35)
2060print_DQL_eye_margin:
2061    ldr   r0, =0x1e6e03d0
2062    ldr   r2, [r0]
2063    and   r2, r2, #0xFF
2064    cmp   r2, r10                                @ check violation
2065    movlt r9, #1
2066    ldr   r0, =0x1e784000
2067    mov   r1, #0x30                              @ '0'
2068    str   r1, [r0]
2069    mov   r1, #0x2E                              @ '.'
2070    str   r1, [r0]
2071    mov   r3, #0x4                               @ print 4 digits
2072print_DQL_div_loop:
2073    mul   r2, r8, r2
2074    cmp   r2, r7
2075    blt   print_DQL_div_0
2076    mov   r6, #0x0
2077print_DQL_div_digit:
2078    sub   r2, r2, r7
2079    add   r6, r6, #0x1
2080    cmp   r2, r7
2081    bge   print_DQL_div_digit
2082    b     print_DQL_div_n
2083
2084print_DQL_div_0:
2085    mov   r1, #0x30                              @ '0'
2086    str   r1, [r0]
2087    b     print_DQL_next
2088print_DQL_div_n:
2089    add   r1, r6, #0x30                          @ print n
2090    str   r1, [r0]
2091print_DQL_next:
2092    subs  r3, r3, #1
2093    beq   print_DQH_eye_margin
2094    cmp   r2, #0x0
2095    beq   print_DQH_eye_margin
2096    b     print_DQL_div_loop
2097
2098print_DQH_eye_margin:
2099    mov   r1, #0x2F                              @ '/'
2100    str   r1, [r0]
2101    mov   r1, #0x44                              @ 'D'
2102    str   r1, [r0]
2103    mov   r1, #0x48                              @ 'H'
2104    str   r1, [r0]
2105    mov   r1, #0x3A                              @ ':'
2106    str   r1, [r0]
2107
2108    ldr   r0, =0x1e784014
2109wait_print_3:
2110    ldr   r1, [r0]
2111    tst   r1, #0x40
2112    beq   wait_print_3
2113
2114    ldr   r0, =0x1e6e03d0
2115    ldr   r2, [r0]
2116    mov   r2, r2, lsr #8
2117    and   r2, r2, #0xFF
2118    cmp   r2, r10                                @ check violation
2119    movlt r9, #1
2120    ldr   r0, =0x1e784000
2121    mov   r1, #0x30                              @ '0'
2122    str   r1, [r0]
2123    mov   r1, #0x2E                              @ '.'
2124    str   r1, [r0]
2125    mov   r3, #0x4                               @ print 4 digits
2126print_DQH_div_loop:
2127    mul   r2, r8, r2
2128    cmp   r2, r7
2129    blt   print_DQH_div_0
2130    mov   r6, #0x0
2131print_DQH_div_digit:
2132    sub   r2, r2, r7
2133    add   r6, r6, #0x1
2134    cmp   r2, r7
2135    bge   print_DQH_div_digit
2136    b     print_DQH_div_n
2137
2138print_DQH_div_0:
2139    mov   r1, #0x30                              @ '0'
2140    str   r1, [r0]
2141    b     print_DQH_next
2142print_DQH_div_n:
2143    add   r1, r6, #0x30                          @ print n
2144    str   r1, [r0]
2145print_DQH_next:
2146    subs  r3, r3, #1
2147    beq   print_DQ_eye_margin_last
2148    cmp   r2, #0x0
2149    beq   print_DQ_eye_margin_last
2150    b     print_DQH_div_loop
2151
2152print_DQ_eye_margin_last:
2153    mov   r1, #0x20                              @ ' '
2154    str   r1, [r0]
2155    mov   r1, #0x43                              @ 'C'
2156    str   r1, [r0]
2157    mov   r1, #0x4B                              @ 'K'
2158    str   r1, [r0]
2159
2160    ldr   r0, =0x1e6e0004
2161    ldr   r1, [r0]
2162    tst   r1, #0x10                              @ bit[4]=1 => DDR4
2163    movne r10, #0x30                             @ DDR4 min = 0.30
2164    moveq r10, #0x35                             @ DDR4 min = 0.35
2165
2166    ldr   r0, =0x1e784014
2167wait_print_4:
2168    ldr   r1, [r0]
2169    tst   r1, #0x40
2170    beq   wait_print_4
2171
2172    ldr   r0, =0x1e784000
2173    mov   r1, #0x20                              @ ' '
2174    str   r1, [r0]
2175    mov   r1, #0x28                              @ '('
2176    str   r1, [r0]
2177    mov   r1, #0x6D                              @ 'm'
2178    str   r1, [r0]
2179    mov   r1, #0x69                              @ 'i'
2180    str   r1, [r0]
2181    mov   r1, #0x6E                              @ 'n'
2182    str   r1, [r0]
2183    mov   r1, #0x3A                              @ ':'
2184    str   r1, [r0]
2185    mov   r1, #0x30                              @ '0'
2186    str   r1, [r0]
2187    mov   r1, #0x2E                              @ '.'
2188    str   r1, [r0]
2189    mov   r1, #0x33                              @ '3'
2190    str   r1, [r0]
2191    str   r10, [r0]
2192    mov   r1, #0x29                              @ ')'
2193    str   r1, [r0]
2194
2195    cmp   r9, #0
2196    beq   print_DQ_margin_last
2197    mov   r1, #0x20                              @ ' '
2198    str   r1, [r0]
2199    ldr   r0, =0x1e784014
2200wait_print_5:
2201    ldr   r1, [r0]
2202    tst   r1, #0x40
2203    beq   wait_print_5
2204
2205    ldr   r0, =0x1e784000
2206    mov   r1, #0x57                              @ 'W'
2207    str   r1, [r0]
2208    mov   r1, #0x61                              @ 'a'
2209    str   r1, [r0]
2210    mov   r1, #0x72                              @ 'r'
2211    str   r1, [r0]
2212    mov   r1, #0x6E                              @ 'n'
2213    str   r1, [r0]
2214    mov   r1, #0x69                              @ 'i'
2215    str   r1, [r0]
2216    mov   r1, #0x6E                              @ 'n'
2217    str   r1, [r0]
2218    mov   r1, #0x67                              @ 'g'
2219    str   r1, [r0]
2220    mov   r1, #0x3A                              @ ':'
2221    str   r1, [r0]
2222    mov   r1, #0x20                              @ ' '
2223    str   r1, [r0]
2224    mov   r1, #0x4D                              @ 'M'
2225    str   r1, [r0]
2226    mov   r1, #0x61                              @ 'a'
2227    str   r1, [r0]
2228    mov   r1, #0x72                              @ 'r'
2229    str   r1, [r0]
2230    mov   r1, #0x67                              @ 'g'
2231    str   r1, [r0]
2232    mov   r1, #0x69                              @ 'i'
2233    str   r1, [r0]
2234    mov   r1, #0x6E                              @ 'n'
2235    str   r1, [r0]
2236    ldr   r0, =0x1e784014
2237wait_print_6:
2238    ldr   r1, [r0]
2239    tst   r1, #0x40
2240    beq   wait_print_6
2241    ldr   r0, =0x1e784000
2242    mov   r1, #0x20                              @ ' '
2243    str   r1, [r0]
2244    mov   r1, #0x74                              @ 't'
2245    str   r1, [r0]
2246    mov   r1, #0x6F                              @ 'o'
2247    str   r1, [r0]
2248    mov   r1, #0x6F                              @ 'o'
2249    str   r1, [r0]
2250    mov   r1, #0x20                              @ ' '
2251    str   r1, [r0]
2252    mov   r1, #0x73                              @ 's'
2253    str   r1, [r0]
2254    mov   r1, #0x6D                              @ 'm'
2255    str   r1, [r0]
2256    mov   r1, #0x61                              @ 'a'
2257    str   r1, [r0]
2258    mov   r1, #0x6C                              @ 'l'
2259    str   r1, [r0]
2260    mov   r1, #0x6C                              @ 'l'
2261    str   r1, [r0]
2262
2263print_DQ_margin_last:
2264    mov   r1, #0x0D                              @ '\r'
2265    str   r1, [r0]
2266    mov   r1, #0x0A                              @ '\n'
2267    str   r1, [r0]
2268/* Debug - UART console message */
2269
2270platform_exit:
2271#ifdef CONFIG_DRAM_ECC
2272    ldr   r0, =0x1e6e0004
2273    ldr   r2, =0x00000880                        @ add cache range control, 2016.09.02
2274    ldr   r1, [r0]
2275    orr   r1, r1, r2
2276    str   r1, [r0]
2277
2278    ldr   r0, =0x1e6e0054
2279    ldr   r1, =CONFIG_DRAM_ECC_SIZE              /* ECC protected memory size */
2280    str   r1, [r0]
2281
2282    ldr   r0, =0x1e6e007C
2283    ldr   r1, =0x00000000
2284    str   r1, [r0]
2285    ldr   r0, =0x1e6e0074
2286    str   r1, [r0]
2287
2288    ldr   r0, =0x1e6e0070
2289    ldr   r1, =0x00000221
2290    str   r1, [r0]
2291
2292    ldr   r2, =0x00001000
2293ECC_Init_Flag:
2294    ldr   r1, [r0]
2295    tst   r1, r2                                 @ D[12] = 1, Done
2296    beq   ECC_Init_Flag
2297
2298    ldr   r1, =0x00000000
2299    str   r1, [r0]
2300
2301    ldr   r0, =0x1e6e0050
2302    ldr   r1, =0x80000000
2303    str   r1, [r0]
2304
2305    ldr   r0, =0x1e6e0050
2306    ldr   r1, =0x00000000
2307    str   r1, [r0]
2308
2309    ldr   r0, =0x1e6e0070
2310    ldr   r1, =0x00000400                        @ Enable ECC auto-scrubbing
2311    str   r1, [r0]
2312#endif
2313
2314/******************************************************************************
2315 SPI Timing Calibration
2316 ******************************************************************************/
2317#ifndef CONFIG_SPL_BUILD
2318    mov   r2, #0x0
2319    mov   r6, #0x0
2320    mov   r7, #0x0
2321    init_spi_checksum
2322spi_checksum_wait_0:
2323    ldr   r1, [r0]
2324    tst   r1, r2
2325    beq   spi_checksum_wait_0
2326    ldr   r0, =0x1e620090
2327    ldr   r5, [r0]                               @ record golden checksum
2328    ldr   r0, =0x1e620080
2329    mov   r1, #0x0
2330    str   r1, [r0]
2331
2332    ldr   r0, =0x1e620010                        @ set to fast read mode
2333    ldr   r1, =0x000B0041
2334    str   r1, [r0]
2335
2336    ldr   r6, =0x00F7E6D0                        @ Init spiclk loop
2337    mov   r8, #0x0                               @ Init delay record
2338
2339spi_cbr_next_clkrate:
2340    mov   r6, r6, lsr #0x4
2341    cmp   r6, #0x0
2342    beq   spi_cbr_end
2343
2344    mov   r7, #0x0                               @ Init delay loop
2345    mov   r8, r8, lsl #4
2346
2347spi_cbr_next_delay_s:
2348    mov   r2, #0x8
2349    init_spi_checksum
2350spi_checksum_wait_1:
2351    ldr   r1, [r0]
2352    tst   r1, r2
2353    beq   spi_checksum_wait_1
2354    ldr   r0, =0x1e620090
2355    ldr   r2, [r0]                               @ read checksum
2356    ldr   r0, =0x1e620080
2357    mov   r1, #0x0
2358    str   r1, [r0]
2359    cmp   r2, r5
2360    bne   spi_cbr_next_delay_e
2361
2362    mov   r2, #0x0
2363    init_spi_checksum
2364spi_checksum_wait_2:
2365    ldr   r1, [r0]
2366    tst   r1, r2
2367    beq   spi_checksum_wait_2
2368    ldr   r0, =0x1e620090
2369    ldr   r2, [r0]                               @ read checksum
2370    ldr   r0, =0x1e620080
2371    mov   r1, #0x0
2372    str   r1, [r0]
2373    cmp   r2, r5
2374    bne   spi_cbr_next_delay_e
2375
2376    orr   r8, r8, r7                             @ record passed delay
2377    b     spi_cbr_next_clkrate
2378
2379spi_cbr_next_delay_e:
2380    add   r7, r7, #0x1
2381    cmp   r7, #0x6
2382    blt   spi_cbr_next_delay_s
2383    b     spi_cbr_next_clkrate
2384
2385spi_cbr_end:
2386    ldr   r0, =0x1e620094
2387    str   r8, [r0]
2388    ldr   r0, =0x1e620010
2389    mov   r1, #0x0
2390    str   r1, [r0]
2391#endif
2392
2393/******************************************************************************
2394 Miscellaneous Setting
2395 ******************************************************************************/
2396    /* Set UART DMA as AHB high priority master */
2397    ldr   r0, =0x1e600000
2398    ldr   r1, =0xAEED1A03
2399    str   r1, [r0]
2400
2401    ldr   r0, =0x1e600080
2402    ldr   r2, =0x100
2403    ldr   r1, [r0]
2404    orr   r1, r1, r2
2405    str   r1, [r0]
2406
2407    /* Enable UART3/4 clock and disable LHCLK */
2408    ldr   r0, =0x1e6e200c
2409    ldr   r1, [r0]
2410    ldr   r2, =0xF9FFFFFF
2411    and   r1, r1, r2
2412    ldr   r2, =0x10000000
2413    orr   r1, r1, r2
2414    str   r1, [r0]
2415
2416    ldr   r0, =0x1e6e2008                        @ Set Video ECLK phase
2417    ldr   r1, [r0]
2418    ldr   r2, =0x0ffffff3
2419    and   r1, r1, r2
2420    str   r1, [r0]
2421
2422    ldr r0, =0x1e6e2004                          @ Enable JTAG Master, solve ARM stucked by JTAG issue
2423    ldr r1, [r0]
2424    bic r1, r1, #0x00400000
2425    str r1, [r0]
2426
2427/******************************************************************************
2428 Configure MAC timing
2429 ******************************************************************************/
2430    /* Enable D2PLL and set to 250MHz */
2431    ldr   r0, =0x1e6e213c
2432    ldr   r1, =0x00000585                        @ Reset D2PLL
2433    str   r1, [r0]
2434
2435    ldr   r0, =0x1e6e202c
2436    ldr   r1, [r0]
2437    bic   r1, r1, #0x10                          @ Enable D2PLL
2438    ldr   r2, =0x00200000                        @ Set CRT = 40MHz
2439    orr   r1, r1, r2
2440    str   r1, [r0]
2441
2442    ldr   r2, =0x8E00A17C                        @ Set to 250MHz
2443
2444    ldr   r0, =0x1e6e2070                        @ Check CLKIN = 25MHz
2445    ldr   r1, [r0]
2446    mov   r1, r1, lsr #23
2447    tst   r1, #0x01
2448    beq   set_D2PLL
2449    ldr   r2, =0x8E00A177
2450
2451set_D2PLL:
2452    ldr   r0, =0x1e6e201c
2453    str   r2, [r0]
2454    ldr   r0, =0x1e6e213c                        @ Enable D2PLL
2455    ldr   r1, =0x00000580
2456    str   r1, [r0]
2457
2458    ldr   r0, =0x1e6e204c
2459    ldr   r1, [r0]
2460    bic   r1, r1, #0xFF0000
2461    ldr   r2, =0x00040000                        @ Set divider ratio
2462    orr   r1, r1, r2
2463    str   r1, [r0]
2464
2465    ldr   r0, =0x1e6e2048                        @ Set MAC interface delay timing = 1G
2466    ldr   r1, =0x80082208                        @ Select internal 125MHz
2467    str   r1, [r0]
2468    ldr   r0, =0x1e6e20b8                        @ Set MAC interface delay timing = 100M
2469    str   r1, [r0]
2470    ldr   r0, =0x1e6e20bc                        @ Set MAC interface delay timing = 10M
2471    str   r1, [r0]
2472
2473    ldr   r0, =0x1e6e2070                        @ Set MAC AHB bus clock
2474    ldr   r1, [r0]
2475    mov   r2, #0x04                              @ Default RMII, set MHCLK = HPLL/10
2476    tst   r1, #0xC0
2477    movne r2, #0x02                              @ if RGMII,     set MHCLK = HPLL/6
2478    ldr   r0, =0x1e6e2008
2479    ldr   r1, [r0]
2480    bic   r1, r1, #0x00070000
2481    orr   r1, r1, r2, lsl #16
2482    str   r1, [r0]
2483
2484    ldr   r0, =0x1e6e21dc                        @ Set MAC duty
2485    ldr   r1, =0x00666400
2486    str   r1, [r0]
2487
2488    ldr   r0, =0x1e6e2090                        @ Enable MAC interface pull low
2489    ldr   r1, [r0]
2490    bic   r1, r1, #0x0000F000
2491    bic   r1, r1, #0x20000000                    @ Set USB portA as Device mode
2492    str   r1, [r0]
2493
2494/* Test - DRAM initial time */
2495    ldr   r0, =0x1e782040
2496    ldr   r1, [r0]
2497    ldr   r0, =0xFFFFFFFF
2498    sub   r1, r0, r1
2499    ldr   r0, =0x1e6e008c
2500    str   r1, [r0]
2501    ldr   r0, =0x1e78203c
2502    ldr   r1, =0x0000F000
2503    str   r1, [r0]
2504/* Test - DRAM initial time */
2505
2506    ldr   r0, =0x1e6e0000                        @ disable MMC password
2507    mov   r1, #0x0
2508    str   r1, [r0]
2509
2510    /* Disable Timer separate mode */
2511    ldr   r0, =0x1e782038
2512    ldr   r1, =0xEA
2513    str   r1, [r0]
2514
2515    /* back to arch calling code */
2516    mov   pc, lr
2517
2518