1 /* 2 * Aspeed PCIe host controller 3 * 4 * Copyright (c) 2022 Cédric Le Goater <clg@kaod.org> 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #ifndef ASPEED_PCIE_H 11 #define ASPEED_PCIE_H 12 13 #include "hw/sysbus.h" 14 #include "hw/pci/pci.h" 15 #include "hw/pci/pci_bridge.h" 16 #include "hw/pci/pcie_host.h" 17 #include "qom/object.h" 18 19 #define TYPE_ASPEED_PCIE_ROOT "aspeed-pcie-root" 20 OBJECT_DECLARE_SIMPLE_TYPE(AspeedPCIERoot, ASPEED_PCIE_ROOT); 21 22 struct AspeedPCIERoot { 23 PCIBridge parent_obj; 24 }; 25 26 #define TYPE_ASPEED_PCIE_RC "aspeed-pcie-rc" 27 OBJECT_DECLARE_SIMPLE_TYPE(AspeedPCIERc, ASPEED_PCIE_RC); 28 29 #define ASPEED_PCIE_RC_REGS (0xD0 >> 2) 30 31 struct AspeedPCIERc { 32 PCIExpressHost parent_obj; 33 34 char name[16]; 35 36 uint32_t bus_nr; 37 uint64_t mmio_base, mmio_size; 38 39 MemoryRegion mmio; 40 MemoryRegion io; 41 MemoryRegion mmio_window; 42 MemoryRegion io_window; 43 44 MemoryRegion reg_rc_mmio; 45 uint32_t regs[ASPEED_PCIE_RC_REGS]; 46 qemu_irq irq; 47 48 AspeedPCIERoot root; 49 }; 50 51 /* bridge between AHB bus and PCIe RC. */ 52 #define TYPE_ASPEED_PCIE_CFG "aspeed-pcie-cfg" 53 OBJECT_DECLARE_SIMPLE_TYPE(AspeedPCIECfg, ASPEED_PCIE_CFG); 54 55 #define ASPEED_PCIE_CFG_REGS (0xD0 >> 2) 56 57 struct AspeedPCIECfg { 58 SysBusDevice parent_obj; 59 60 MemoryRegion reg_mmio_container; 61 MemoryRegion reg_cfg_mmio; 62 uint32_t regs[ASPEED_PCIE_CFG_REGS]; 63 64 AspeedPCIERc rcs[2]; 65 }; 66 67 68 #define TYPE_ASPEED_PCIE_PHY "aspeed-pcie-phy" 69 OBJECT_DECLARE_SIMPLE_TYPE(AspeedPCIEPhy, ASPEED_PCIE_PHY); 70 71 #define ASPEED_PCIE_PHY_REGS (0xD0 >> 2) 72 73 struct AspeedPCIEPhy { 74 SysBusDevice parent_obj; 75 76 MemoryRegion mmio; 77 uint32_t regs[ASPEED_PCIE_PHY_REGS]; 78 }; 79 80 #endif /* ASPEED_PCIE_H */ 81