1 /*
2 * ASPEED SoC family
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #ifndef ASPEED_SOC_H
13 #define ASPEED_SOC_H
14
15 #include "hw/cpu/a15mpcore.h"
16 #include "hw/arm/armv7m.h"
17 #include "hw/intc/aspeed_vic.h"
18 #include "hw/intc/aspeed_intc.h"
19 #include "hw/misc/aspeed_scu.h"
20 #include "hw/adc/aspeed_adc.h"
21 #include "hw/misc/aspeed_gfx.h"
22 #include "hw/misc/aspeed_sdmc.h"
23 #include "hw/misc/aspeed_xdma.h"
24 #include "hw/timer/aspeed_timer.h"
25 #include "hw/rtc/aspeed_rtc.h"
26 #include "hw/misc/aspeed_ibt.h"
27 #include "hw/i2c/aspeed_i2c.h"
28 #include "hw/i3c/aspeed_i3c.h"
29 #include "hw/ssi/aspeed_smc.h"
30 #include "hw/misc/aspeed_hace.h"
31 #include "hw/misc/aspeed_sbc.h"
32 #include "hw/misc/aspeed_sli.h"
33 #include "hw/misc/aspeed_pwm.h"
34 #include "hw/watchdog/wdt_aspeed.h"
35 #include "hw/net/ftgmac100.h"
36 #include "target/arm/cpu.h"
37 #include "hw/gpio/aspeed_gpio.h"
38 #include "hw/sd/aspeed_sdhci.h"
39 #include "hw/usb/hcd-ehci.h"
40 #include "hw/usb/hcd-uhci-sysbus.h"
41 #include "qom/object.h"
42 #include "hw/misc/aspeed_lpc.h"
43 #include "hw/misc/unimp.h"
44 #include "hw/pci-host/aspeed_pcie.h"
45 #include "hw/misc/aspeed_peci.h"
46 #include "hw/fsi/aspeed_apb2opb.h"
47 #include "hw/char/serial-mm.h"
48 #include "hw/intc/arm_gicv3.h"
49
50 #define ASPEED_SPIS_NUM 3
51 #define ASPEED_EHCIS_NUM 4
52 #define ASPEED_WDTS_NUM 8
53 #define ASPEED_CPUS_NUM 4
54 #define ASPEED_MACS_NUM 4
55 #define ASPEED_UARTS_NUM 13
56 #define ASPEED_JTAG_NUM 2
57
58 struct AspeedSoCState {
59 DeviceState parent;
60
61 MemoryRegion *memory;
62 MemoryRegion *dram_mr;
63 MemoryRegion dram_container;
64 MemoryRegion sram;
65 MemoryRegion spi_boot_container;
66 MemoryRegion spi_boot;
67 MemoryRegion vbootrom;
68 AddressSpace dram_as;
69 AspeedRtcState rtc;
70 AspeedTimerCtrlState timerctrl;
71 AspeedIBTState ibt;
72 AspeedI2CState i2c;
73 AspeedI3CState i3c;
74 AspeedSCUState scu;
75 AspeedSCUState scuio;
76 AspeedHACEState hace;
77 AspeedXDMAState xdma;
78 AspeedADCState adc;
79 AspeedSMCState fmc;
80 AspeedSMCState spi[ASPEED_SPIS_NUM];
81 EHCISysBusState ehci[ASPEED_EHCIS_NUM];
82 ASPEEDUHCIState uhci;
83 AspeedSBCState sbc;
84 AspeedSLIState sli;
85 AspeedSLIState sliio;
86 MemoryRegion secsram;
87 UnimplementedDeviceState sbc_unimplemented;
88 AspeedSDMCState sdmc;
89 AspeedWDTState wdt[ASPEED_WDTS_NUM];
90 FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
91 AspeedMiiState mii[ASPEED_MACS_NUM];
92 AspeedGPIOState gpio;
93 AspeedGPIOState gpio_1_8v;
94 AspeedSDHCIState sdhci;
95 AspeedSDHCIState emmc;
96 AspeedLPCState lpc;
97 AspeedPCIECfg pcie;
98 AspeedPCIEPhy pcie_phy[2];
99 AspeedPECIState peci;
100 AspeedGFXState gfx;
101 SerialMM uart[ASPEED_UARTS_NUM];
102 Clock *sysclk;
103 UnimplementedDeviceState iomem;
104 UnimplementedDeviceState iomem0;
105 UnimplementedDeviceState iomem1;
106 UnimplementedDeviceState video;
107 UnimplementedDeviceState emmc_boot_controller;
108 UnimplementedDeviceState dpmcu;
109 AspeedPWMState pwm;
110 UnimplementedDeviceState espi;
111 UnimplementedDeviceState udc;
112 UnimplementedDeviceState sgpiom;
113 UnimplementedDeviceState ltpi;
114 UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
115 AspeedAPB2OPBState fsi[2];
116 };
117
118 #define TYPE_ASPEED_SOC "aspeed-soc"
119 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
120
121 struct Aspeed2400SoCState {
122 AspeedSoCState parent;
123
124 ARMCPU cpu[ASPEED_CPUS_NUM];
125 AspeedVICState vic;
126 };
127
128 #define TYPE_ASPEED2400_SOC "aspeed2400-soc"
129 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
130
131 struct Aspeed2600SoCState {
132 AspeedSoCState parent;
133
134 A15MPPrivState a7mpcore;
135 ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */
136 };
137
138 #define TYPE_ASPEED2600_SOC "aspeed2600-soc"
139 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
140
141 struct Aspeed27x0SoCState {
142 AspeedSoCState parent;
143
144 ARMCPU cpu[ASPEED_CPUS_NUM];
145 AspeedINTCState intc[2];
146 GICv3State gic;
147 MemoryRegion dram_empty;
148 };
149
150 #define TYPE_ASPEED27X0_SOC "aspeed27x0-soc"
151 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SoCState, ASPEED27X0_SOC)
152
153 struct Aspeed10x0SoCState {
154 AspeedSoCState parent;
155
156 ARMv7MState armv7m;
157 };
158
159 struct Aspeed27x0SSPSoCState {
160 AspeedSoCState parent;
161 AspeedINTCState intc[2];
162 UnimplementedDeviceState ipc[2];
163 UnimplementedDeviceState scuio;
164
165 ARMv7MState armv7m;
166 };
167
168 #define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc"
169 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState, ASPEED27X0SSP_SOC)
170
171 struct Aspeed27x0TSPSoCState {
172 AspeedSoCState parent;
173 AspeedINTCState intc[2];
174 UnimplementedDeviceState ipc[2];
175 UnimplementedDeviceState scuio;
176
177 ARMv7MState armv7m;
178 };
179
180 #define TYPE_ASPEED27X0TSP_SOC "aspeed27x0tsp-soc"
181 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0TSPSoCState, ASPEED27X0TSP_SOC)
182
183 #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
184 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC)
185
186 struct AspeedSoCClass {
187 DeviceClass parent_class;
188
189 /** valid_cpu_types: NULL terminated array of a single CPU type. */
190 const char * const *valid_cpu_types;
191 uint32_t silicon_rev;
192 uint64_t sram_size;
193 uint64_t vbootrom_size;
194 uint64_t secsram_size;
195 int spis_num;
196 int ehcis_num;
197 int wdts_num;
198 int macs_num;
199 int uarts_num;
200 int uarts_base;
201 const int *irqmap;
202 const hwaddr *memmap;
203 uint32_t num_cpus;
204 qemu_irq (*get_irq)(AspeedSoCState *s, int dev);
205 bool (*boot_from_emmc)(AspeedSoCState *s);
206 };
207
208 const char *aspeed_soc_cpu_type(AspeedSoCClass *sc);
209
210 enum {
211 ASPEED_DEV_VBOOTROM,
212 ASPEED_DEV_SPI_BOOT,
213 ASPEED_DEV_IOMEM,
214 ASPEED_DEV_IOMEM0,
215 ASPEED_DEV_IOMEM1,
216 ASPEED_DEV_LTPI,
217 ASPEED_DEV_UART0,
218 ASPEED_DEV_UART1,
219 ASPEED_DEV_UART2,
220 ASPEED_DEV_UART3,
221 ASPEED_DEV_UART4,
222 ASPEED_DEV_UART5,
223 ASPEED_DEV_UART6,
224 ASPEED_DEV_UART7,
225 ASPEED_DEV_UART8,
226 ASPEED_DEV_UART9,
227 ASPEED_DEV_UART10,
228 ASPEED_DEV_UART11,
229 ASPEED_DEV_UART12,
230 ASPEED_DEV_UART13,
231 ASPEED_DEV_VUART,
232 ASPEED_DEV_FMC,
233 ASPEED_DEV_SPI0,
234 ASPEED_DEV_SPI1,
235 ASPEED_DEV_SPI2,
236 ASPEED_DEV_EHCI1,
237 ASPEED_DEV_EHCI2,
238 ASPEED_DEV_EHCI3,
239 ASPEED_DEV_EHCI4,
240 ASPEED_DEV_UHCI,
241 ASPEED_DEV_VIC,
242 ASPEED_DEV_INTC,
243 ASPEED_DEV_INTCIO,
244 ASPEED_DEV_SDMC,
245 ASPEED_DEV_SCU,
246 ASPEED_DEV_ADC,
247 ASPEED_DEV_SBC,
248 ASPEED_DEV_SECSRAM,
249 ASPEED_DEV_EMMC_BC,
250 ASPEED_DEV_VIDEO,
251 ASPEED_DEV_SRAM,
252 ASPEED_DEV_SDHCI,
253 ASPEED_DEV_GPIO,
254 ASPEED_DEV_GPIO_1_8V,
255 ASPEED_DEV_RTC,
256 ASPEED_DEV_TIMER1,
257 ASPEED_DEV_TIMER2,
258 ASPEED_DEV_TIMER3,
259 ASPEED_DEV_TIMER4,
260 ASPEED_DEV_TIMER5,
261 ASPEED_DEV_TIMER6,
262 ASPEED_DEV_TIMER7,
263 ASPEED_DEV_TIMER8,
264 ASPEED_DEV_WDT,
265 ASPEED_DEV_PWM,
266 ASPEED_DEV_LPC,
267 ASPEED_DEV_IBT,
268 ASPEED_DEV_I2C,
269 ASPEED_DEV_PCIE_PHY1,
270 ASPEED_DEV_PCIE_PHY2,
271 ASPEED_DEV_PCIE,
272 ASPEED_DEV_PCIE_MMIO1,
273 ASPEED_DEV_PCIE_MMIO2,
274 ASPEED_DEV_PECI,
275 ASPEED_DEV_ETH1,
276 ASPEED_DEV_ETH2,
277 ASPEED_DEV_ETH3,
278 ASPEED_DEV_ETH4,
279 ASPEED_DEV_MII1,
280 ASPEED_DEV_MII2,
281 ASPEED_DEV_MII3,
282 ASPEED_DEV_MII4,
283 ASPEED_DEV_SDRAM,
284 ASPEED_DEV_XDMA,
285 ASPEED_DEV_EMMC,
286 ASPEED_DEV_KCS,
287 ASPEED_DEV_HACE,
288 ASPEED_DEV_GFX,
289 ASPEED_DEV_DPMCU,
290 ASPEED_DEV_DP,
291 ASPEED_DEV_I3C,
292 ASPEED_DEV_ESPI,
293 ASPEED_DEV_UDC,
294 ASPEED_DEV_SGPIOM,
295 ASPEED_DEV_JTAG0,
296 ASPEED_DEV_JTAG1,
297 ASPEED_DEV_FSI1,
298 ASPEED_DEV_FSI2,
299 ASPEED_DEV_SCUIO,
300 ASPEED_DEV_SLI,
301 ASPEED_DEV_SLIIO,
302 ASPEED_GIC_DIST,
303 ASPEED_GIC_REDIST,
304 ASPEED_DEV_IPC0,
305 ASPEED_DEV_IPC1,
306 };
307
308 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
309 bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp);
310 void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr);
311 bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp);
312 void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr);
313 void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
314 const char *name, hwaddr addr,
315 uint64_t size);
316 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
317 unsigned int count, int unit0);
318
aspeed_uart_index(int uart_dev)319 static inline int aspeed_uart_index(int uart_dev)
320 {
321 return uart_dev - ASPEED_DEV_UART0;
322 }
323
aspeed_uart_first(AspeedSoCClass * sc)324 static inline int aspeed_uart_first(AspeedSoCClass *sc)
325 {
326 return aspeed_uart_index(sc->uarts_base);
327 }
328
aspeed_uart_last(AspeedSoCClass * sc)329 static inline int aspeed_uart_last(AspeedSoCClass *sc)
330 {
331 return aspeed_uart_first(sc) + sc->uarts_num - 1;
332 }
333
334 #endif /* ASPEED_SOC_H */
335