1 #ifndef CPER_SECTION_ARM_H 2 #define CPER_SECTION_ARM_H 3 4 #ifdef __cplusplus 5 extern "C" { 6 #endif 7 8 #include <json.h> 9 #include <libcper/Cper.h> 10 11 #define ARM_ERROR_VALID_BITFIELD_NAMES \ 12 (const char *[]) \ 13 { \ 14 "mpidrValid", "errorAffinityLevelValid", "runningStateValid", \ 15 "vendorSpecificInfoValid" \ 16 } 17 #define ARM_ERROR_INFO_ENTRY_VALID_BITFIELD_NAMES \ 18 (const char *[]) \ 19 { \ 20 "multipleErrorValid", "flagsValid", "errorInformationValid", \ 21 "virtualFaultAddressValid", \ 22 "physicalFaultAddressValid" \ 23 } 24 #define ARM_ERROR_INFO_ENTRY_FLAGS_NAMES \ 25 (const char *[]) \ 26 { \ 27 "firstErrorCaptured", "lastErrorCaptured", "propagated", \ 28 "overflow" \ 29 } 30 #define ARM_CACHE_TLB_ERROR_VALID_BITFIELD_NAMES \ 31 (const char *[]) \ 32 { \ 33 "transactionTypeValid", "operationValid", "levelValid", \ 34 "processorContextCorruptValid", "correctedValid", \ 35 "precisePCValid", "restartablePCValid" \ 36 } 37 #define ARM_BUS_ERROR_VALID_BITFIELD_NAMES \ 38 (const char *[]) \ 39 { \ 40 "transactionTypeValid", "operationValid", "levelValid", \ 41 "processorContextCorruptValid", "correctedValid", \ 42 "precisePCValid", "restartablePCValid", \ 43 "participationTypeValid", "timedOutValid", \ 44 "addressSpaceValid", "memoryAttributesValid", \ 45 "accessModeValid" \ 46 } 47 #define ARM_ERROR_TRANSACTION_TYPES_KEYS \ 48 (int[]) \ 49 { \ 50 0, 1, 2 \ 51 } 52 #define ARM_ERROR_TRANSACTION_TYPES_VALUES \ 53 (const char *[]) \ 54 { \ 55 "Instruction", "Data Access", "Generic" \ 56 } 57 #define ARM_ERROR_INFO_ENTRY_INFO_TYPES_KEYS \ 58 (int[]) \ 59 { \ 60 0, 1, 2, 3 \ 61 } 62 #define ARM_ERROR_INFO_ENTRY_INFO_TYPES_VALUES \ 63 (const char *[]) \ 64 { \ 65 "Cache Error", "TLB Error", "Bus Error", \ 66 "Micro-Architectural Error" \ 67 } 68 #define ARM_CACHE_BUS_OPERATION_TYPES_KEYS \ 69 (int[]) \ 70 { \ 71 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 \ 72 } 73 #define ARM_CACHE_BUS_OPERATION_TYPES_VALUES \ 74 (const char *[]) \ 75 { \ 76 "Generic Error", "Generic Read", "Generic Write", "Data Read", \ 77 "Data Write", "Instruction Fetch", "Prefetch", \ 78 "Eviction", "Snooping", "Snooped", "Management" \ 79 } 80 #define ARM_TLB_OPERATION_TYPES_KEYS \ 81 (int[]) \ 82 { \ 83 0, 1, 2, 3, 4, 5, 6, 7, 8 \ 84 } 85 #define ARM_TLB_OPERATION_TYPES_VALUES \ 86 (const char *[]) \ 87 { \ 88 "Generic Error", "Generic Read", "Generic Write", "Data Read", \ 89 "Data Write", "Instruction Fetch", "Prefetch", \ 90 "Local Management Operation", \ 91 "External Management Operation" \ 92 } 93 #define ARM_BUS_PARTICIPATION_TYPES_KEYS \ 94 (int[]) \ 95 { \ 96 0, 1, 2, 3 \ 97 } 98 #define ARM_BUS_PARTICIPATION_TYPES_VALUES \ 99 (const char *[]) \ 100 { \ 101 "Local Processor Originated Request", \ 102 "Local Processor Responded to Request", \ 103 "Local Processor Observed", "Generic" \ 104 } 105 #define ARM_BUS_ADDRESS_SPACE_TYPES_KEYS \ 106 (int[]) \ 107 { \ 108 0, 1, 3 \ 109 } 110 #define ARM_BUS_ADDRESS_SPACE_TYPES_VALUES \ 111 (const char *[]) \ 112 { \ 113 "External Memory Access", "Internal Memory Access", \ 114 "Device Memory Access" \ 115 } 116 #define ARM_PROCESSOR_INFO_REGISTER_CONTEXT_TYPES_KEYS \ 117 (int[]) \ 118 { \ 119 0, 1, 2, 3, 4, 5, 6, 7, 8 \ 120 } 121 #define ARM_PROCESSOR_INFO_REGISTER_CONTEXT_TYPES_VALUES \ 122 (const char *[]) \ 123 { \ 124 "AArch32 General Purpose Registers", \ 125 "AArch32 EL1 Context Registers", \ 126 "AArch32 EL2 Context Registers", \ 127 "AArch32 Secure Context Registers", \ 128 "AArch64 General Purpose Registers", \ 129 "AArch64 EL1 Context Registers", \ 130 "AArch64 EL2 Context Registers", \ 131 "AArch64 EL3 Context Registers", \ 132 "Miscellaneous System Register Structure" \ 133 } 134 #define ARM_AARCH32_GPR_NAMES \ 135 (const char *[]) \ 136 { \ 137 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \ 138 "r10", "r11", "r12", "r13_sp", "r14_lr", "r15_pc" \ 139 } 140 #define ARM_AARCH32_EL1_REGISTER_NAMES \ 141 (const char *[]) \ 142 { \ 143 "dfar", "dfsr", "ifar", "isr", "mair0", "mair1", "midr", \ 144 "mpidr", "nmrr", "prrr", "sctlr_ns", "spsr", \ 145 "spsr_abt", "spsr_fiq", "spsr_irq", "spsr_svc", \ 146 "spsr_und", "tpidrprw", "tpidruro", "tpidrurw", \ 147 "ttbcr", "ttbr0", "ttbr1", "dacr" \ 148 } 149 #define ARM_AARCH32_EL2_REGISTER_NAMES \ 150 (const char *[]) \ 151 { \ 152 "elr_hyp", "hamair0", "hamair1", "hcr", "hcr2", "hdfar", \ 153 "hifar", "hpfar", "hsr", "htcr", "htpidr", "httbr", \ 154 "spsr_hyp", "vtcr", "vttbr", "dacr32_el2" \ 155 } 156 #define ARM_AARCH32_SECURE_REGISTER_NAMES \ 157 (const char *[]) \ 158 { \ 159 "sctlr_s", "spsr_mon" \ 160 } 161 #define ARM_AARCH64_GPR_NAMES \ 162 (const char *[]) \ 163 { \ 164 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", \ 165 "x10", "x11", "x12", "x13", "x14", "x15", "x16", \ 166 "x17", "x18", "x19", "x20", "x21", "x22", "x23", \ 167 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp" \ 168 } 169 #define ARM_AARCH64_EL1_REGISTER_NAMES \ 170 (const char *[]) \ 171 { \ 172 "elr_el1", "esr_el1", "far_el1", "isr_el1", "mair_el1", \ 173 "midr_el1", "mpidr_el1", "sctlr_el1", "sp_el0", \ 174 "sp_el1", "spsr_el1", "tcr_el1", "tpidr_el0", \ 175 "tpidr_el1", "tpidrro_el0", "ttbr0_el1", "ttbr1_el1" \ 176 } 177 #define ARM_AARCH64_EL2_REGISTER_NAMES \ 178 (const char *[]) \ 179 { \ 180 "elr_el2", "esr_el2", "far_el2", "hacr_el2", "hcr_el2", \ 181 "hpfar_el2", "mair_el2", "sctlr_el2", "sp_el2", \ 182 "spsr_el2", "tcr_el2", "tpidr_el2", "ttbr0_el2", \ 183 "vtcr_el2", "vttbr_el2" \ 184 } 185 #define ARM_AARCH64_EL3_REGISTER_NAMES \ 186 (const char *[]) \ 187 { \ 188 "elr_el3", "esr_el3", "far_el3", "mair_el3", "sctlr_el3", \ 189 "sp_el3", "spsr_el3", "tcr_el3", "tpidr_el3", \ 190 "ttbr0_el3" \ 191 } 192 193 json_object *cper_section_arm_to_ir(void *section); 194 void ir_section_arm_to_cper(json_object *section, FILE *out); 195 196 #ifdef __cplusplus 197 } 198 #endif 199 200 #endif 201