1 /* 2 * QEMU Arm CPU -- feature test functions 3 * 4 * Copyright (c) 2023 Linaro Ltd 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef TARGET_ARM_FEATURES_H 21 #define TARGET_ARM_FEATURES_H 22 23 #include "hw/registerfields.h" 24 #include "qemu/host-utils.h" 25 #include "cpu.h" 26 #include "cpu-sysregs.h" 27 28 /* 29 * System register ID fields. 30 */ 31 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 32 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 33 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 34 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 35 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 36 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 37 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 38 FIELD(CLIDR_EL1, LOUIS, 21, 3) 39 FIELD(CLIDR_EL1, LOC, 24, 3) 40 FIELD(CLIDR_EL1, LOUU, 27, 3) 41 FIELD(CLIDR_EL1, ICB, 30, 3) 42 43 /* When FEAT_CCIDX is implemented */ 44 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 45 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 46 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 47 48 /* When FEAT_CCIDX is not implemented */ 49 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 50 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 51 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 52 53 FIELD(CTR_EL0, IMINLINE, 0, 4) 54 FIELD(CTR_EL0, L1IP, 14, 2) 55 FIELD(CTR_EL0, DMINLINE, 16, 4) 56 FIELD(CTR_EL0, ERG, 20, 4) 57 FIELD(CTR_EL0, CWG, 24, 4) 58 FIELD(CTR_EL0, IDC, 28, 1) 59 FIELD(CTR_EL0, DIC, 29, 1) 60 FIELD(CTR_EL0, TMINLINE, 32, 6) 61 62 FIELD(MIDR_EL1, REVISION, 0, 4) 63 FIELD(MIDR_EL1, PARTNUM, 4, 12) 64 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 65 FIELD(MIDR_EL1, VARIANT, 20, 4) 66 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 67 68 FIELD(ID_ISAR0, SWAP, 0, 4) 69 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 70 FIELD(ID_ISAR0, BITFIELD, 8, 4) 71 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 72 FIELD(ID_ISAR0, COPROC, 16, 4) 73 FIELD(ID_ISAR0, DEBUG, 20, 4) 74 FIELD(ID_ISAR0, DIVIDE, 24, 4) 75 76 FIELD(ID_ISAR1, ENDIAN, 0, 4) 77 FIELD(ID_ISAR1, EXCEPT, 4, 4) 78 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 79 FIELD(ID_ISAR1, EXTEND, 12, 4) 80 FIELD(ID_ISAR1, IFTHEN, 16, 4) 81 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 82 FIELD(ID_ISAR1, INTERWORK, 24, 4) 83 FIELD(ID_ISAR1, JAZELLE, 28, 4) 84 85 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 86 FIELD(ID_ISAR2, MEMHINT, 4, 4) 87 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 88 FIELD(ID_ISAR2, MULT, 12, 4) 89 FIELD(ID_ISAR2, MULTS, 16, 4) 90 FIELD(ID_ISAR2, MULTU, 20, 4) 91 FIELD(ID_ISAR2, PSR_AR, 24, 4) 92 FIELD(ID_ISAR2, REVERSAL, 28, 4) 93 94 FIELD(ID_ISAR3, SATURATE, 0, 4) 95 FIELD(ID_ISAR3, SIMD, 4, 4) 96 FIELD(ID_ISAR3, SVC, 8, 4) 97 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 98 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 99 FIELD(ID_ISAR3, T32COPY, 20, 4) 100 FIELD(ID_ISAR3, TRUENOP, 24, 4) 101 FIELD(ID_ISAR3, T32EE, 28, 4) 102 103 FIELD(ID_ISAR4, UNPRIV, 0, 4) 104 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 105 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 106 FIELD(ID_ISAR4, SMC, 12, 4) 107 FIELD(ID_ISAR4, BARRIER, 16, 4) 108 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 109 FIELD(ID_ISAR4, PSR_M, 24, 4) 110 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 111 112 FIELD(ID_ISAR5, SEVL, 0, 4) 113 FIELD(ID_ISAR5, AES, 4, 4) 114 FIELD(ID_ISAR5, SHA1, 8, 4) 115 FIELD(ID_ISAR5, SHA2, 12, 4) 116 FIELD(ID_ISAR5, CRC32, 16, 4) 117 FIELD(ID_ISAR5, RDM, 24, 4) 118 FIELD(ID_ISAR5, VCMA, 28, 4) 119 120 FIELD(ID_ISAR6, JSCVT, 0, 4) 121 FIELD(ID_ISAR6, DP, 4, 4) 122 FIELD(ID_ISAR6, FHM, 8, 4) 123 FIELD(ID_ISAR6, SB, 12, 4) 124 FIELD(ID_ISAR6, SPECRES, 16, 4) 125 FIELD(ID_ISAR6, BF16, 20, 4) 126 FIELD(ID_ISAR6, I8MM, 24, 4) 127 128 FIELD(ID_MMFR0, VMSA, 0, 4) 129 FIELD(ID_MMFR0, PMSA, 4, 4) 130 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 131 FIELD(ID_MMFR0, SHARELVL, 12, 4) 132 FIELD(ID_MMFR0, TCM, 16, 4) 133 FIELD(ID_MMFR0, AUXREG, 20, 4) 134 FIELD(ID_MMFR0, FCSE, 24, 4) 135 FIELD(ID_MMFR0, INNERSHR, 28, 4) 136 137 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 138 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 139 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 140 FIELD(ID_MMFR1, L1UNISW, 12, 4) 141 FIELD(ID_MMFR1, L1HVD, 16, 4) 142 FIELD(ID_MMFR1, L1UNI, 20, 4) 143 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 144 FIELD(ID_MMFR1, BPRED, 28, 4) 145 146 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 147 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 148 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 149 FIELD(ID_MMFR2, HVDTLB, 12, 4) 150 FIELD(ID_MMFR2, UNITLB, 16, 4) 151 FIELD(ID_MMFR2, MEMBARR, 20, 4) 152 FIELD(ID_MMFR2, WFISTALL, 24, 4) 153 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 154 155 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 156 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 157 FIELD(ID_MMFR3, BPMAINT, 8, 4) 158 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 159 FIELD(ID_MMFR3, PAN, 16, 4) 160 FIELD(ID_MMFR3, COHWALK, 20, 4) 161 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 162 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 163 164 FIELD(ID_MMFR4, SPECSEI, 0, 4) 165 FIELD(ID_MMFR4, AC2, 4, 4) 166 FIELD(ID_MMFR4, XNX, 8, 4) 167 FIELD(ID_MMFR4, CNP, 12, 4) 168 FIELD(ID_MMFR4, HPDS, 16, 4) 169 FIELD(ID_MMFR4, LSM, 20, 4) 170 FIELD(ID_MMFR4, CCIDX, 24, 4) 171 FIELD(ID_MMFR4, EVT, 28, 4) 172 173 FIELD(ID_MMFR5, ETS, 0, 4) 174 FIELD(ID_MMFR5, NTLBPA, 4, 4) 175 176 FIELD(ID_PFR0, STATE0, 0, 4) 177 FIELD(ID_PFR0, STATE1, 4, 4) 178 FIELD(ID_PFR0, STATE2, 8, 4) 179 FIELD(ID_PFR0, STATE3, 12, 4) 180 FIELD(ID_PFR0, CSV2, 16, 4) 181 FIELD(ID_PFR0, AMU, 20, 4) 182 FIELD(ID_PFR0, DIT, 24, 4) 183 FIELD(ID_PFR0, RAS, 28, 4) 184 185 FIELD(ID_PFR1, PROGMOD, 0, 4) 186 FIELD(ID_PFR1, SECURITY, 4, 4) 187 FIELD(ID_PFR1, MPROGMOD, 8, 4) 188 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 189 FIELD(ID_PFR1, GENTIMER, 16, 4) 190 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 191 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 192 FIELD(ID_PFR1, GIC, 28, 4) 193 194 FIELD(ID_PFR2, CSV3, 0, 4) 195 FIELD(ID_PFR2, SSBS, 4, 4) 196 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 197 198 FIELD(ID_AA64ISAR0, AES, 4, 4) 199 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 200 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 201 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 202 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 203 FIELD(ID_AA64ISAR0, TME, 24, 4) 204 FIELD(ID_AA64ISAR0, RDM, 28, 4) 205 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 206 FIELD(ID_AA64ISAR0, SM3, 36, 4) 207 FIELD(ID_AA64ISAR0, SM4, 40, 4) 208 FIELD(ID_AA64ISAR0, DP, 44, 4) 209 FIELD(ID_AA64ISAR0, FHM, 48, 4) 210 FIELD(ID_AA64ISAR0, TS, 52, 4) 211 FIELD(ID_AA64ISAR0, TLB, 56, 4) 212 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 213 214 FIELD(ID_AA64ISAR1, DPB, 0, 4) 215 FIELD(ID_AA64ISAR1, APA, 4, 4) 216 FIELD(ID_AA64ISAR1, API, 8, 4) 217 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 218 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 219 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 220 FIELD(ID_AA64ISAR1, GPA, 24, 4) 221 FIELD(ID_AA64ISAR1, GPI, 28, 4) 222 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 223 FIELD(ID_AA64ISAR1, SB, 36, 4) 224 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 225 FIELD(ID_AA64ISAR1, BF16, 44, 4) 226 FIELD(ID_AA64ISAR1, DGH, 48, 4) 227 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 228 FIELD(ID_AA64ISAR1, XS, 56, 4) 229 FIELD(ID_AA64ISAR1, LS64, 60, 4) 230 231 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 232 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 233 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 234 FIELD(ID_AA64ISAR2, APA3, 12, 4) 235 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 236 FIELD(ID_AA64ISAR2, BC, 20, 4) 237 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 238 FIELD(ID_AA64ISAR2, CLRBHB, 28, 4) 239 FIELD(ID_AA64ISAR2, SYSREG_128, 32, 4) 240 FIELD(ID_AA64ISAR2, SYSINSTR_128, 36, 4) 241 FIELD(ID_AA64ISAR2, PRFMSLC, 40, 4) 242 FIELD(ID_AA64ISAR2, RPRFM, 48, 4) 243 FIELD(ID_AA64ISAR2, CSSC, 52, 4) 244 FIELD(ID_AA64ISAR2, LUT, 56, 4) 245 FIELD(ID_AA64ISAR2, ATS1A, 60, 4) 246 247 FIELD(ID_AA64PFR0, EL0, 0, 4) 248 FIELD(ID_AA64PFR0, EL1, 4, 4) 249 FIELD(ID_AA64PFR0, EL2, 8, 4) 250 FIELD(ID_AA64PFR0, EL3, 12, 4) 251 FIELD(ID_AA64PFR0, FP, 16, 4) 252 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 253 FIELD(ID_AA64PFR0, GIC, 24, 4) 254 FIELD(ID_AA64PFR0, RAS, 28, 4) 255 FIELD(ID_AA64PFR0, SVE, 32, 4) 256 FIELD(ID_AA64PFR0, SEL2, 36, 4) 257 FIELD(ID_AA64PFR0, MPAM, 40, 4) 258 FIELD(ID_AA64PFR0, AMU, 44, 4) 259 FIELD(ID_AA64PFR0, DIT, 48, 4) 260 FIELD(ID_AA64PFR0, RME, 52, 4) 261 FIELD(ID_AA64PFR0, CSV2, 56, 4) 262 FIELD(ID_AA64PFR0, CSV3, 60, 4) 263 264 FIELD(ID_AA64PFR1, BT, 0, 4) 265 FIELD(ID_AA64PFR1, SSBS, 4, 4) 266 FIELD(ID_AA64PFR1, MTE, 8, 4) 267 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 268 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 269 FIELD(ID_AA64PFR1, SME, 24, 4) 270 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 271 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 272 FIELD(ID_AA64PFR1, NMI, 36, 4) 273 FIELD(ID_AA64PFR1, MTE_FRAC, 40, 4) 274 FIELD(ID_AA64PFR1, GCS, 44, 4) 275 FIELD(ID_AA64PFR1, THE, 48, 4) 276 FIELD(ID_AA64PFR1, MTEX, 52, 4) 277 FIELD(ID_AA64PFR1, DF2, 56, 4) 278 FIELD(ID_AA64PFR1, PFAR, 60, 4) 279 280 FIELD(ID_AA64PFR2, MTEPERM, 0, 4) 281 FIELD(ID_AA64PFR2, MTESTOREONLY, 4, 4) 282 FIELD(ID_AA64PFR2, MTEFAR, 8, 4) 283 FIELD(ID_AA64PFR2, FPMR, 32, 4) 284 285 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 286 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 287 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 288 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 289 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 290 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 291 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 292 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 293 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 294 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 295 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 296 FIELD(ID_AA64MMFR0, EXS, 44, 4) 297 FIELD(ID_AA64MMFR0, FGT, 56, 4) 298 FIELD(ID_AA64MMFR0, ECV, 60, 4) 299 300 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 301 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 302 FIELD(ID_AA64MMFR1, VH, 8, 4) 303 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 304 FIELD(ID_AA64MMFR1, LO, 16, 4) 305 FIELD(ID_AA64MMFR1, PAN, 20, 4) 306 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 307 FIELD(ID_AA64MMFR1, XNX, 28, 4) 308 FIELD(ID_AA64MMFR1, TWED, 32, 4) 309 FIELD(ID_AA64MMFR1, ETS, 36, 4) 310 FIELD(ID_AA64MMFR1, HCX, 40, 4) 311 FIELD(ID_AA64MMFR1, AFP, 44, 4) 312 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 313 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 314 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 315 FIELD(ID_AA64MMFR1, ECBHB, 60, 4) 316 317 FIELD(ID_AA64MMFR2, CNP, 0, 4) 318 FIELD(ID_AA64MMFR2, UAO, 4, 4) 319 FIELD(ID_AA64MMFR2, LSM, 8, 4) 320 FIELD(ID_AA64MMFR2, IESB, 12, 4) 321 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 322 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 323 FIELD(ID_AA64MMFR2, NV, 24, 4) 324 FIELD(ID_AA64MMFR2, ST, 28, 4) 325 FIELD(ID_AA64MMFR2, AT, 32, 4) 326 FIELD(ID_AA64MMFR2, IDS, 36, 4) 327 FIELD(ID_AA64MMFR2, FWB, 40, 4) 328 FIELD(ID_AA64MMFR2, TTL, 48, 4) 329 FIELD(ID_AA64MMFR2, BBM, 52, 4) 330 FIELD(ID_AA64MMFR2, EVT, 56, 4) 331 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 332 333 FIELD(ID_AA64MMFR3, TCRX, 0, 4) 334 FIELD(ID_AA64MMFR3, SCTLRX, 4, 4) 335 FIELD(ID_AA64MMFR3, S1PIE, 8, 4) 336 FIELD(ID_AA64MMFR3, S2PIE, 12, 4) 337 FIELD(ID_AA64MMFR3, S1POE, 16, 4) 338 FIELD(ID_AA64MMFR3, S2POE, 20, 4) 339 FIELD(ID_AA64MMFR3, AIE, 24, 4) 340 FIELD(ID_AA64MMFR3, MEC, 28, 4) 341 FIELD(ID_AA64MMFR3, D128, 32, 4) 342 FIELD(ID_AA64MMFR3, D128_2, 36, 4) 343 FIELD(ID_AA64MMFR3, SNERR, 40, 4) 344 FIELD(ID_AA64MMFR3, ANERR, 44, 4) 345 FIELD(ID_AA64MMFR3, SDERR, 52, 4) 346 FIELD(ID_AA64MMFR3, ADERR, 56, 4) 347 FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4) 348 349 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 350 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 351 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 352 FIELD(ID_AA64DFR0, BRPS, 12, 4) 353 FIELD(ID_AA64DFR0, PMSS, 16, 4) 354 FIELD(ID_AA64DFR0, WRPS, 20, 4) 355 FIELD(ID_AA64DFR0, SEBEP, 24, 4) 356 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 357 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 358 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 359 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 360 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 361 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 362 FIELD(ID_AA64DFR0, BRBE, 52, 4) 363 FIELD(ID_AA64DFR0, EXTTRCBUFF, 56, 4) 364 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 365 366 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 367 FIELD(ID_AA64ZFR0, AES, 4, 4) 368 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 369 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 370 FIELD(ID_AA64ZFR0, B16B16, 24, 4) 371 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 372 FIELD(ID_AA64ZFR0, SM4, 40, 4) 373 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 374 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 375 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 376 377 FIELD(ID_AA64SMFR0, F32F32, 32, 1) 378 FIELD(ID_AA64SMFR0, BI32I32, 33, 1) 379 FIELD(ID_AA64SMFR0, B16F32, 34, 1) 380 FIELD(ID_AA64SMFR0, F16F32, 35, 1) 381 FIELD(ID_AA64SMFR0, I8I32, 36, 4) 382 FIELD(ID_AA64SMFR0, F16F16, 42, 1) 383 FIELD(ID_AA64SMFR0, B16B16, 43, 1) 384 FIELD(ID_AA64SMFR0, I16I32, 44, 4) 385 FIELD(ID_AA64SMFR0, F64F64, 48, 1) 386 FIELD(ID_AA64SMFR0, I16I64, 52, 4) 387 FIELD(ID_AA64SMFR0, SMEVER, 56, 4) 388 FIELD(ID_AA64SMFR0, FA64, 63, 1) 389 390 FIELD(ID_DFR0, COPDBG, 0, 4) 391 FIELD(ID_DFR0, COPSDBG, 4, 4) 392 FIELD(ID_DFR0, MMAPDBG, 8, 4) 393 FIELD(ID_DFR0, COPTRC, 12, 4) 394 FIELD(ID_DFR0, MMAPTRC, 16, 4) 395 FIELD(ID_DFR0, MPROFDBG, 20, 4) 396 FIELD(ID_DFR0, PERFMON, 24, 4) 397 FIELD(ID_DFR0, TRACEFILT, 28, 4) 398 399 FIELD(ID_DFR1, MTPMU, 0, 4) 400 FIELD(ID_DFR1, HPMN0, 4, 4) 401 402 FIELD(DBGDIDR, SE_IMP, 12, 1) 403 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 404 FIELD(DBGDIDR, VERSION, 16, 4) 405 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 406 FIELD(DBGDIDR, BRPS, 24, 4) 407 FIELD(DBGDIDR, WRPS, 28, 4) 408 409 FIELD(DBGDEVID, PCSAMPLE, 0, 4) 410 FIELD(DBGDEVID, WPADDRMASK, 4, 4) 411 FIELD(DBGDEVID, BPADDRMASK, 8, 4) 412 FIELD(DBGDEVID, VECTORCATCH, 12, 4) 413 FIELD(DBGDEVID, VIRTEXTNS, 16, 4) 414 FIELD(DBGDEVID, DOUBLELOCK, 20, 4) 415 FIELD(DBGDEVID, AUXREGS, 24, 4) 416 FIELD(DBGDEVID, CIDMASK, 28, 4) 417 418 FIELD(DBGDEVID1, PCSROFFSET, 0, 4) 419 420 FIELD(MVFR0, SIMDREG, 0, 4) 421 FIELD(MVFR0, FPSP, 4, 4) 422 FIELD(MVFR0, FPDP, 8, 4) 423 FIELD(MVFR0, FPTRAP, 12, 4) 424 FIELD(MVFR0, FPDIVIDE, 16, 4) 425 FIELD(MVFR0, FPSQRT, 20, 4) 426 FIELD(MVFR0, FPSHVEC, 24, 4) 427 FIELD(MVFR0, FPROUND, 28, 4) 428 429 FIELD(MVFR1, FPFTZ, 0, 4) 430 FIELD(MVFR1, FPDNAN, 4, 4) 431 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 432 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 433 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 434 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 435 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 436 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 437 FIELD(MVFR1, FPHP, 24, 4) 438 FIELD(MVFR1, SIMDFMAC, 28, 4) 439 440 FIELD(MVFR2, SIMDMISC, 0, 4) 441 FIELD(MVFR2, FPMISC, 4, 4) 442 443 /* 444 * Naming convention for isar_feature functions: 445 * Functions which test 32-bit ID registers should have _aa32_ in 446 * their name. Functions which test 64-bit ID registers should have 447 * _aa64_ in their name. These must only be used in code where we 448 * know for certain that the CPU has AArch32 or AArch64 respectively 449 * or where the correct answer for a CPU which doesn't implement that 450 * CPU state is "false" (eg when generating A32 or A64 code, if adding 451 * system registers that are specific to that CPU state, for "should 452 * we let this system register bit be set" tests where the 32-bit 453 * flavour of the register doesn't have the bit, and so on). 454 * Functions which simply ask "does this feature exist at all" have 455 * _any_ in their name, and always return the logical OR of the _aa64_ 456 * and the _aa32_ function. 457 */ 458 459 /* 460 * 32-bit feature tests via id registers. 461 */ 462 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) 463 { 464 return FIELD_EX32_IDREG(id, ID_ISAR0, DIVIDE) != 0; 465 } 466 467 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) 468 { 469 return FIELD_EX32_IDREG(id, ID_ISAR0, DIVIDE) > 1; 470 } 471 472 static inline bool isar_feature_aa32_lob(const ARMISARegisters *id) 473 { 474 /* (M-profile) low-overhead loops and branch future */ 475 return FIELD_EX32_IDREG(id, ID_ISAR0, CMPBRANCH) >= 3; 476 } 477 478 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) 479 { 480 return FIELD_EX32_IDREG(id, ID_ISAR1, JAZELLE) != 0; 481 } 482 483 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 484 { 485 return FIELD_EX32_IDREG(id, ID_ISAR5, AES) != 0; 486 } 487 488 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 489 { 490 return FIELD_EX32_IDREG(id, ID_ISAR5, AES) > 1; 491 } 492 493 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 494 { 495 return FIELD_EX32_IDREG(id, ID_ISAR5, SHA1) != 0; 496 } 497 498 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 499 { 500 return FIELD_EX32_IDREG(id, ID_ISAR5, SHA2) != 0; 501 } 502 503 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 504 { 505 return FIELD_EX32_IDREG(id, ID_ISAR5, CRC32) != 0; 506 } 507 508 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 509 { 510 return FIELD_EX32_IDREG(id, ID_ISAR5, RDM) != 0; 511 } 512 513 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 514 { 515 return FIELD_EX32_IDREG(id, ID_ISAR5, VCMA) != 0; 516 } 517 518 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 519 { 520 return FIELD_EX32_IDREG(id, ID_ISAR6, JSCVT) != 0; 521 } 522 523 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 524 { 525 return FIELD_EX32_IDREG(id, ID_ISAR6, DP) != 0; 526 } 527 528 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 529 { 530 return FIELD_EX32_IDREG(id, ID_ISAR6, FHM) != 0; 531 } 532 533 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 534 { 535 return FIELD_EX32_IDREG(id, ID_ISAR6, SB) != 0; 536 } 537 538 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) 539 { 540 return FIELD_EX32_IDREG(id, ID_ISAR6, SPECRES) != 0; 541 } 542 543 static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id) 544 { 545 return FIELD_EX32_IDREG(id, ID_ISAR6, BF16) != 0; 546 } 547 548 static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id) 549 { 550 return FIELD_EX32_IDREG(id, ID_ISAR6, I8MM) != 0; 551 } 552 553 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) 554 { 555 return FIELD_EX32_IDREG(id, ID_PFR0, RAS) != 0; 556 } 557 558 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) 559 { 560 return FIELD_EX32_IDREG(id, ID_PFR1, MPROGMOD) != 0; 561 } 562 563 static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) 564 { 565 /* 566 * Return true if M-profile state handling insns 567 * (VSCCLRM, CLRM, FPCTX access insns) are implemented 568 */ 569 return FIELD_EX32_IDREG(id, ID_PFR1, SECURITY) >= 3; 570 } 571 572 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 573 { 574 /* Sadly this is encoded differently for A-profile and M-profile */ 575 if (isar_feature_aa32_mprofile(id)) { 576 return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0; 577 } else { 578 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3; 579 } 580 } 581 582 static inline bool isar_feature_aa32_mve(const ARMISARegisters *id) 583 { 584 /* 585 * Return true if MVE is supported (either integer or floating point). 586 * We must check for M-profile as the MVFR1 field means something 587 * else for A-profile. 588 */ 589 return isar_feature_aa32_mprofile(id) && 590 FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0; 591 } 592 593 static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id) 594 { 595 /* 596 * Return true if MVE is supported (either integer or floating point). 597 * We must check for M-profile as the MVFR1 field means something 598 * else for A-profile. 599 */ 600 return isar_feature_aa32_mprofile(id) && 601 FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2; 602 } 603 604 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) 605 { 606 /* 607 * Return true if either VFP or SIMD is implemented. 608 * In this case, a minimum of VFP w/ D0-D15. 609 */ 610 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; 611 } 612 613 static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) 614 { 615 /* Return true if D16-D31 are implemented */ 616 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2; 617 } 618 619 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) 620 { 621 return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; 622 } 623 624 static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) 625 { 626 /* Return true if CPU supports single precision floating point, VFPv2 */ 627 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; 628 } 629 630 static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) 631 { 632 /* Return true if CPU supports single precision floating point, VFPv3 */ 633 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2; 634 } 635 636 static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) 637 { 638 /* Return true if CPU supports double precision floating point, VFPv2 */ 639 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; 640 } 641 642 static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) 643 { 644 /* Return true if CPU supports double precision floating point, VFPv3 */ 645 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2; 646 } 647 648 static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id) 649 { 650 return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id); 651 } 652 653 /* 654 * We always set the FP and SIMD FP16 fields to indicate identical 655 * levels of support (assuming SIMD is implemented at all), so 656 * we only need one set of accessors. 657 */ 658 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) 659 { 660 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; 661 } 662 663 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) 664 { 665 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; 666 } 667 668 /* 669 * Note that this ID register field covers both VFP and Neon FMAC, 670 * so should usually be tested in combination with some other 671 * check that confirms the presence of whichever of VFP or Neon is 672 * relevant, to avoid accidentally enabling a Neon feature on 673 * a VFP-no-Neon core or vice-versa. 674 */ 675 static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) 676 { 677 return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0; 678 } 679 680 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) 681 { 682 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1; 683 } 684 685 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) 686 { 687 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2; 688 } 689 690 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) 691 { 692 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3; 693 } 694 695 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) 696 { 697 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4; 698 } 699 700 static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id) 701 { 702 return FIELD_EX32_IDREG(id, ID_MMFR0, VMSA) >= 4; 703 } 704 705 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) 706 { 707 return FIELD_EX32_IDREG(id, ID_MMFR3, PAN) != 0; 708 } 709 710 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) 711 { 712 return FIELD_EX32_IDREG(id, ID_MMFR3, PAN) >= 2; 713 } 714 715 static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id) 716 { 717 /* 0xf means "non-standard IMPDEF PMU" */ 718 return FIELD_EX32_IDREG(id, ID_DFR0, PERFMON) >= 4 && 719 FIELD_EX32_IDREG(id, ID_DFR0, PERFMON) != 0xf; 720 } 721 722 static inline bool isar_feature_aa32_pmuv3p4(const ARMISARegisters *id) 723 { 724 /* 0xf means "non-standard IMPDEF PMU" */ 725 return FIELD_EX32_IDREG(id, ID_DFR0, PERFMON) >= 5 && 726 FIELD_EX32_IDREG(id, ID_DFR0, PERFMON) != 0xf; 727 } 728 729 static inline bool isar_feature_aa32_pmuv3p5(const ARMISARegisters *id) 730 { 731 /* 0xf means "non-standard IMPDEF PMU" */ 732 return FIELD_EX32_IDREG(id, ID_DFR0, PERFMON) >= 6 && 733 FIELD_EX32_IDREG(id, ID_DFR0, PERFMON) != 0xf; 734 } 735 736 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) 737 { 738 return FIELD_EX32_IDREG(id, ID_MMFR4, HPDS) != 0; 739 } 740 741 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) 742 { 743 return FIELD_EX32_IDREG(id, ID_MMFR4, AC2) != 0; 744 } 745 746 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) 747 { 748 return FIELD_EX32_IDREG(id, ID_MMFR4, CCIDX) != 0; 749 } 750 751 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) 752 { 753 return FIELD_EX32_IDREG(id, ID_MMFR4, XNX) != 0; 754 } 755 756 static inline bool isar_feature_aa32_half_evt(const ARMISARegisters *id) 757 { 758 return FIELD_EX32_IDREG(id, ID_MMFR4, EVT) >= 1; 759 } 760 761 static inline bool isar_feature_aa32_evt(const ARMISARegisters *id) 762 { 763 return FIELD_EX32_IDREG(id, ID_MMFR4, EVT) >= 2; 764 } 765 766 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) 767 { 768 return FIELD_EX32_IDREG(id, ID_PFR0, DIT) != 0; 769 } 770 771 static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) 772 { 773 return FIELD_EX32_IDREG(id, ID_PFR2, SSBS) != 0; 774 } 775 776 static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id) 777 { 778 return FIELD_EX32_IDREG(id, ID_DFR0, COPDBG) >= 5; 779 } 780 781 static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) 782 { 783 return FIELD_EX32_IDREG(id, ID_DFR0, COPDBG) >= 8; 784 } 785 786 static inline bool isar_feature_aa32_doublelock(const ARMISARegisters *id) 787 { 788 return FIELD_EX32(id->dbgdevid, DBGDEVID, DOUBLELOCK) > 0; 789 } 790 791 /* 792 * 64-bit feature tests via id registers. 793 */ 794 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 795 { 796 return FIELD_EX64_IDREG(id, ID_AA64ISAR0, AES) != 0; 797 } 798 799 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 800 { 801 return FIELD_EX64_IDREG(id, ID_AA64ISAR0, AES) > 1; 802 } 803 804 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 805 { 806 return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SHA1) != 0; 807 } 808 809 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 810 { 811 return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SHA2) != 0; 812 } 813 814 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 815 { 816 return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SHA2) > 1; 817 } 818 819 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 820 { 821 return FIELD_EX64_IDREG(id, ID_AA64ISAR0, CRC32) != 0; 822 } 823 824 static inline bool isar_feature_aa64_lse(const ARMISARegisters *id) 825 { 826 return FIELD_EX64_IDREG(id, ID_AA64ISAR0, ATOMIC) >= 2; 827 } 828 829 static inline bool isar_feature_aa64_lse128(const ARMISARegisters *id) 830 { 831 return FIELD_EX64_IDREG(id, ID_AA64ISAR0, ATOMIC) >= 3; 832 } 833 834 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 835 { 836 return FIELD_EX64_IDREG(id, ID_AA64ISAR0, RDM) != 0; 837 } 838 839 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 840 { 841 return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SHA3) != 0; 842 } 843 844 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 845 { 846 return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SM3) != 0; 847 } 848 849 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 850 { 851 return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SM4) != 0; 852 } 853 854 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 855 { 856 return FIELD_EX64_IDREG(id, ID_AA64ISAR0, DP) != 0; 857 } 858 859 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 860 { 861 return FIELD_EX64_IDREG(id, ID_AA64ISAR0, FHM) != 0; 862 } 863 864 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 865 { 866 return FIELD_EX64_IDREG(id, ID_AA64ISAR0, TS) != 0; 867 } 868 869 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) 870 { 871 return FIELD_EX64_IDREG(id, ID_AA64ISAR0, TS) >= 2; 872 } 873 874 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) 875 { 876 return FIELD_EX64_IDREG(id, ID_AA64ISAR0, RNDR) != 0; 877 } 878 879 static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) 880 { 881 return FIELD_EX64_IDREG(id, ID_AA64ISAR0, TLB) == 2; 882 } 883 884 static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) 885 { 886 return FIELD_EX64_IDREG(id, ID_AA64ISAR0, TLB) != 0; 887 } 888 889 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 890 { 891 return FIELD_EX64_IDREG(id, ID_AA64ISAR1, JSCVT) != 0; 892 } 893 894 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 895 { 896 return FIELD_EX64_IDREG(id, ID_AA64ISAR1, FCMA) != 0; 897 } 898 899 static inline bool isar_feature_aa64_xs(const ARMISARegisters *id) 900 { 901 return FIELD_EX64_IDREG(id, ID_AA64ISAR1, XS) != 0; 902 } 903 904 /* 905 * These are the values from APA/API/APA3. 906 * In general these must be compared '>=', per the normal Arm ARM 907 * treatment of fields in ID registers. 908 */ 909 typedef enum { 910 PauthFeat_None = 0, 911 PauthFeat_1 = 1, 912 PauthFeat_EPAC = 2, 913 PauthFeat_2 = 3, 914 PauthFeat_FPAC = 4, 915 PauthFeat_FPACCOMBINED = 5, 916 } ARMPauthFeature; 917 918 static inline ARMPauthFeature 919 isar_feature_pauth_feature(const ARMISARegisters *id) 920 { 921 /* 922 * Architecturally, only one of {APA,API,APA3} may be active (non-zero) 923 * and the other two must be zero. Thus we may avoid conditionals. 924 */ 925 return (FIELD_EX64_IDREG(id, ID_AA64ISAR1, APA) | 926 FIELD_EX64_IDREG(id, ID_AA64ISAR1, API) | 927 FIELD_EX64_IDREG(id, ID_AA64ISAR2, APA3)); 928 } 929 930 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 931 { 932 /* 933 * Return true if any form of pauth is enabled, as this 934 * predicate controls migration of the 128-bit keys. 935 */ 936 return isar_feature_pauth_feature(id) != PauthFeat_None; 937 } 938 939 static inline bool isar_feature_aa64_pauth_qarma5(const ARMISARegisters *id) 940 { 941 /* 942 * Return true if pauth is enabled with the architected QARMA5 algorithm. 943 * QEMU will always enable or disable both APA and GPA. 944 */ 945 return FIELD_EX64_IDREG(id, ID_AA64ISAR1, APA) != 0; 946 } 947 948 static inline bool isar_feature_aa64_pauth_qarma3(const ARMISARegisters *id) 949 { 950 /* 951 * Return true if pauth is enabled with the architected QARMA3 algorithm. 952 * QEMU will always enable or disable both APA3 and GPA3. 953 */ 954 return FIELD_EX64_IDREG(id, ID_AA64ISAR2, APA3) != 0; 955 } 956 957 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 958 { 959 return FIELD_EX64_IDREG(id, ID_AA64ISAR1, SB) != 0; 960 } 961 962 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) 963 { 964 return FIELD_EX64_IDREG(id, ID_AA64ISAR1, SPECRES) != 0; 965 } 966 967 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) 968 { 969 return FIELD_EX64_IDREG(id, ID_AA64ISAR1, FRINTTS) != 0; 970 } 971 972 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) 973 { 974 return FIELD_EX64_IDREG(id, ID_AA64ISAR1, DPB) != 0; 975 } 976 977 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) 978 { 979 return FIELD_EX64_IDREG(id, ID_AA64ISAR1, DPB) >= 2; 980 } 981 982 static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id) 983 { 984 return FIELD_EX64_IDREG(id, ID_AA64ISAR1, BF16) != 0; 985 } 986 987 static inline bool isar_feature_aa64_ebf16(const ARMISARegisters *id) 988 { 989 return FIELD_EX64_IDREG(id, ID_AA64ISAR1, BF16) > 1; 990 } 991 992 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) 993 { 994 return FIELD_EX64_IDREG(id, ID_AA64ISAR1, LRCPC) != 0; 995 } 996 997 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) 998 { 999 return FIELD_EX64_IDREG(id, ID_AA64ISAR1, LRCPC) >= 2; 1000 } 1001 1002 static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id) 1003 { 1004 return FIELD_EX64_IDREG(id, ID_AA64ISAR1, I8MM) != 0; 1005 } 1006 1007 static inline bool isar_feature_aa64_wfxt(const ARMISARegisters *id) 1008 { 1009 return FIELD_EX64_IDREG(id, ID_AA64ISAR2, WFXT) >= 2; 1010 } 1011 1012 static inline bool isar_feature_aa64_hbc(const ARMISARegisters *id) 1013 { 1014 return FIELD_EX64_IDREG(id, ID_AA64ISAR2, BC) != 0; 1015 } 1016 1017 static inline bool isar_feature_aa64_mops(const ARMISARegisters *id) 1018 { 1019 return FIELD_EX64_IDREG(id, ID_AA64ISAR2, MOPS); 1020 } 1021 1022 static inline bool isar_feature_aa64_rpres(const ARMISARegisters *id) 1023 { 1024 return FIELD_EX64_IDREG(id, ID_AA64ISAR2, RPRES); 1025 } 1026 1027 static inline bool isar_feature_aa64_cssc(const ARMISARegisters *id) 1028 { 1029 return FIELD_EX64_IDREG(id, ID_AA64ISAR2, CSSC) != 0; 1030 } 1031 1032 static inline bool isar_feature_aa64_lut(const ARMISARegisters *id) 1033 { 1034 return FIELD_EX64_IDREG(id, ID_AA64ISAR2, LUT); 1035 } 1036 1037 static inline bool isar_feature_aa64_ats1a(const ARMISARegisters *id) 1038 { 1039 return FIELD_EX64_IDREG(id, ID_AA64ISAR2, ATS1A); 1040 } 1041 1042 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) 1043 { 1044 /* We always set the AdvSIMD and FP fields identically. */ 1045 return FIELD_EX64_IDREG(id, ID_AA64PFR0, FP) != 0xf; 1046 } 1047 1048 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 1049 { 1050 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 1051 return FIELD_EX64_IDREG(id, ID_AA64PFR0, FP) == 1; 1052 } 1053 1054 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 1055 { 1056 return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL0) >= 2; 1057 } 1058 1059 static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) 1060 { 1061 return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL1) >= 2; 1062 } 1063 1064 static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id) 1065 { 1066 return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL2) >= 2; 1067 } 1068 1069 static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) 1070 { 1071 return FIELD_EX64_IDREG(id, ID_AA64PFR0, RAS) != 0; 1072 } 1073 1074 static inline bool isar_feature_aa64_doublefault(const ARMISARegisters *id) 1075 { 1076 return FIELD_EX64_IDREG(id, ID_AA64PFR0, RAS) >= 2; 1077 } 1078 1079 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 1080 { 1081 return FIELD_EX64_IDREG(id, ID_AA64PFR0, SVE) != 0; 1082 } 1083 1084 static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) 1085 { 1086 return FIELD_EX64_IDREG(id, ID_AA64PFR0, SEL2) != 0; 1087 } 1088 1089 static inline bool isar_feature_aa64_rme(const ARMISARegisters *id) 1090 { 1091 return FIELD_EX64_IDREG(id, ID_AA64PFR0, RME) != 0; 1092 } 1093 1094 static inline bool isar_feature_aa64_rme_gpc2(const ARMISARegisters *id) 1095 { 1096 return FIELD_EX64_IDREG(id, ID_AA64PFR0, RME) >= 2; 1097 } 1098 1099 static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) 1100 { 1101 return FIELD_EX64_IDREG(id, ID_AA64PFR0, DIT) != 0; 1102 } 1103 1104 static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) 1105 { 1106 int key = FIELD_EX64_IDREG(id, ID_AA64PFR0, CSV2); 1107 if (key >= 2) { 1108 return true; /* FEAT_CSV2_2 */ 1109 } 1110 if (key == 1) { 1111 key = FIELD_EX64_IDREG(id, ID_AA64PFR1, CSV2_FRAC); 1112 return key >= 2; /* FEAT_CSV2_1p2 */ 1113 } 1114 return false; 1115 } 1116 1117 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) 1118 { 1119 return FIELD_EX64_IDREG(id, ID_AA64PFR1, SSBS) != 0; 1120 } 1121 1122 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 1123 { 1124 return FIELD_EX64_IDREG(id, ID_AA64PFR1, BT) != 0; 1125 } 1126 1127 static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) 1128 { 1129 return FIELD_EX64_IDREG(id, ID_AA64PFR1, MTE) != 0; 1130 } 1131 1132 static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) 1133 { 1134 return FIELD_EX64_IDREG(id, ID_AA64PFR1, MTE) >= 2; 1135 } 1136 1137 static inline bool isar_feature_aa64_mte3(const ARMISARegisters *id) 1138 { 1139 return FIELD_EX64_IDREG(id, ID_AA64PFR1, MTE) >= 3; 1140 } 1141 1142 static inline bool isar_feature_aa64_sme(const ARMISARegisters *id) 1143 { 1144 return FIELD_EX64_IDREG(id, ID_AA64PFR1, SME) != 0; 1145 } 1146 1147 static inline bool isar_feature_aa64_nmi(const ARMISARegisters *id) 1148 { 1149 return FIELD_EX64_IDREG(id, ID_AA64PFR1, NMI) != 0; 1150 } 1151 1152 static inline bool isar_feature_aa64_gcs(const ARMISARegisters *id) 1153 { 1154 return FIELD_EX64_IDREG(id, ID_AA64PFR1, GCS) != 0; 1155 } 1156 1157 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) 1158 { 1159 return FIELD_SEX64_IDREG(id, ID_AA64MMFR0, TGRAN4) >= 1; 1160 } 1161 1162 static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id) 1163 { 1164 unsigned t = FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN4_2); 1165 return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id)); 1166 } 1167 1168 static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id) 1169 { 1170 return FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN16) >= 2; 1171 } 1172 1173 static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id) 1174 { 1175 unsigned t = FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN16_2); 1176 return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id)); 1177 } 1178 1179 static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id) 1180 { 1181 return FIELD_SEX64_IDREG(id, ID_AA64MMFR0, TGRAN4) >= 0; 1182 } 1183 1184 static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id) 1185 { 1186 return FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN16) >= 1; 1187 } 1188 1189 static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id) 1190 { 1191 return FIELD_SEX64_IDREG(id, ID_AA64MMFR0, TGRAN64) >= 0; 1192 } 1193 1194 static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id) 1195 { 1196 unsigned t = FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN4_2); 1197 return t >= 2 || (t == 0 && isar_feature_aa64_tgran4(id)); 1198 } 1199 1200 static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id) 1201 { 1202 unsigned t = FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN16_2); 1203 return t >= 2 || (t == 0 && isar_feature_aa64_tgran16(id)); 1204 } 1205 1206 static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id) 1207 { 1208 unsigned t = FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN64_2); 1209 return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id)); 1210 } 1211 1212 static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id) 1213 { 1214 return FIELD_EX64_IDREG(id, ID_AA64MMFR0, FGT) != 0; 1215 } 1216 1217 static inline bool isar_feature_aa64_ecv_traps(const ARMISARegisters *id) 1218 { 1219 return FIELD_EX64_IDREG(id, ID_AA64MMFR0, ECV) > 0; 1220 } 1221 1222 static inline bool isar_feature_aa64_ecv(const ARMISARegisters *id) 1223 { 1224 return FIELD_EX64_IDREG(id, ID_AA64MMFR0, ECV) > 1; 1225 } 1226 1227 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) 1228 { 1229 return FIELD_EX64_IDREG(id, ID_AA64MMFR1, VH) != 0; 1230 } 1231 1232 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 1233 { 1234 return FIELD_EX64_IDREG(id, ID_AA64MMFR1, LO) != 0; 1235 } 1236 1237 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) 1238 { 1239 return FIELD_EX64_IDREG(id, ID_AA64MMFR1, PAN) != 0; 1240 } 1241 1242 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) 1243 { 1244 return FIELD_EX64_IDREG(id, ID_AA64MMFR1, PAN) >= 2; 1245 } 1246 1247 static inline bool isar_feature_aa64_pan3(const ARMISARegisters *id) 1248 { 1249 return FIELD_EX64_IDREG(id, ID_AA64MMFR1, PAN) >= 3; 1250 } 1251 1252 static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id) 1253 { 1254 return FIELD_EX64_IDREG(id, ID_AA64MMFR1, HCX) != 0; 1255 } 1256 1257 static inline bool isar_feature_aa64_afp(const ARMISARegisters *id) 1258 { 1259 return FIELD_EX64_IDREG(id, ID_AA64MMFR1, AFP) != 0; 1260 } 1261 1262 static inline bool isar_feature_aa64_tidcp1(const ARMISARegisters *id) 1263 { 1264 return FIELD_EX64_IDREG(id, ID_AA64MMFR1, TIDCP1) != 0; 1265 } 1266 1267 static inline bool isar_feature_aa64_cmow(const ARMISARegisters *id) 1268 { 1269 return FIELD_EX64_IDREG(id, ID_AA64MMFR1, CMOW) != 0; 1270 } 1271 1272 static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id) 1273 { 1274 return FIELD_EX64_IDREG(id, ID_AA64MMFR1, HAFDBS) != 0; 1275 } 1276 1277 static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id) 1278 { 1279 return FIELD_EX64_IDREG(id, ID_AA64MMFR1, HAFDBS) >= 2; 1280 } 1281 1282 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) 1283 { 1284 return FIELD_EX64_IDREG(id, ID_AA64MMFR1, XNX) != 0; 1285 } 1286 1287 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) 1288 { 1289 return FIELD_EX64_IDREG(id, ID_AA64MMFR2, UAO) != 0; 1290 } 1291 1292 static inline bool isar_feature_aa64_st(const ARMISARegisters *id) 1293 { 1294 return FIELD_EX64_IDREG(id, ID_AA64MMFR2, ST) != 0; 1295 } 1296 1297 static inline bool isar_feature_aa64_lse2(const ARMISARegisters *id) 1298 { 1299 return FIELD_EX64_IDREG(id, ID_AA64MMFR2, AT) != 0; 1300 } 1301 1302 static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id) 1303 { 1304 return FIELD_EX64_IDREG(id, ID_AA64MMFR2, FWB) != 0; 1305 } 1306 1307 static inline bool isar_feature_aa64_ids(const ARMISARegisters *id) 1308 { 1309 return FIELD_EX64_IDREG(id, ID_AA64MMFR2, IDS) != 0; 1310 } 1311 1312 static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id) 1313 { 1314 return FIELD_EX64_IDREG(id, ID_AA64MMFR2, EVT) >= 1; 1315 } 1316 1317 static inline bool isar_feature_aa64_evt(const ARMISARegisters *id) 1318 { 1319 return FIELD_EX64_IDREG(id, ID_AA64MMFR2, EVT) >= 2; 1320 } 1321 1322 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) 1323 { 1324 return FIELD_EX64_IDREG(id, ID_AA64MMFR2, CCIDX) != 0; 1325 } 1326 1327 static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) 1328 { 1329 return FIELD_EX64_IDREG(id, ID_AA64MMFR2, VARANGE) != 0; 1330 } 1331 1332 static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id) 1333 { 1334 return FIELD_EX64_IDREG(id, ID_AA64MMFR2, E0PD) != 0; 1335 } 1336 1337 static inline bool isar_feature_aa64_nv(const ARMISARegisters *id) 1338 { 1339 return FIELD_EX64_IDREG(id, ID_AA64MMFR2, NV) != 0; 1340 } 1341 1342 static inline bool isar_feature_aa64_nv2(const ARMISARegisters *id) 1343 { 1344 return FIELD_EX64_IDREG(id, ID_AA64MMFR2, NV) >= 2; 1345 } 1346 1347 static inline bool isar_feature_aa64_tcr2(const ARMISARegisters *id) 1348 { 1349 return FIELD_EX64_IDREG(id, ID_AA64MMFR3, TCRX) != 0; 1350 } 1351 1352 static inline bool isar_feature_aa64_sctlr2(const ARMISARegisters *id) 1353 { 1354 return FIELD_EX64_IDREG(id, ID_AA64MMFR3, SCTLRX) != 0; 1355 } 1356 1357 static inline bool isar_feature_aa64_s1pie(const ARMISARegisters *id) 1358 { 1359 return FIELD_EX64_IDREG(id, ID_AA64MMFR3, S1PIE) != 0; 1360 } 1361 1362 static inline bool isar_feature_aa64_s2pie(const ARMISARegisters *id) 1363 { 1364 return FIELD_EX64_IDREG(id, ID_AA64MMFR3, S2PIE) != 0; 1365 } 1366 1367 static inline bool isar_feature_aa64_aie(const ARMISARegisters *id) 1368 { 1369 return FIELD_EX64_IDREG(id, ID_AA64MMFR3, AIE) != 0; 1370 } 1371 1372 static inline bool isar_feature_aa64_mec(const ARMISARegisters *id) 1373 { 1374 return FIELD_EX64_IDREG(id, ID_AA64MMFR3, MEC) != 0; 1375 } 1376 1377 static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) 1378 { 1379 return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >= 4 && 1380 FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) != 0xf; 1381 } 1382 1383 static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id) 1384 { 1385 return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >= 5 && 1386 FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) != 0xf; 1387 } 1388 1389 static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id) 1390 { 1391 return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >= 6 && 1392 FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) != 0xf; 1393 } 1394 1395 static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) 1396 { 1397 return FIELD_EX64_IDREG(id, ID_AA64DFR0, DEBUGVER) >= 8; 1398 } 1399 1400 static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id) 1401 { 1402 return FIELD_SEX64_IDREG(id, ID_AA64DFR0, DOUBLELOCK) >= 0; 1403 } 1404 1405 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) 1406 { 1407 return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SVEVER) != 0; 1408 } 1409 1410 static inline bool isar_feature_aa64_sve2p1(const ARMISARegisters *id) 1411 { 1412 return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SVEVER) >=2; 1413 } 1414 1415 static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id) 1416 { 1417 return FIELD_EX64_IDREG(id, ID_AA64ZFR0, AES) != 0; 1418 } 1419 1420 static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id) 1421 { 1422 return FIELD_EX64_IDREG(id, ID_AA64ZFR0, AES) >= 2; 1423 } 1424 1425 static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id) 1426 { 1427 return FIELD_EX64_IDREG(id, ID_AA64ZFR0, BITPERM) != 0; 1428 } 1429 1430 static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) 1431 { 1432 return FIELD_EX64_IDREG(id, ID_AA64ZFR0, BFLOAT16) != 0; 1433 } 1434 1435 static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id) 1436 { 1437 return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SHA3) != 0; 1438 } 1439 1440 static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id) 1441 { 1442 return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SM4) != 0; 1443 } 1444 1445 static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id) 1446 { 1447 return FIELD_EX64_IDREG(id, ID_AA64ZFR0, I8MM) != 0; 1448 } 1449 1450 static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id) 1451 { 1452 return FIELD_EX64_IDREG(id, ID_AA64ZFR0, F32MM) != 0; 1453 } 1454 1455 static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id) 1456 { 1457 return FIELD_EX64_IDREG(id, ID_AA64ZFR0, F64MM) != 0; 1458 } 1459 1460 static inline bool isar_feature_aa64_sve_b16b16(const ARMISARegisters *id) 1461 { 1462 return FIELD_EX64_IDREG(id, ID_AA64ZFR0, B16B16); 1463 } 1464 1465 static inline bool isar_feature_aa64_sme_b16b16(const ARMISARegisters *id) 1466 { 1467 return FIELD_EX64_IDREG(id, ID_AA64SMFR0, B16B16); 1468 } 1469 1470 static inline bool isar_feature_aa64_sme_f16f16(const ARMISARegisters *id) 1471 { 1472 return FIELD_EX64_IDREG(id, ID_AA64SMFR0, F16F16); 1473 } 1474 1475 static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id) 1476 { 1477 return FIELD_EX64_IDREG(id, ID_AA64SMFR0, F64F64); 1478 } 1479 1480 static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters *id) 1481 { 1482 return FIELD_EX64_IDREG(id, ID_AA64SMFR0, I16I64) == 0xf; 1483 } 1484 1485 static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id) 1486 { 1487 return FIELD_EX64_IDREG(id, ID_AA64SMFR0, FA64); 1488 } 1489 1490 static inline bool isar_feature_aa64_sme2(const ARMISARegisters *id) 1491 { 1492 return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SMEVER) != 0; 1493 } 1494 1495 static inline bool isar_feature_aa64_sme2p1(const ARMISARegisters *id) 1496 { 1497 return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SMEVER) >= 2; 1498 } 1499 1500 /* 1501 * Combinations of feature tests, for ease of use with TRANS_FEAT. 1502 */ 1503 static inline bool isar_feature_aa64_sme_or_sve2p1(const ARMISARegisters *id) 1504 { 1505 return isar_feature_aa64_sme(id) || isar_feature_aa64_sve2p1(id); 1506 } 1507 1508 static inline bool isar_feature_aa64_sme2_or_sve2p1(const ARMISARegisters *id) 1509 { 1510 return isar_feature_aa64_sme2(id) || isar_feature_aa64_sve2p1(id); 1511 } 1512 1513 static inline bool isar_feature_aa64_sme2p1_or_sve2p1(const ARMISARegisters *id) 1514 { 1515 return isar_feature_aa64_sme2p1(id) || isar_feature_aa64_sve2p1(id); 1516 } 1517 1518 static inline bool isar_feature_aa64_sme2_i16i64(const ARMISARegisters *id) 1519 { 1520 return isar_feature_aa64_sme2(id) && isar_feature_aa64_sme_i16i64(id); 1521 } 1522 1523 static inline bool isar_feature_aa64_sme2_f64f64(const ARMISARegisters *id) 1524 { 1525 return isar_feature_aa64_sme2(id) && isar_feature_aa64_sme_f64f64(id); 1526 } 1527 1528 /* 1529 * Feature tests for "does this exist in either 32-bit or 64-bit?" 1530 */ 1531 static inline bool isar_feature_any_fp16(const ARMISARegisters *id) 1532 { 1533 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); 1534 } 1535 1536 static inline bool isar_feature_any_predinv(const ARMISARegisters *id) 1537 { 1538 return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); 1539 } 1540 1541 static inline bool isar_feature_any_pmuv3p1(const ARMISARegisters *id) 1542 { 1543 return isar_feature_aa64_pmuv3p1(id) || isar_feature_aa32_pmuv3p1(id); 1544 } 1545 1546 static inline bool isar_feature_any_pmuv3p4(const ARMISARegisters *id) 1547 { 1548 return isar_feature_aa64_pmuv3p4(id) || isar_feature_aa32_pmuv3p4(id); 1549 } 1550 1551 static inline bool isar_feature_any_pmuv3p5(const ARMISARegisters *id) 1552 { 1553 return isar_feature_aa64_pmuv3p5(id) || isar_feature_aa32_pmuv3p5(id); 1554 } 1555 1556 static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) 1557 { 1558 return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); 1559 } 1560 1561 static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id) 1562 { 1563 return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); 1564 } 1565 1566 static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id) 1567 { 1568 return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id); 1569 } 1570 1571 static inline bool isar_feature_any_ras(const ARMISARegisters *id) 1572 { 1573 return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id); 1574 } 1575 1576 static inline bool isar_feature_any_half_evt(const ARMISARegisters *id) 1577 { 1578 return isar_feature_aa64_half_evt(id) || isar_feature_aa32_half_evt(id); 1579 } 1580 1581 static inline bool isar_feature_any_evt(const ARMISARegisters *id) 1582 { 1583 return isar_feature_aa64_evt(id) || isar_feature_aa32_evt(id); 1584 } 1585 1586 typedef enum { 1587 CCSIDR_FORMAT_LEGACY, 1588 CCSIDR_FORMAT_CCIDX, 1589 } CCSIDRFormat; 1590 1591 static inline uint64_t make_ccsidr(CCSIDRFormat format, unsigned assoc, 1592 unsigned linesize, unsigned cachesize, 1593 uint8_t flags) 1594 { 1595 unsigned lg_linesize = ctz32(linesize); 1596 unsigned sets; 1597 uint64_t ccsidr = 0; 1598 1599 assert(assoc != 0); 1600 assert(is_power_of_2(linesize)); 1601 assert(lg_linesize >= 4 && lg_linesize <= 7 + 4); 1602 1603 /* sets * associativity * linesize == cachesize. */ 1604 sets = cachesize / (assoc * linesize); 1605 assert(cachesize % (assoc * linesize) == 0); 1606 1607 if (format == CCSIDR_FORMAT_LEGACY) { 1608 /* 1609 * The 32-bit CCSIDR format is: 1610 * [27:13] number of sets - 1 1611 * [12:3] associativity - 1 1612 * [2:0] log2(linesize) - 4 1613 * so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc 1614 */ 1615 ccsidr = deposit32(ccsidr, 28, 4, flags); 1616 ccsidr = deposit32(ccsidr, 13, 15, sets - 1); 1617 ccsidr = deposit32(ccsidr, 3, 10, assoc - 1); 1618 ccsidr = deposit32(ccsidr, 0, 3, lg_linesize - 4); 1619 } else { 1620 /* 1621 * The 64-bit CCSIDR_EL1 format is: 1622 * [55:32] number of sets - 1 1623 * [23:3] associativity - 1 1624 * [2:0] log2(linesize) - 4 1625 * so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc 1626 */ 1627 ccsidr = deposit64(ccsidr, 32, 24, sets - 1); 1628 ccsidr = deposit64(ccsidr, 3, 21, assoc - 1); 1629 ccsidr = deposit64(ccsidr, 0, 3, lg_linesize - 4); 1630 } 1631 1632 return ccsidr; 1633 } 1634 1635 /* 1636 * Forward to the above feature tests given an ARMCPU pointer. 1637 */ 1638 #define cpu_isar_feature(name, cpu) \ 1639 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 1640 1641 #endif 1642