xref: /openbmc/u-boot/drivers/net/phy/atheros.c (revision fc82e768)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Atheros PHY drivers
4  *
5  * Copyright 2011, 2013 Freescale Semiconductor, Inc.
6  * author Andy Fleming
7  */
8 #include <common.h>
9 #include <phy.h>
10 
11 #define AR803x_PHY_DEBUG_ADDR_REG	0x1d
12 #define AR803x_PHY_DEBUG_DATA_REG	0x1e
13 
14 #define AR803x_DEBUG_REG_5		0x5
15 #define AR803x_RGMII_TX_CLK_DLY		0x100
16 
17 #define AR803x_DEBUG_REG_0		0x0
18 #define AR803x_RGMII_RX_CLK_DLY		0x8000
19 
ar8021_config(struct phy_device * phydev)20 static int ar8021_config(struct phy_device *phydev)
21 {
22 	phy_write(phydev, MDIO_DEVAD_NONE, 0x00, 0x1200);
23 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
24 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
25 
26 	phydev->supported = phydev->drv->features;
27 	return 0;
28 }
29 
ar8031_config(struct phy_device * phydev)30 static int ar8031_config(struct phy_device *phydev)
31 {
32 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
33 	    phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
34 		phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
35 			  AR803x_DEBUG_REG_5);
36 		phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG,
37 			  AR803x_RGMII_TX_CLK_DLY);
38 	}
39 
40 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
41 	    phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
42 		phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
43 			  AR803x_DEBUG_REG_0);
44 		phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG,
45 			  AR803x_RGMII_RX_CLK_DLY);
46 	}
47 
48 	phydev->supported = phydev->drv->features;
49 
50 	genphy_config_aneg(phydev);
51 	genphy_restart_aneg(phydev);
52 
53 	return 0;
54 }
55 
ar8035_config(struct phy_device * phydev)56 static int ar8035_config(struct phy_device *phydev)
57 {
58 	int regval;
59 
60 	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x0007);
61 	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
62 	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
63 	regval = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
64 	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018));
65 
66 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
67 	regval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
68 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, (regval|0x0100));
69 
70 	if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
71 	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
72 		/* select debug reg 5 */
73 		phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x5);
74 		/* enable tx delay */
75 		phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x0100);
76 	}
77 
78 	if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
79 	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)) {
80 		/* select debug reg 0 */
81 		phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x0);
82 		/* enable rx delay */
83 		phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x8000);
84 	}
85 
86 	phydev->supported = phydev->drv->features;
87 
88 	genphy_config_aneg(phydev);
89 	genphy_restart_aneg(phydev);
90 
91 	return 0;
92 }
93 
94 static struct phy_driver AR8021_driver =  {
95 	.name = "AR8021",
96 	.uid = 0x4dd040,
97 	.mask = 0x4ffff0,
98 	.features = PHY_GBIT_FEATURES,
99 	.config = ar8021_config,
100 	.startup = genphy_startup,
101 	.shutdown = genphy_shutdown,
102 };
103 
104 static struct phy_driver AR8031_driver =  {
105 	.name = "AR8031/AR8033",
106 	.uid = 0x4dd074,
107 	.mask = 0xffffffef,
108 	.features = PHY_GBIT_FEATURES,
109 	.config = ar8031_config,
110 	.startup = genphy_startup,
111 	.shutdown = genphy_shutdown,
112 };
113 
114 static struct phy_driver AR8035_driver =  {
115 	.name = "AR8035",
116 	.uid = 0x4dd072,
117 	.mask = 0xffffffef,
118 	.features = PHY_GBIT_FEATURES,
119 	.config = ar8035_config,
120 	.startup = genphy_startup,
121 	.shutdown = genphy_shutdown,
122 };
123 
phy_atheros_init(void)124 int phy_atheros_init(void)
125 {
126 	phy_register(&AR8021_driver);
127 	phy_register(&AR8031_driver);
128 	phy_register(&AR8035_driver);
129 
130 	return 0;
131 }
132