xref: /openbmc/linux/drivers/net/wireless/ath/ath5k/desc.h (revision c47faa36)
1 /*
2  * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3  * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4  *
5  * Permission to use, copy, modify, and distribute this software for any
6  * purpose with or without fee is hereby granted, provided that the above
7  * copyright notice and this permission notice appear in all copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16  *
17  */
18 
19 /*
20  * RX/TX descriptor structures
21  */
22 
23 /**
24  * struct ath5k_hw_rx_ctl - Common hardware RX control descriptor
25  * @rx_control_0: RX control word 0
26  * @rx_control_1: RX control word 1
27  */
28 struct ath5k_hw_rx_ctl {
29 	u32	rx_control_0;
30 	u32	rx_control_1;
31 } __packed __aligned(4);
32 
33 /* RX control word 1 fields/flags */
34 #define AR5K_DESC_RX_CTL1_BUF_LEN		0x00000fff /* data buffer length */
35 #define AR5K_DESC_RX_CTL1_INTREQ		0x00002000 /* RX interrupt request */
36 
37 /**
38  * struct ath5k_hw_rx_status - Common hardware RX status descriptor
39  * @rx_status_0: RX status word 0
40  * @rx_status_1: RX status word 1
41  *
42  * 5210, 5211 and 5212 differ only in the fields and flags defined below
43  */
44 struct ath5k_hw_rx_status {
45 	u32	rx_status_0;
46 	u32	rx_status_1;
47 } __packed __aligned(4);
48 
49 /* 5210/5211 */
50 /* RX status word 0 fields/flags */
51 #define AR5K_5210_RX_DESC_STATUS0_DATA_LEN		0x00000fff /* RX data length */
52 #define AR5K_5210_RX_DESC_STATUS0_MORE			0x00001000 /* more desc for this frame */
53 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5210	0x00004000 /* [5210] receive on ant 1 */
54 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE		0x00078000 /* reception rate */
55 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE_S	15
56 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL	0x07f80000 /* rssi */
57 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL_S	19
58 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5211	0x38000000 /* [5211] receive antenna */
59 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5211_S	27
60 
61 /* RX status word 1 fields/flags */
62 #define AR5K_5210_RX_DESC_STATUS1_DONE			0x00000001 /* descriptor complete */
63 #define AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK	0x00000002 /* reception success */
64 #define AR5K_5210_RX_DESC_STATUS1_CRC_ERROR		0x00000004 /* CRC error */
65 #define AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN_5210	0x00000008 /* [5210] FIFO overrun */
66 #define AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR	0x00000010 /* decryption CRC failure */
67 #define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR		0x000000e0 /* PHY error */
68 #define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR_S		5
69 #define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID	0x00000100 /* key index valid */
70 #define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX		0x00007e00 /* decryption key index */
71 #define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_S		9
72 #define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP	0x0fff8000 /* 13 bit of TSF */
73 #define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S	15
74 #define AR5K_5210_RX_DESC_STATUS1_KEY_CACHE_MISS	0x10000000 /* key cache miss */
75 
76 /* 5212 */
77 /* RX status word 0 fields/flags */
78 #define AR5K_5212_RX_DESC_STATUS0_DATA_LEN		0x00000fff /* RX data length */
79 #define AR5K_5212_RX_DESC_STATUS0_MORE			0x00001000 /* more desc for this frame */
80 #define AR5K_5212_RX_DESC_STATUS0_DECOMP_CRC_ERROR	0x00002000 /* decompression CRC error */
81 #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE		0x000f8000 /* reception rate */
82 #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE_S	15
83 #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL	0x0ff00000 /* rssi */
84 #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL_S	20
85 #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA	0xf0000000 /* receive antenna */
86 #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA_S	28
87 
88 /* RX status word 1 fields/flags */
89 #define AR5K_5212_RX_DESC_STATUS1_DONE			0x00000001 /* descriptor complete */
90 #define AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK	0x00000002 /* frame reception success */
91 #define AR5K_5212_RX_DESC_STATUS1_CRC_ERROR		0x00000004 /* CRC error */
92 #define AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR	0x00000008 /* decryption CRC failure */
93 #define AR5K_5212_RX_DESC_STATUS1_PHY_ERROR		0x00000010 /* PHY error */
94 #define AR5K_5212_RX_DESC_STATUS1_MIC_ERROR		0x00000020 /* MIC decrypt error */
95 #define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID	0x00000100 /* key index valid */
96 #define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX		0x0000fe00 /* decryption key index */
97 #define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_S		9
98 #define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP	0x7fff0000 /* first 15bit of the TSF */
99 #define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S	16
100 #define AR5K_5212_RX_DESC_STATUS1_KEY_CACHE_MISS	0x80000000 /* key cache miss */
101 #define AR5K_5212_RX_DESC_STATUS1_PHY_ERROR_CODE	0x0000ff00 /* phy error code overlays key index and valid fields */
102 #define AR5K_5212_RX_DESC_STATUS1_PHY_ERROR_CODE_S	8
103 
104 /**
105  * enum ath5k_phy_error_code - PHY Error codes
106  * @AR5K_RX_PHY_ERROR_UNDERRUN: Transmit underrun, [5210] No error
107  * @AR5K_RX_PHY_ERROR_TIMING: Timing error
108  * @AR5K_RX_PHY_ERROR_PARITY: Illegal parity
109  * @AR5K_RX_PHY_ERROR_RATE: Illegal rate
110  * @AR5K_RX_PHY_ERROR_LENGTH: Illegal length
111  * @AR5K_RX_PHY_ERROR_RADAR: Radar detect, [5210] 64 QAM rate
112  * @AR5K_RX_PHY_ERROR_SERVICE: Illegal service
113  * @AR5K_RX_PHY_ERROR_TOR: Transmit override receive
114  * @AR5K_RX_PHY_ERROR_OFDM_TIMING: OFDM Timing error [5212+]
115  * @AR5K_RX_PHY_ERROR_OFDM_SIGNAL_PARITY: OFDM Signal parity error [5212+]
116  * @AR5K_RX_PHY_ERROR_OFDM_RATE_ILLEGAL: OFDM Illegal rate [5212+]
117  * @AR5K_RX_PHY_ERROR_OFDM_LENGTH_ILLEGAL: OFDM Illegal length [5212+]
118  * @AR5K_RX_PHY_ERROR_OFDM_POWER_DROP: OFDM Power drop [5212+]
119  * @AR5K_RX_PHY_ERROR_OFDM_SERVICE: OFDM Service (?) [5212+]
120  * @AR5K_RX_PHY_ERROR_OFDM_RESTART: OFDM Restart (?) [5212+]
121  * @AR5K_RX_PHY_ERROR_CCK_TIMING: CCK Timing error [5212+]
122  * @AR5K_RX_PHY_ERROR_CCK_HEADER_CRC: Header CRC error [5212+]
123  * @AR5K_RX_PHY_ERROR_CCK_RATE_ILLEGAL: Illegal rate [5212+]
124  * @AR5K_RX_PHY_ERROR_CCK_SERVICE: CCK Service (?) [5212+]
125  * @AR5K_RX_PHY_ERROR_CCK_RESTART: CCK Restart (?) [5212+]
126  */
127 enum ath5k_phy_error_code {
128 	AR5K_RX_PHY_ERROR_UNDERRUN		= 0,
129 	AR5K_RX_PHY_ERROR_TIMING		= 1,
130 	AR5K_RX_PHY_ERROR_PARITY		= 2,
131 	AR5K_RX_PHY_ERROR_RATE			= 3,
132 	AR5K_RX_PHY_ERROR_LENGTH		= 4,
133 	AR5K_RX_PHY_ERROR_RADAR			= 5,
134 	AR5K_RX_PHY_ERROR_SERVICE		= 6,
135 	AR5K_RX_PHY_ERROR_TOR			= 7,
136 	AR5K_RX_PHY_ERROR_OFDM_TIMING		= 17,
137 	AR5K_RX_PHY_ERROR_OFDM_SIGNAL_PARITY	= 18,
138 	AR5K_RX_PHY_ERROR_OFDM_RATE_ILLEGAL	= 19,
139 	AR5K_RX_PHY_ERROR_OFDM_LENGTH_ILLEGAL	= 20,
140 	AR5K_RX_PHY_ERROR_OFDM_POWER_DROP	= 21,
141 	AR5K_RX_PHY_ERROR_OFDM_SERVICE		= 22,
142 	AR5K_RX_PHY_ERROR_OFDM_RESTART		= 23,
143 	AR5K_RX_PHY_ERROR_CCK_TIMING		= 25,
144 	AR5K_RX_PHY_ERROR_CCK_HEADER_CRC	= 26,
145 	AR5K_RX_PHY_ERROR_CCK_RATE_ILLEGAL	= 27,
146 	AR5K_RX_PHY_ERROR_CCK_SERVICE		= 30,
147 	AR5K_RX_PHY_ERROR_CCK_RESTART		= 31,
148 };
149 
150 /**
151  * struct ath5k_hw_2w_tx_ctl  - 5210/5211 hardware 2-word TX control descriptor
152  * @tx_control_0: TX control word 0
153  * @tx_control_1: TX control word 1
154  */
155 struct ath5k_hw_2w_tx_ctl {
156 	u32	tx_control_0;
157 	u32	tx_control_1;
158 } __packed __aligned(4);
159 
160 /* TX control word 0 fields/flags */
161 #define AR5K_2W_TX_DESC_CTL0_FRAME_LEN		0x00000fff /* frame length */
162 #define AR5K_2W_TX_DESC_CTL0_HEADER_LEN_5210	0x0003f000 /* [5210] header length */
163 #define AR5K_2W_TX_DESC_CTL0_HEADER_LEN_5210_S	12
164 #define AR5K_2W_TX_DESC_CTL0_XMIT_RATE		0x003c0000 /* tx rate */
165 #define AR5K_2W_TX_DESC_CTL0_XMIT_RATE_S	18
166 #define AR5K_2W_TX_DESC_CTL0_RTSENA		0x00400000 /* RTS/CTS enable */
167 #define AR5K_2W_TX_DESC_CTL0_LONG_PACKET_5210	0x00800000 /* [5210] long packet */
168 #define AR5K_2W_TX_DESC_CTL0_VEOL_5211		0x00800000 /* [5211] virtual end-of-list */
169 #define AR5K_2W_TX_DESC_CTL0_CLRDMASK		0x01000000 /* clear destination mask */
170 #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210	0x02000000 /* [5210] antenna selection */
171 #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211	0x1e000000 /* [5211] antenna selection */
172 #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT			\
173 		(ah->ah_version == AR5K_AR5210 ?		\
174 		AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 :	\
175 		AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211)
176 #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_S	25
177 #define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_5210	0x1c000000 /* [5210] frame type */
178 #define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_5210_S	26
179 #define AR5K_2W_TX_DESC_CTL0_INTREQ		0x20000000 /* TX interrupt request */
180 #define AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID	0x40000000 /* key is valid */
181 
182 /* TX control word 1 fields/flags */
183 #define AR5K_2W_TX_DESC_CTL1_BUF_LEN		0x00000fff /* data buffer length */
184 #define AR5K_2W_TX_DESC_CTL1_MORE		0x00001000 /* more desc for this frame */
185 #define AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX_5210	0x0007e000 /* [5210] key table index */
186 #define AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX_5211	0x000fe000 /* [5211] key table index */
187 #define AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX				\
188 			(ah->ah_version == AR5K_AR5210 ?		\
189 			AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX_5210 :		\
190 			AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX_5211)
191 #define AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX_S	13
192 #define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_5211	0x00700000 /* [5211] frame type */
193 #define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_5211_S	20
194 #define AR5K_2W_TX_DESC_CTL1_NOACK_5211		0x00800000 /* [5211] no ACK */
195 #define AR5K_2W_TX_DESC_CTL1_RTS_DURATION_5210	0xfff80000 /* [5210] lower 13 bit of duration */
196 
197 /* Frame types */
198 #define AR5K_AR5210_TX_DESC_FRAME_TYPE_NORMAL	0
199 #define AR5K_AR5210_TX_DESC_FRAME_TYPE_ATIM	1
200 #define AR5K_AR5210_TX_DESC_FRAME_TYPE_PSPOLL	2
201 #define AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY	3
202 #define AR5K_AR5211_TX_DESC_FRAME_TYPE_BEACON	3
203 #define AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS	4
204 #define AR5K_AR5211_TX_DESC_FRAME_TYPE_PRESP	4
205 
206 /**
207  * struct ath5k_hw_4w_tx_ctl - 5212 hardware 4-word TX control descriptor
208  * @tx_control_0: TX control word 0
209  * @tx_control_1: TX control word 1
210  * @tx_control_2: TX control word 2
211  * @tx_control_3: TX control word 3
212  */
213 struct ath5k_hw_4w_tx_ctl {
214 	u32	tx_control_0;
215 	u32	tx_control_1;
216 	u32	tx_control_2;
217 	u32	tx_control_3;
218 } __packed __aligned(4);
219 
220 /* TX control word 0 fields/flags */
221 #define AR5K_4W_TX_DESC_CTL0_FRAME_LEN		0x00000fff /* frame length */
222 #define AR5K_4W_TX_DESC_CTL0_XMIT_POWER		0x003f0000 /* transmit power */
223 #define AR5K_4W_TX_DESC_CTL0_XMIT_POWER_S	16
224 #define AR5K_4W_TX_DESC_CTL0_RTSENA		0x00400000 /* RTS/CTS enable */
225 #define AR5K_4W_TX_DESC_CTL0_VEOL		0x00800000 /* virtual end-of-list */
226 #define AR5K_4W_TX_DESC_CTL0_CLRDMASK		0x01000000 /* clear destination mask */
227 #define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT	0x1e000000 /* TX antenna selection */
228 #define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT_S	25
229 #define AR5K_4W_TX_DESC_CTL0_INTREQ		0x20000000 /* TX interrupt request */
230 #define AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID	0x40000000 /* destination index valid */
231 #define AR5K_4W_TX_DESC_CTL0_CTSENA		0x80000000 /* precede frame with CTS */
232 
233 /* TX control word 1 fields/flags */
234 #define AR5K_4W_TX_DESC_CTL1_BUF_LEN		0x00000fff /* data buffer length */
235 #define AR5K_4W_TX_DESC_CTL1_MORE		0x00001000 /* more desc for this frame */
236 #define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_IDX	0x000fe000 /* destination table index */
237 #define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_IDX_S	13
238 #define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE		0x00f00000 /* frame type */
239 #define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE_S	20
240 #define AR5K_4W_TX_DESC_CTL1_NOACK		0x01000000 /* no ACK */
241 #define AR5K_4W_TX_DESC_CTL1_COMP_PROC		0x06000000 /* compression processing */
242 #define AR5K_4W_TX_DESC_CTL1_COMP_PROC_S	25
243 #define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN	0x18000000 /* length of frame IV */
244 #define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN_S	27
245 #define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN	0x60000000 /* length of frame ICV */
246 #define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN_S	29
247 
248 /* TX control word 2 fields/flags */
249 #define AR5K_4W_TX_DESC_CTL2_RTS_DURATION	0x00007fff /* RTS/CTS duration */
250 #define AR5K_4W_TX_DESC_CTL2_DURATION_UPD_EN	0x00008000 /* frame duration update */
251 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0	0x000f0000 /* series 0 max attempts */
252 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0_S	16
253 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1	0x00f00000 /* series 1 max attempts */
254 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1_S	20
255 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2	0x0f000000 /* series 2 max attempts */
256 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2_S	24
257 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3	0xf0000000 /* series 3 max attempts */
258 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3_S	28
259 
260 /* TX control word 3 fields/flags */
261 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE0		0x0000001f /* series 0 tx rate */
262 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1		0x000003e0 /* series 1 tx rate */
263 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1_S	5
264 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2		0x00007c00 /* series 2 tx rate */
265 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2_S	10
266 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3		0x000f8000 /* series 3 tx rate */
267 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3_S	15
268 #define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE	0x01f00000 /* RTS or CTS rate */
269 #define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE_S	20
270 
271 /**
272  * struct ath5k_hw_tx_status - Common TX status descriptor
273  * @tx_status_0: TX status word 0
274  * @tx_status_1: TX status word 1
275  */
276 struct ath5k_hw_tx_status {
277 	u32	tx_status_0;
278 	u32	tx_status_1;
279 } __packed __aligned(4);
280 
281 /* TX status word 0 fields/flags */
282 #define AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK	0x00000001 /* TX success */
283 #define AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES	0x00000002 /* excessive retries */
284 #define AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN	0x00000004 /* FIFO underrun */
285 #define AR5K_DESC_TX_STATUS0_FILTERED		0x00000008 /* TX filter indication */
286 /* according to the HAL sources the spec has short/long retry counts reversed.
287  * we have it reversed to the HAL sources as well, for 5210 and 5211.
288  * For 5212 these fields are defined as RTS_FAIL_COUNT and DATA_FAIL_COUNT,
289  * but used respectively as SHORT and LONG retry count in the code later. This
290  * is consistent with the definitions here... TODO: check */
291 #define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT	0x000000f0 /* short retry count */
292 #define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT_S	4
293 #define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT	0x00000f00 /* long retry count */
294 #define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT_S	8
295 #define AR5K_DESC_TX_STATUS0_VIRTCOLL_CT_5211	0x0000f000 /* [5211+] virtual collision count */
296 #define AR5K_DESC_TX_STATUS0_VIRTCOLL_CT_5212_S	12
297 #define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP	0xffff0000 /* TX timestamp */
298 #define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP_S	16
299 
300 /* TX status word 1 fields/flags */
301 #define AR5K_DESC_TX_STATUS1_DONE		0x00000001 /* descriptor complete */
302 #define AR5K_DESC_TX_STATUS1_SEQ_NUM		0x00001ffe /* TX sequence number */
303 #define AR5K_DESC_TX_STATUS1_SEQ_NUM_S		1
304 #define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH	0x001fe000 /* signal strength of ACK */
305 #define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S	13
306 #define AR5K_DESC_TX_STATUS1_FINAL_TS_IX_5212	0x00600000 /* [5212] final TX attempt series ix */
307 #define AR5K_DESC_TX_STATUS1_FINAL_TS_IX_5212_S	21
308 #define AR5K_DESC_TX_STATUS1_COMP_SUCCESS_5212	0x00800000 /* [5212] compression status */
309 #define AR5K_DESC_TX_STATUS1_XMIT_ANTENNA_5212	0x01000000 /* [5212] transmit antenna */
310 
311 /**
312  * struct ath5k_hw_5210_tx_desc - 5210/5211 hardware TX descriptor
313  * @tx_ctl: The &struct ath5k_hw_2w_tx_ctl
314  * @tx_stat: The &struct ath5k_hw_tx_status
315  */
316 struct ath5k_hw_5210_tx_desc {
317 	struct ath5k_hw_2w_tx_ctl	tx_ctl;
318 	struct ath5k_hw_tx_status	tx_stat;
319 } __packed __aligned(4);
320 
321 /**
322  * struct ath5k_hw_5212_tx_desc - 5212 hardware TX descriptor
323  * @tx_ctl: The &struct ath5k_hw_4w_tx_ctl
324  * @tx_stat: The &struct ath5k_hw_tx_status
325  */
326 struct ath5k_hw_5212_tx_desc {
327 	struct ath5k_hw_4w_tx_ctl	tx_ctl;
328 	struct ath5k_hw_tx_status	tx_stat;
329 } __packed __aligned(4);
330 
331 /**
332  * struct ath5k_hw_all_rx_desc - Common hardware RX descriptor
333  * @rx_ctl: The &struct ath5k_hw_rx_ctl
334  * @rx_stat: The &struct ath5k_hw_rx_status
335  */
336 struct ath5k_hw_all_rx_desc {
337 	struct ath5k_hw_rx_ctl		rx_ctl;
338 	struct ath5k_hw_rx_status	rx_stat;
339 } __packed __aligned(4);
340 
341 /**
342  * struct ath5k_desc - Atheros hardware DMA descriptor
343  * @ds_link: Physical address of the next descriptor
344  * @ds_data: Physical address of data buffer (skb)
345  * @ud: Union containing hw_5xxx_tx_desc structs and hw_all_rx_desc
346  *
347  * This is read and written to by the hardware
348  */
349 struct ath5k_desc {
350 	u32	ds_link;
351 	u32	ds_data;
352 
353 	union {
354 		struct ath5k_hw_5210_tx_desc	ds_tx5210;
355 		struct ath5k_hw_5212_tx_desc	ds_tx5212;
356 		struct ath5k_hw_all_rx_desc	ds_rx;
357 	} ud;
358 } __packed __aligned(4);
359 
360 #define AR5K_RXDESC_INTREQ	0x0020
361 
362 #define AR5K_TXDESC_CLRDMASK	0x0001
363 #define AR5K_TXDESC_NOACK	0x0002	/*[5211+]*/
364 #define AR5K_TXDESC_RTSENA	0x0004
365 #define AR5K_TXDESC_CTSENA	0x0008
366 #define AR5K_TXDESC_INTREQ	0x0010
367 #define AR5K_TXDESC_VEOL	0x0020	/*[5211+]*/
368