1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2012 ARM Ltd.
4 */
5 #ifndef __ASM_CPUTYPE_H
6 #define __ASM_CPUTYPE_H
7
8 #define INVALID_HWID ULONG_MAX
9
10 #define MPIDR_UP_BITMASK (0x1 << 30)
11 #define MPIDR_MT_BITMASK (0x1 << 24)
12 #define MPIDR_HWID_BITMASK UL(0xff00ffffff)
13
14 #define MPIDR_LEVEL_BITS_SHIFT 3
15 #define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT)
16 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
17
18 #define MPIDR_LEVEL_SHIFT(level) \
19 (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
20
21 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
22 ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
23
24 #define MIDR_REVISION_MASK 0xf
25 #define MIDR_REVISION(midr) ((midr) & MIDR_REVISION_MASK)
26 #define MIDR_PARTNUM_SHIFT 4
27 #define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT)
28 #define MIDR_PARTNUM(midr) \
29 (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
30 #define MIDR_ARCHITECTURE_SHIFT 16
31 #define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT)
32 #define MIDR_ARCHITECTURE(midr) \
33 (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
34 #define MIDR_VARIANT_SHIFT 20
35 #define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT)
36 #define MIDR_VARIANT(midr) \
37 (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
38 #define MIDR_IMPLEMENTOR_SHIFT 24
39 #define MIDR_IMPLEMENTOR_MASK (0xffU << MIDR_IMPLEMENTOR_SHIFT)
40 #define MIDR_IMPLEMENTOR(midr) \
41 (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
42
43 #define MIDR_CPU_MODEL(imp, partnum) \
44 ((_AT(u32, imp) << MIDR_IMPLEMENTOR_SHIFT) | \
45 (0xf << MIDR_ARCHITECTURE_SHIFT) | \
46 ((partnum) << MIDR_PARTNUM_SHIFT))
47
48 #define MIDR_CPU_VAR_REV(var, rev) \
49 (((var) << MIDR_VARIANT_SHIFT) | (rev))
50
51 #define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \
52 MIDR_ARCHITECTURE_MASK)
53
54 #define ARM_CPU_IMP_ARM 0x41
55 #define ARM_CPU_IMP_APM 0x50
56 #define ARM_CPU_IMP_CAVIUM 0x43
57 #define ARM_CPU_IMP_BRCM 0x42
58 #define ARM_CPU_IMP_QCOM 0x51
59 #define ARM_CPU_IMP_NVIDIA 0x4E
60 #define ARM_CPU_IMP_FUJITSU 0x46
61 #define ARM_CPU_IMP_HISI 0x48
62 #define ARM_CPU_IMP_APPLE 0x61
63 #define ARM_CPU_IMP_AMPERE 0xC0
64
65 #define ARM_CPU_PART_AEM_V8 0xD0F
66 #define ARM_CPU_PART_FOUNDATION 0xD00
67 #define ARM_CPU_PART_CORTEX_A57 0xD07
68 #define ARM_CPU_PART_CORTEX_A72 0xD08
69 #define ARM_CPU_PART_CORTEX_A53 0xD03
70 #define ARM_CPU_PART_CORTEX_A73 0xD09
71 #define ARM_CPU_PART_CORTEX_A75 0xD0A
72 #define ARM_CPU_PART_CORTEX_A35 0xD04
73 #define ARM_CPU_PART_CORTEX_A55 0xD05
74 #define ARM_CPU_PART_CORTEX_A76 0xD0B
75 #define ARM_CPU_PART_NEOVERSE_N1 0xD0C
76 #define ARM_CPU_PART_CORTEX_A77 0xD0D
77 #define ARM_CPU_PART_NEOVERSE_V1 0xD40
78 #define ARM_CPU_PART_CORTEX_A78 0xD41
79 #define ARM_CPU_PART_CORTEX_A78AE 0xD42
80 #define ARM_CPU_PART_CORTEX_X1 0xD44
81 #define ARM_CPU_PART_CORTEX_A510 0xD46
82 #define ARM_CPU_PART_CORTEX_A710 0xD47
83 #define ARM_CPU_PART_CORTEX_A715 0xD4D
84 #define ARM_CPU_PART_CORTEX_X2 0xD48
85 #define ARM_CPU_PART_NEOVERSE_N2 0xD49
86 #define ARM_CPU_PART_CORTEX_A78C 0xD4B
87 #define ARM_CPU_PART_NEOVERSE_V2 0xD4F
88 #define ARM_CPU_PART_CORTEX_X4 0xD82
89 #define ARM_CPU_PART_NEOVERSE_V3 0xD84
90
91 #define APM_CPU_PART_POTENZA 0x000
92
93 #define CAVIUM_CPU_PART_THUNDERX 0x0A1
94 #define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2
95 #define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3
96 #define CAVIUM_CPU_PART_THUNDERX2 0x0AF
97 /* OcteonTx2 series */
98 #define CAVIUM_CPU_PART_OCTX2_98XX 0x0B1
99 #define CAVIUM_CPU_PART_OCTX2_96XX 0x0B2
100 #define CAVIUM_CPU_PART_OCTX2_95XX 0x0B3
101 #define CAVIUM_CPU_PART_OCTX2_95XXN 0x0B4
102 #define CAVIUM_CPU_PART_OCTX2_95XXMM 0x0B5
103 #define CAVIUM_CPU_PART_OCTX2_95XXO 0x0B6
104
105 #define BRCM_CPU_PART_BRAHMA_B53 0x100
106 #define BRCM_CPU_PART_VULCAN 0x516
107
108 #define QCOM_CPU_PART_FALKOR_V1 0x800
109 #define QCOM_CPU_PART_FALKOR 0xC00
110 #define QCOM_CPU_PART_KRYO 0x200
111 #define QCOM_CPU_PART_KRYO_2XX_GOLD 0x800
112 #define QCOM_CPU_PART_KRYO_2XX_SILVER 0x801
113 #define QCOM_CPU_PART_KRYO_3XX_SILVER 0x803
114 #define QCOM_CPU_PART_KRYO_4XX_GOLD 0x804
115 #define QCOM_CPU_PART_KRYO_4XX_SILVER 0x805
116
117 #define NVIDIA_CPU_PART_DENVER 0x003
118 #define NVIDIA_CPU_PART_CARMEL 0x004
119
120 #define FUJITSU_CPU_PART_A64FX 0x001
121
122 #define HISI_CPU_PART_TSV110 0xD01
123
124 #define APPLE_CPU_PART_M1_ICESTORM 0x022
125 #define APPLE_CPU_PART_M1_FIRESTORM 0x023
126 #define APPLE_CPU_PART_M1_ICESTORM_PRO 0x024
127 #define APPLE_CPU_PART_M1_FIRESTORM_PRO 0x025
128 #define APPLE_CPU_PART_M1_ICESTORM_MAX 0x028
129 #define APPLE_CPU_PART_M1_FIRESTORM_MAX 0x029
130 #define APPLE_CPU_PART_M2_BLIZZARD 0x032
131 #define APPLE_CPU_PART_M2_AVALANCHE 0x033
132 #define APPLE_CPU_PART_M2_BLIZZARD_PRO 0x034
133 #define APPLE_CPU_PART_M2_AVALANCHE_PRO 0x035
134 #define APPLE_CPU_PART_M2_BLIZZARD_MAX 0x038
135 #define APPLE_CPU_PART_M2_AVALANCHE_MAX 0x039
136
137 #define AMPERE_CPU_PART_AMPERE1 0xAC3
138
139 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
140 #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
141 #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
142 #define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)
143 #define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75)
144 #define MIDR_CORTEX_A35 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A35)
145 #define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55)
146 #define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
147 #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
148 #define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
149 #define MIDR_NEOVERSE_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V1)
150 #define MIDR_CORTEX_A78 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78)
151 #define MIDR_CORTEX_A78AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78AE)
152 #define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1)
153 #define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510)
154 #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)
155 #define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A715)
156 #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
157 #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
158 #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
159 #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)
160 #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)
161 #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
162 #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
163 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
164 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
165 #define MIDR_OCTX2_98XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_98XX)
166 #define MIDR_OCTX2_96XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_96XX)
167 #define MIDR_OCTX2_95XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XX)
168 #define MIDR_OCTX2_95XXN MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXN)
169 #define MIDR_OCTX2_95XXMM MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXMM)
170 #define MIDR_OCTX2_95XXO MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXO)
171 #define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2)
172 #define MIDR_BRAHMA_B53 MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_BRAHMA_B53)
173 #define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN)
174 #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
175 #define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)
176 #define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)
177 #define MIDR_QCOM_KRYO_2XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_GOLD)
178 #define MIDR_QCOM_KRYO_2XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_SILVER)
179 #define MIDR_QCOM_KRYO_3XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_SILVER)
180 #define MIDR_QCOM_KRYO_4XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_GOLD)
181 #define MIDR_QCOM_KRYO_4XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_SILVER)
182 #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)
183 #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
184 #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
185 #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
186 #define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
187 #define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)
188 #define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO)
189 #define MIDR_APPLE_M1_FIRESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_PRO)
190 #define MIDR_APPLE_M1_ICESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_MAX)
191 #define MIDR_APPLE_M1_FIRESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_MAX)
192 #define MIDR_APPLE_M2_BLIZZARD MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD)
193 #define MIDR_APPLE_M2_AVALANCHE MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE)
194 #define MIDR_APPLE_M2_BLIZZARD_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_PRO)
195 #define MIDR_APPLE_M2_AVALANCHE_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_PRO)
196 #define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX)
197 #define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX)
198 #define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
199
200 /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
201 #define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
202 #define MIDR_FUJITSU_ERRATUM_010001_MASK (~MIDR_CPU_VAR_REV(1, 0))
203 #define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_NFD1 | TCR_NFD0)
204
205 #ifndef __ASSEMBLY__
206
207 #include <asm/sysreg.h>
208
209 #define read_cpuid(reg) read_sysreg_s(SYS_ ## reg)
210
211 /*
212 * Represent a range of MIDR values for a given CPU model and a
213 * range of variant/revision values.
214 *
215 * @model - CPU model as defined by MIDR_CPU_MODEL
216 * @rv_min - Minimum value for the revision/variant as defined by
217 * MIDR_CPU_VAR_REV
218 * @rv_max - Maximum value for the variant/revision for the range.
219 */
220 struct midr_range {
221 u32 model;
222 u32 rv_min;
223 u32 rv_max;
224 };
225
226 #define MIDR_RANGE(m, v_min, r_min, v_max, r_max) \
227 { \
228 .model = m, \
229 .rv_min = MIDR_CPU_VAR_REV(v_min, r_min), \
230 .rv_max = MIDR_CPU_VAR_REV(v_max, r_max), \
231 }
232
233 #define MIDR_REV_RANGE(m, v, r_min, r_max) MIDR_RANGE(m, v, r_min, v, r_max)
234 #define MIDR_REV(m, v, r) MIDR_RANGE(m, v, r, v, r)
235 #define MIDR_ALL_VERSIONS(m) MIDR_RANGE(m, 0, 0, 0xf, 0xf)
236
midr_is_cpu_model_range(u32 midr,u32 model,u32 rv_min,u32 rv_max)237 static inline bool midr_is_cpu_model_range(u32 midr, u32 model, u32 rv_min,
238 u32 rv_max)
239 {
240 u32 _model = midr & MIDR_CPU_MODEL_MASK;
241 u32 rv = midr & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK);
242
243 return _model == model && rv >= rv_min && rv <= rv_max;
244 }
245
is_midr_in_range(u32 midr,struct midr_range const * range)246 static inline bool is_midr_in_range(u32 midr, struct midr_range const *range)
247 {
248 return midr_is_cpu_model_range(midr, range->model,
249 range->rv_min, range->rv_max);
250 }
251
252 static inline bool
is_midr_in_range_list(u32 midr,struct midr_range const * ranges)253 is_midr_in_range_list(u32 midr, struct midr_range const *ranges)
254 {
255 while (ranges->model)
256 if (is_midr_in_range(midr, ranges++))
257 return true;
258 return false;
259 }
260
261 /*
262 * The CPU ID never changes at run time, so we might as well tell the
263 * compiler that it's constant. Use this function to read the CPU ID
264 * rather than directly reading processor_id or read_cpuid() directly.
265 */
read_cpuid_id(void)266 static inline u32 __attribute_const__ read_cpuid_id(void)
267 {
268 return read_cpuid(MIDR_EL1);
269 }
270
read_cpuid_mpidr(void)271 static inline u64 __attribute_const__ read_cpuid_mpidr(void)
272 {
273 return read_cpuid(MPIDR_EL1);
274 }
275
read_cpuid_implementor(void)276 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
277 {
278 return MIDR_IMPLEMENTOR(read_cpuid_id());
279 }
280
read_cpuid_part_number(void)281 static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
282 {
283 return MIDR_PARTNUM(read_cpuid_id());
284 }
285
read_cpuid_cachetype(void)286 static inline u32 __attribute_const__ read_cpuid_cachetype(void)
287 {
288 return read_cpuid(CTR_EL0);
289 }
290 #endif /* __ASSEMBLY__ */
291
292 #endif
293