xref: /openbmc/linux/sound/soc/tegra/tegra210_amx.c (revision 49bd7b08)
1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // tegra210_amx.c - Tegra210 AMX driver
4 //
5 // Copyright (c) 2021-2023 NVIDIA CORPORATION.  All rights reserved.
6 
7 #include <linux/clk.h>
8 #include <linux/device.h>
9 #include <linux/io.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regmap.h>
16 #include <sound/core.h>
17 #include <sound/pcm.h>
18 #include <sound/pcm_params.h>
19 #include <sound/soc.h>
20 
21 #include "tegra210_amx.h"
22 #include "tegra_cif.h"
23 
24 /*
25  * The counter is in terms of AHUB clock cycles. If a frame is not
26  * received within these clock cycles, the AMX input channel gets
27  * automatically disabled. For now the counter is calculated as a
28  * function of sample rate (8 kHz) and AHUB clock (49.152 MHz).
29  * If later an accurate number is needed, the counter needs to be
30  * calculated at runtime.
31  *
32  *     count = ahub_clk / sample_rate
33  */
34 #define TEGRA194_MAX_FRAME_IDLE_COUNT	0x1800
35 
36 #define AMX_CH_REG(id, reg) ((reg) + ((id) * TEGRA210_AMX_AUDIOCIF_CH_STRIDE))
37 
38 static const struct reg_default tegra210_amx_reg_defaults[] = {
39 	{ TEGRA210_AMX_RX_INT_MASK, 0x0000000f},
40 	{ TEGRA210_AMX_RX1_CIF_CTRL, 0x00007000},
41 	{ TEGRA210_AMX_RX2_CIF_CTRL, 0x00007000},
42 	{ TEGRA210_AMX_RX3_CIF_CTRL, 0x00007000},
43 	{ TEGRA210_AMX_RX4_CIF_CTRL, 0x00007000},
44 	{ TEGRA210_AMX_TX_INT_MASK, 0x00000001},
45 	{ TEGRA210_AMX_TX_CIF_CTRL, 0x00007000},
46 	{ TEGRA210_AMX_CG, 0x1},
47 	{ TEGRA210_AMX_CFG_RAM_CTRL, 0x00004000},
48 };
49 
tegra210_amx_write_map_ram(struct tegra210_amx * amx)50 static void tegra210_amx_write_map_ram(struct tegra210_amx *amx)
51 {
52 	int i;
53 
54 	regmap_write(amx->regmap, TEGRA210_AMX_CFG_RAM_CTRL,
55 		     TEGRA210_AMX_CFG_RAM_CTRL_SEQ_ACCESS_EN |
56 		     TEGRA210_AMX_CFG_RAM_CTRL_ADDR_INIT_EN |
57 		     TEGRA210_AMX_CFG_RAM_CTRL_RW_WRITE);
58 
59 	for (i = 0; i < TEGRA210_AMX_RAM_DEPTH; i++)
60 		regmap_write(amx->regmap, TEGRA210_AMX_CFG_RAM_DATA,
61 			     amx->map[i]);
62 
63 	regmap_write(amx->regmap, TEGRA210_AMX_OUT_BYTE_EN0, amx->byte_mask[0]);
64 	regmap_write(amx->regmap, TEGRA210_AMX_OUT_BYTE_EN1, amx->byte_mask[1]);
65 }
66 
tegra210_amx_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)67 static int tegra210_amx_startup(struct snd_pcm_substream *substream,
68 				struct snd_soc_dai *dai)
69 {
70 	struct tegra210_amx *amx = snd_soc_dai_get_drvdata(dai);
71 	unsigned int val;
72 	int err;
73 
74 	/* Ensure if AMX is disabled */
75 	err = regmap_read_poll_timeout(amx->regmap, TEGRA210_AMX_STATUS, val,
76 				       !(val & 0x1), 10, 10000);
77 	if (err < 0) {
78 		dev_err(dai->dev, "failed to stop AMX, err = %d\n", err);
79 		return err;
80 	}
81 
82 	/*
83 	 * Soft Reset: Below performs module soft reset which clears
84 	 * all FSM logic, flushes flow control of FIFO and resets the
85 	 * state register. It also brings module back to disabled
86 	 * state (without flushing the data in the pipe).
87 	 */
88 	regmap_update_bits(amx->regmap, TEGRA210_AMX_SOFT_RESET,
89 			   TEGRA210_AMX_SOFT_RESET_SOFT_RESET_MASK,
90 			   TEGRA210_AMX_SOFT_RESET_SOFT_EN);
91 
92 	err = regmap_read_poll_timeout(amx->regmap, TEGRA210_AMX_SOFT_RESET,
93 				       val, !(val & 0x1), 10, 10000);
94 	if (err < 0) {
95 		dev_err(dai->dev, "failed to reset AMX, err = %d\n", err);
96 		return err;
97 	}
98 
99 	return 0;
100 }
101 
tegra210_amx_runtime_suspend(struct device * dev)102 static int __maybe_unused tegra210_amx_runtime_suspend(struct device *dev)
103 {
104 	struct tegra210_amx *amx = dev_get_drvdata(dev);
105 
106 	regcache_cache_only(amx->regmap, true);
107 	regcache_mark_dirty(amx->regmap);
108 
109 	return 0;
110 }
111 
tegra210_amx_runtime_resume(struct device * dev)112 static int __maybe_unused tegra210_amx_runtime_resume(struct device *dev)
113 {
114 	struct tegra210_amx *amx = dev_get_drvdata(dev);
115 
116 	regcache_cache_only(amx->regmap, false);
117 	regcache_sync(amx->regmap);
118 
119 	regmap_update_bits(amx->regmap,
120 		TEGRA210_AMX_CTRL,
121 		TEGRA210_AMX_CTRL_RX_DEP_MASK,
122 		TEGRA210_AMX_WAIT_ON_ANY << TEGRA210_AMX_CTRL_RX_DEP_SHIFT);
123 
124 	tegra210_amx_write_map_ram(amx);
125 
126 	return 0;
127 }
128 
tegra210_amx_set_audio_cif(struct snd_soc_dai * dai,struct snd_pcm_hw_params * params,unsigned int reg)129 static int tegra210_amx_set_audio_cif(struct snd_soc_dai *dai,
130 				      struct snd_pcm_hw_params *params,
131 				      unsigned int reg)
132 {
133 	struct tegra210_amx *amx = snd_soc_dai_get_drvdata(dai);
134 	int channels, audio_bits;
135 	struct tegra_cif_conf cif_conf;
136 
137 	memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
138 
139 	channels = params_channels(params);
140 
141 	switch (params_format(params)) {
142 	case SNDRV_PCM_FORMAT_S8:
143 		audio_bits = TEGRA_ACIF_BITS_8;
144 		break;
145 	case SNDRV_PCM_FORMAT_S16_LE:
146 		audio_bits = TEGRA_ACIF_BITS_16;
147 		break;
148 	case SNDRV_PCM_FORMAT_S32_LE:
149 		audio_bits = TEGRA_ACIF_BITS_32;
150 		break;
151 	default:
152 		return -EINVAL;
153 	}
154 
155 	cif_conf.audio_ch = channels;
156 	cif_conf.client_ch = channels;
157 	cif_conf.audio_bits = audio_bits;
158 	cif_conf.client_bits = audio_bits;
159 
160 	tegra_set_cif(amx->regmap, reg, &cif_conf);
161 
162 	return 0;
163 }
164 
tegra210_amx_in_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)165 static int tegra210_amx_in_hw_params(struct snd_pcm_substream *substream,
166 				     struct snd_pcm_hw_params *params,
167 				     struct snd_soc_dai *dai)
168 {
169 	struct tegra210_amx *amx = snd_soc_dai_get_drvdata(dai);
170 
171 	if (amx->soc_data->auto_disable) {
172 		regmap_write(amx->regmap,
173 			     AMX_CH_REG(dai->id, TEGRA194_AMX_RX1_FRAME_PERIOD),
174 			     TEGRA194_MAX_FRAME_IDLE_COUNT);
175 		regmap_write(amx->regmap, TEGRA210_AMX_CYA, 1);
176 	}
177 
178 	return tegra210_amx_set_audio_cif(dai, params,
179 			AMX_CH_REG(dai->id, TEGRA210_AMX_RX1_CIF_CTRL));
180 }
181 
tegra210_amx_out_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)182 static int tegra210_amx_out_hw_params(struct snd_pcm_substream *substream,
183 				      struct snd_pcm_hw_params *params,
184 				      struct snd_soc_dai *dai)
185 {
186 	return tegra210_amx_set_audio_cif(dai, params,
187 					  TEGRA210_AMX_TX_CIF_CTRL);
188 }
189 
tegra210_amx_get_byte_map(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)190 static int tegra210_amx_get_byte_map(struct snd_kcontrol *kcontrol,
191 				     struct snd_ctl_elem_value *ucontrol)
192 {
193 	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
194 	struct soc_mixer_control *mc =
195 		(struct soc_mixer_control *)kcontrol->private_value;
196 	struct tegra210_amx *amx = snd_soc_component_get_drvdata(cmpnt);
197 	unsigned char *bytes_map = (unsigned char *)&amx->map;
198 	int reg = mc->reg;
199 	int enabled;
200 
201 	if (reg > 31)
202 		enabled = amx->byte_mask[1] & (1 << (reg - 32));
203 	else
204 		enabled = amx->byte_mask[0] & (1 << reg);
205 
206 	/*
207 	 * TODO: Simplify this logic to just return from bytes_map[]
208 	 *
209 	 * Presently below is required since bytes_map[] is
210 	 * tightly packed and cannot store the control value of 256.
211 	 * Byte mask state is used to know if 256 needs to be returned.
212 	 * Note that for control value of 256, the put() call stores 0
213 	 * in the bytes_map[] and disables the corresponding bit in
214 	 * byte_mask[].
215 	 */
216 	if (enabled)
217 		ucontrol->value.integer.value[0] = bytes_map[reg];
218 	else
219 		ucontrol->value.integer.value[0] = 256;
220 
221 	return 0;
222 }
223 
tegra210_amx_put_byte_map(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)224 static int tegra210_amx_put_byte_map(struct snd_kcontrol *kcontrol,
225 				     struct snd_ctl_elem_value *ucontrol)
226 {
227 	struct soc_mixer_control *mc =
228 		(struct soc_mixer_control *)kcontrol->private_value;
229 	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
230 	struct tegra210_amx *amx = snd_soc_component_get_drvdata(cmpnt);
231 	unsigned char *bytes_map = (unsigned char *)&amx->map;
232 	int reg = mc->reg;
233 	int value = ucontrol->value.integer.value[0];
234 	unsigned int mask_val = amx->byte_mask[reg / 32];
235 
236 	if (value >= 0 && value <= 255)
237 		mask_val |= (1 << (reg % 32));
238 	else
239 		mask_val &= ~(1 << (reg % 32));
240 
241 	if (mask_val == amx->byte_mask[reg / 32])
242 		return 0;
243 
244 	/* Update byte map and slot */
245 	bytes_map[reg] = value % 256;
246 	amx->byte_mask[reg / 32] = mask_val;
247 
248 	return 1;
249 }
250 
251 static const struct snd_soc_dai_ops tegra210_amx_out_dai_ops = {
252 	.hw_params	= tegra210_amx_out_hw_params,
253 	.startup	= tegra210_amx_startup,
254 };
255 
256 static const struct snd_soc_dai_ops tegra210_amx_in_dai_ops = {
257 	.hw_params	= tegra210_amx_in_hw_params,
258 };
259 
260 #define IN_DAI(id)						\
261 	{							\
262 		.name = "AMX-RX-CIF" #id,			\
263 		.playback = {					\
264 			.stream_name = "RX" #id "-CIF-Playback",\
265 			.channels_min = 1,			\
266 			.channels_max = 16,			\
267 			.rates = SNDRV_PCM_RATE_8000_192000,	\
268 			.formats = SNDRV_PCM_FMTBIT_S8 |	\
269 				   SNDRV_PCM_FMTBIT_S16_LE |	\
270 				   SNDRV_PCM_FMTBIT_S32_LE,	\
271 		},						\
272 		.capture = {					\
273 			.stream_name = "RX" #id "-CIF-Capture",	\
274 			.channels_min = 1,			\
275 			.channels_max = 16,			\
276 			.rates = SNDRV_PCM_RATE_8000_192000,	\
277 			.formats = SNDRV_PCM_FMTBIT_S8 |	\
278 				   SNDRV_PCM_FMTBIT_S16_LE |	\
279 				   SNDRV_PCM_FMTBIT_S32_LE,	\
280 		},						\
281 		.ops = &tegra210_amx_in_dai_ops,		\
282 	}
283 
284 #define OUT_DAI							\
285 	{							\
286 		.name = "AMX-TX-CIF",				\
287 		.playback = {					\
288 			.stream_name = "TX-CIF-Playback",	\
289 			.channels_min = 1,			\
290 			.channels_max = 16,			\
291 			.rates = SNDRV_PCM_RATE_8000_192000,	\
292 			.formats = SNDRV_PCM_FMTBIT_S8 |	\
293 				   SNDRV_PCM_FMTBIT_S16_LE |	\
294 				   SNDRV_PCM_FMTBIT_S32_LE,	\
295 		},						\
296 		.capture = {					\
297 			.stream_name = "TX-CIF-Capture",	\
298 			.channels_min = 1,			\
299 			.channels_max = 16,			\
300 			.rates = SNDRV_PCM_RATE_8000_192000,	\
301 			.formats = SNDRV_PCM_FMTBIT_S8 |	\
302 				   SNDRV_PCM_FMTBIT_S16_LE |	\
303 				   SNDRV_PCM_FMTBIT_S32_LE,	\
304 		},						\
305 		.ops = &tegra210_amx_out_dai_ops,		\
306 	}
307 
308 static struct snd_soc_dai_driver tegra210_amx_dais[] = {
309 	IN_DAI(1),
310 	IN_DAI(2),
311 	IN_DAI(3),
312 	IN_DAI(4),
313 	OUT_DAI,
314 };
315 
316 static const struct snd_soc_dapm_widget tegra210_amx_widgets[] = {
317 	SND_SOC_DAPM_AIF_IN("RX1", NULL, 0, TEGRA210_AMX_CTRL, 0, 0),
318 	SND_SOC_DAPM_AIF_IN("RX2", NULL, 0, TEGRA210_AMX_CTRL, 1, 0),
319 	SND_SOC_DAPM_AIF_IN("RX3", NULL, 0, TEGRA210_AMX_CTRL, 2, 0),
320 	SND_SOC_DAPM_AIF_IN("RX4", NULL, 0, TEGRA210_AMX_CTRL, 3, 0),
321 	SND_SOC_DAPM_AIF_OUT("TX", NULL, 0, TEGRA210_AMX_ENABLE,
322 			     TEGRA210_AMX_ENABLE_SHIFT, 0),
323 };
324 
325 #define STREAM_ROUTES(id, sname)					  \
326 	{ "RX" #id " XBAR-" sname,	NULL,	"RX" #id " XBAR-TX" },	  \
327 	{ "RX" #id "-CIF-" sname,	NULL,	"RX" #id " XBAR-" sname },\
328 	{ "RX" #id,			NULL,	"RX" #id "-CIF-" sname }, \
329 	{ "TX",				NULL,	"RX" #id },		  \
330 	{ "TX-CIF-" sname,		NULL,	"TX" },			  \
331 	{ "XBAR-" sname,		NULL,	"TX-CIF-" sname },	  \
332 	{ "XBAR-RX",			NULL,	"XBAR-" sname }
333 
334 #define AMX_ROUTES(id)			\
335 	STREAM_ROUTES(id, "Playback"),	\
336 	STREAM_ROUTES(id, "Capture")
337 
338 static const struct snd_soc_dapm_route tegra210_amx_routes[] = {
339 	AMX_ROUTES(1),
340 	AMX_ROUTES(2),
341 	AMX_ROUTES(3),
342 	AMX_ROUTES(4),
343 };
344 
345 #define TEGRA210_AMX_BYTE_MAP_CTRL(reg)					\
346 	SOC_SINGLE_EXT("Byte Map " #reg, reg, 0, 256, 0,		\
347 		       tegra210_amx_get_byte_map,			\
348 		       tegra210_amx_put_byte_map)
349 
350 static struct snd_kcontrol_new tegra210_amx_controls[] = {
351 	TEGRA210_AMX_BYTE_MAP_CTRL(0),
352 	TEGRA210_AMX_BYTE_MAP_CTRL(1),
353 	TEGRA210_AMX_BYTE_MAP_CTRL(2),
354 	TEGRA210_AMX_BYTE_MAP_CTRL(3),
355 	TEGRA210_AMX_BYTE_MAP_CTRL(4),
356 	TEGRA210_AMX_BYTE_MAP_CTRL(5),
357 	TEGRA210_AMX_BYTE_MAP_CTRL(6),
358 	TEGRA210_AMX_BYTE_MAP_CTRL(7),
359 	TEGRA210_AMX_BYTE_MAP_CTRL(8),
360 	TEGRA210_AMX_BYTE_MAP_CTRL(9),
361 	TEGRA210_AMX_BYTE_MAP_CTRL(10),
362 	TEGRA210_AMX_BYTE_MAP_CTRL(11),
363 	TEGRA210_AMX_BYTE_MAP_CTRL(12),
364 	TEGRA210_AMX_BYTE_MAP_CTRL(13),
365 	TEGRA210_AMX_BYTE_MAP_CTRL(14),
366 	TEGRA210_AMX_BYTE_MAP_CTRL(15),
367 	TEGRA210_AMX_BYTE_MAP_CTRL(16),
368 	TEGRA210_AMX_BYTE_MAP_CTRL(17),
369 	TEGRA210_AMX_BYTE_MAP_CTRL(18),
370 	TEGRA210_AMX_BYTE_MAP_CTRL(19),
371 	TEGRA210_AMX_BYTE_MAP_CTRL(20),
372 	TEGRA210_AMX_BYTE_MAP_CTRL(21),
373 	TEGRA210_AMX_BYTE_MAP_CTRL(22),
374 	TEGRA210_AMX_BYTE_MAP_CTRL(23),
375 	TEGRA210_AMX_BYTE_MAP_CTRL(24),
376 	TEGRA210_AMX_BYTE_MAP_CTRL(25),
377 	TEGRA210_AMX_BYTE_MAP_CTRL(26),
378 	TEGRA210_AMX_BYTE_MAP_CTRL(27),
379 	TEGRA210_AMX_BYTE_MAP_CTRL(28),
380 	TEGRA210_AMX_BYTE_MAP_CTRL(29),
381 	TEGRA210_AMX_BYTE_MAP_CTRL(30),
382 	TEGRA210_AMX_BYTE_MAP_CTRL(31),
383 	TEGRA210_AMX_BYTE_MAP_CTRL(32),
384 	TEGRA210_AMX_BYTE_MAP_CTRL(33),
385 	TEGRA210_AMX_BYTE_MAP_CTRL(34),
386 	TEGRA210_AMX_BYTE_MAP_CTRL(35),
387 	TEGRA210_AMX_BYTE_MAP_CTRL(36),
388 	TEGRA210_AMX_BYTE_MAP_CTRL(37),
389 	TEGRA210_AMX_BYTE_MAP_CTRL(38),
390 	TEGRA210_AMX_BYTE_MAP_CTRL(39),
391 	TEGRA210_AMX_BYTE_MAP_CTRL(40),
392 	TEGRA210_AMX_BYTE_MAP_CTRL(41),
393 	TEGRA210_AMX_BYTE_MAP_CTRL(42),
394 	TEGRA210_AMX_BYTE_MAP_CTRL(43),
395 	TEGRA210_AMX_BYTE_MAP_CTRL(44),
396 	TEGRA210_AMX_BYTE_MAP_CTRL(45),
397 	TEGRA210_AMX_BYTE_MAP_CTRL(46),
398 	TEGRA210_AMX_BYTE_MAP_CTRL(47),
399 	TEGRA210_AMX_BYTE_MAP_CTRL(48),
400 	TEGRA210_AMX_BYTE_MAP_CTRL(49),
401 	TEGRA210_AMX_BYTE_MAP_CTRL(50),
402 	TEGRA210_AMX_BYTE_MAP_CTRL(51),
403 	TEGRA210_AMX_BYTE_MAP_CTRL(52),
404 	TEGRA210_AMX_BYTE_MAP_CTRL(53),
405 	TEGRA210_AMX_BYTE_MAP_CTRL(54),
406 	TEGRA210_AMX_BYTE_MAP_CTRL(55),
407 	TEGRA210_AMX_BYTE_MAP_CTRL(56),
408 	TEGRA210_AMX_BYTE_MAP_CTRL(57),
409 	TEGRA210_AMX_BYTE_MAP_CTRL(58),
410 	TEGRA210_AMX_BYTE_MAP_CTRL(59),
411 	TEGRA210_AMX_BYTE_MAP_CTRL(60),
412 	TEGRA210_AMX_BYTE_MAP_CTRL(61),
413 	TEGRA210_AMX_BYTE_MAP_CTRL(62),
414 	TEGRA210_AMX_BYTE_MAP_CTRL(63),
415 };
416 
417 static const struct snd_soc_component_driver tegra210_amx_cmpnt = {
418 	.dapm_widgets		= tegra210_amx_widgets,
419 	.num_dapm_widgets	= ARRAY_SIZE(tegra210_amx_widgets),
420 	.dapm_routes		= tegra210_amx_routes,
421 	.num_dapm_routes	= ARRAY_SIZE(tegra210_amx_routes),
422 	.controls		= tegra210_amx_controls,
423 	.num_controls		= ARRAY_SIZE(tegra210_amx_controls),
424 };
425 
tegra210_amx_wr_reg(struct device * dev,unsigned int reg)426 static bool tegra210_amx_wr_reg(struct device *dev, unsigned int reg)
427 {
428 	switch (reg) {
429 	case TEGRA210_AMX_RX_INT_MASK ... TEGRA210_AMX_RX4_CIF_CTRL:
430 	case TEGRA210_AMX_TX_INT_MASK ... TEGRA210_AMX_CG:
431 	case TEGRA210_AMX_CTRL ... TEGRA210_AMX_CYA:
432 	case TEGRA210_AMX_CFG_RAM_CTRL ... TEGRA210_AMX_CFG_RAM_DATA:
433 		return true;
434 	default:
435 		return false;
436 	}
437 }
438 
tegra194_amx_wr_reg(struct device * dev,unsigned int reg)439 static bool tegra194_amx_wr_reg(struct device *dev, unsigned int reg)
440 {
441 	switch (reg) {
442 	case TEGRA194_AMX_RX1_FRAME_PERIOD ... TEGRA194_AMX_RX4_FRAME_PERIOD:
443 		return true;
444 	default:
445 		return tegra210_amx_wr_reg(dev, reg);
446 	}
447 }
448 
tegra210_amx_rd_reg(struct device * dev,unsigned int reg)449 static bool tegra210_amx_rd_reg(struct device *dev, unsigned int reg)
450 {
451 	switch (reg) {
452 	case TEGRA210_AMX_RX_STATUS ... TEGRA210_AMX_CFG_RAM_DATA:
453 		return true;
454 	default:
455 		return false;
456 	}
457 }
458 
tegra194_amx_rd_reg(struct device * dev,unsigned int reg)459 static bool tegra194_amx_rd_reg(struct device *dev, unsigned int reg)
460 {
461 	switch (reg) {
462 	case TEGRA194_AMX_RX1_FRAME_PERIOD ... TEGRA194_AMX_RX4_FRAME_PERIOD:
463 		return true;
464 	default:
465 		return tegra210_amx_rd_reg(dev, reg);
466 	}
467 }
468 
tegra210_amx_volatile_reg(struct device * dev,unsigned int reg)469 static bool tegra210_amx_volatile_reg(struct device *dev, unsigned int reg)
470 {
471 	switch (reg) {
472 	case TEGRA210_AMX_RX_STATUS:
473 	case TEGRA210_AMX_RX_INT_STATUS:
474 	case TEGRA210_AMX_RX_INT_SET:
475 	case TEGRA210_AMX_TX_STATUS:
476 	case TEGRA210_AMX_TX_INT_STATUS:
477 	case TEGRA210_AMX_TX_INT_SET:
478 	case TEGRA210_AMX_SOFT_RESET:
479 	case TEGRA210_AMX_STATUS:
480 	case TEGRA210_AMX_INT_STATUS:
481 	case TEGRA210_AMX_CFG_RAM_CTRL:
482 	case TEGRA210_AMX_CFG_RAM_DATA:
483 		return true;
484 	default:
485 		break;
486 	}
487 
488 	return false;
489 }
490 
491 static const struct regmap_config tegra210_amx_regmap_config = {
492 	.reg_bits		= 32,
493 	.reg_stride		= 4,
494 	.val_bits		= 32,
495 	.max_register		= TEGRA210_AMX_CFG_RAM_DATA,
496 	.writeable_reg		= tegra210_amx_wr_reg,
497 	.readable_reg		= tegra210_amx_rd_reg,
498 	.volatile_reg		= tegra210_amx_volatile_reg,
499 	.reg_defaults		= tegra210_amx_reg_defaults,
500 	.num_reg_defaults	= ARRAY_SIZE(tegra210_amx_reg_defaults),
501 	.cache_type		= REGCACHE_FLAT,
502 };
503 
504 static const struct regmap_config tegra194_amx_regmap_config = {
505 	.reg_bits		= 32,
506 	.reg_stride		= 4,
507 	.val_bits		= 32,
508 	.max_register		= TEGRA194_AMX_RX4_LAST_FRAME_PERIOD,
509 	.writeable_reg		= tegra194_amx_wr_reg,
510 	.readable_reg		= tegra194_amx_rd_reg,
511 	.volatile_reg		= tegra210_amx_volatile_reg,
512 	.reg_defaults		= tegra210_amx_reg_defaults,
513 	.num_reg_defaults	= ARRAY_SIZE(tegra210_amx_reg_defaults),
514 	.cache_type		= REGCACHE_FLAT,
515 };
516 
517 static const struct tegra210_amx_soc_data soc_data_tegra210 = {
518 	.regmap_conf	= &tegra210_amx_regmap_config,
519 };
520 
521 static const struct tegra210_amx_soc_data soc_data_tegra194 = {
522 	.regmap_conf	= &tegra194_amx_regmap_config,
523 	.auto_disable	= true,
524 };
525 
526 static const struct of_device_id tegra210_amx_of_match[] = {
527 	{ .compatible = "nvidia,tegra210-amx", .data = &soc_data_tegra210 },
528 	{ .compatible = "nvidia,tegra194-amx", .data = &soc_data_tegra194 },
529 	{},
530 };
531 MODULE_DEVICE_TABLE(of, tegra210_amx_of_match);
532 
tegra210_amx_platform_probe(struct platform_device * pdev)533 static int tegra210_amx_platform_probe(struct platform_device *pdev)
534 {
535 	struct device *dev = &pdev->dev;
536 	struct tegra210_amx *amx;
537 	void __iomem *regs;
538 	int err;
539 	const struct of_device_id *match;
540 	struct tegra210_amx_soc_data *soc_data;
541 
542 	match = of_match_device(tegra210_amx_of_match, dev);
543 
544 	soc_data = (struct tegra210_amx_soc_data *)match->data;
545 
546 	amx = devm_kzalloc(dev, sizeof(*amx), GFP_KERNEL);
547 	if (!amx)
548 		return -ENOMEM;
549 
550 	amx->soc_data = soc_data;
551 
552 	dev_set_drvdata(dev, amx);
553 
554 	regs = devm_platform_ioremap_resource(pdev, 0);
555 	if (IS_ERR(regs))
556 		return PTR_ERR(regs);
557 
558 	amx->regmap = devm_regmap_init_mmio(dev, regs,
559 					    soc_data->regmap_conf);
560 	if (IS_ERR(amx->regmap)) {
561 		dev_err(dev, "regmap init failed\n");
562 		return PTR_ERR(amx->regmap);
563 	}
564 
565 	regcache_cache_only(amx->regmap, true);
566 
567 	err = devm_snd_soc_register_component(dev, &tegra210_amx_cmpnt,
568 					      tegra210_amx_dais,
569 					      ARRAY_SIZE(tegra210_amx_dais));
570 	if (err) {
571 		dev_err(dev, "can't register AMX component, err: %d\n", err);
572 		return err;
573 	}
574 
575 	pm_runtime_enable(dev);
576 
577 	return 0;
578 }
579 
tegra210_amx_platform_remove(struct platform_device * pdev)580 static void tegra210_amx_platform_remove(struct platform_device *pdev)
581 {
582 	pm_runtime_disable(&pdev->dev);
583 }
584 
585 static const struct dev_pm_ops tegra210_amx_pm_ops = {
586 	SET_RUNTIME_PM_OPS(tegra210_amx_runtime_suspend,
587 			   tegra210_amx_runtime_resume, NULL)
588 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
589 				pm_runtime_force_resume)
590 };
591 
592 static struct platform_driver tegra210_amx_driver = {
593 	.driver = {
594 		.name = "tegra210-amx",
595 		.of_match_table = tegra210_amx_of_match,
596 		.pm = &tegra210_amx_pm_ops,
597 	},
598 	.probe = tegra210_amx_platform_probe,
599 	.remove_new = tegra210_amx_platform_remove,
600 };
601 module_platform_driver(tegra210_amx_driver);
602 
603 MODULE_AUTHOR("Songhee Baek <sbaek@nvidia.com>");
604 MODULE_DESCRIPTION("Tegra210 AMX ASoC driver");
605 MODULE_LICENSE("GPL v2");
606