1 /* 2 * QEMU emulation of an AMD IOMMU (AMD-Vi) 3 * 4 * Copyright (C) 2011 Eduard - Gabriel Munteanu 5 * Copyright (C) 2015, 2016 David Kiarie Kahurani 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef AMD_IOMMU_H 22 #define AMD_IOMMU_H 23 24 #include "hw/pci/pci.h" 25 #include "hw/i386/x86-iommu.h" 26 #include "qom/object.h" 27 28 #define GENMASK64(h, l) (((~0ULL) >> (63 - (h) + (l))) << (l)) 29 30 /* Capability registers */ 31 #define AMDVI_CAPAB_BAR_LOW 0x04 32 #define AMDVI_CAPAB_BAR_HIGH 0x08 33 #define AMDVI_CAPAB_RANGE 0x0C 34 #define AMDVI_CAPAB_MISC 0x10 35 36 #define AMDVI_CAPAB_SIZE 0x18 37 #define AMDVI_CAPAB_REG_SIZE 0x04 38 39 /* Capability header data */ 40 #define AMDVI_CAPAB_ID_SEC 0xf 41 #define AMDVI_CAPAB_FLAT_EXT (1 << 28) 42 #define AMDVI_CAPAB_EFR_SUP (1 << 27) 43 #define AMDVI_CAPAB_FLAG_NPCACHE (1 << 26) 44 #define AMDVI_CAPAB_FLAG_HTTUNNEL (1 << 25) 45 #define AMDVI_CAPAB_FLAG_IOTLBSUP (1 << 24) 46 #define AMDVI_CAPAB_INIT_TYPE (3 << 16) 47 48 /* No. of used MMIO registers */ 49 #define AMDVI_MMIO_REGS_HIGH 7 50 #define AMDVI_MMIO_REGS_LOW 8 51 52 /* MMIO registers */ 53 #define AMDVI_MMIO_DEVICE_TABLE 0x0000 54 #define AMDVI_MMIO_COMMAND_BASE 0x0008 55 #define AMDVI_MMIO_EVENT_BASE 0x0010 56 #define AMDVI_MMIO_CONTROL 0x0018 57 #define AMDVI_MMIO_EXCL_BASE 0x0020 58 #define AMDVI_MMIO_EXCL_LIMIT 0x0028 59 #define AMDVI_MMIO_EXT_FEATURES 0x0030 60 #define AMDVI_MMIO_COMMAND_HEAD 0x2000 61 #define AMDVI_MMIO_COMMAND_TAIL 0x2008 62 #define AMDVI_MMIO_EVENT_HEAD 0x2010 63 #define AMDVI_MMIO_EVENT_TAIL 0x2018 64 #define AMDVI_MMIO_STATUS 0x2020 65 #define AMDVI_MMIO_PPR_BASE 0x0038 66 #define AMDVI_MMIO_PPR_HEAD 0x2030 67 #define AMDVI_MMIO_PPR_TAIL 0x2038 68 69 #define AMDVI_MMIO_SIZE 0x4000 70 71 #define AMDVI_MMIO_DEVTAB_SIZE_MASK GENMASK64(8, 0) 72 #define AMDVI_MMIO_DEVTAB_BASE_MASK GENMASK64(51, 12) 73 74 #define AMDVI_MMIO_DEVTAB_ENTRY_SIZE 32 75 #define AMDVI_MMIO_DEVTAB_SIZE_UNIT 4096 76 77 /* some of this are similar but just for readability */ 78 #define AMDVI_MMIO_CMDBUF_SIZE_BYTE (AMDVI_MMIO_COMMAND_BASE + 7) 79 #define AMDVI_MMIO_CMDBUF_SIZE_MASK 0x0f 80 #define AMDVI_MMIO_CMDBUF_BASE_MASK GENMASK64(51, 12) 81 #define AMDVI_MMIO_CMDBUF_HEAD_MASK GENMASK64(18, 4) 82 #define AMDVI_MMIO_CMDBUF_TAIL_MASK GENMASK64(18, 4) 83 84 #define AMDVI_MMIO_EVTLOG_SIZE_BYTE (AMDVI_MMIO_EVENT_BASE + 7) 85 #define AMDVI_MMIO_EVTLOG_SIZE_MASK 0x0f 86 #define AMDVI_MMIO_EVTLOG_BASE_MASK GENMASK64(51, 12) 87 #define AMDVI_MMIO_EVTLOG_HEAD_MASK GENMASK64(18, 4) 88 #define AMDVI_MMIO_EVTLOG_TAIL_MASK GENMASK64(18, 4) 89 90 #define AMDVI_MMIO_PPRLOG_SIZE_BYTE (AMDVI_MMIO_PPR_BASE + 7) 91 #define AMDVI_MMIO_PPRLOG_SIZE_MASK 0x0f 92 #define AMDVI_MMIO_PPRLOG_BASE_MASK GENMASK64(51, 12) 93 #define AMDVI_MMIO_PPRLOG_HEAD_MASK GENMASK64(18, 4) 94 #define AMDVI_MMIO_PPRLOG_TAIL_MASK GENMASK64(18, 4) 95 96 #define AMDVI_MMIO_EXCL_ENABLED_MASK (1ULL << 0) 97 #define AMDVI_MMIO_EXCL_ALLOW_MASK (1ULL << 1) 98 #define AMDVI_MMIO_EXCL_LIMIT_MASK GENMASK64(51, 12) 99 #define AMDVI_MMIO_EXCL_LIMIT_LOW 0xfff 100 101 /* mmio control register flags */ 102 #define AMDVI_MMIO_CONTROL_AMDVIEN (1ULL << 0) 103 #define AMDVI_MMIO_CONTROL_HTTUNEN (1ULL << 1) 104 #define AMDVI_MMIO_CONTROL_EVENTLOGEN (1ULL << 2) 105 #define AMDVI_MMIO_CONTROL_EVENTINTEN (1ULL << 3) 106 #define AMDVI_MMIO_CONTROL_COMWAITINTEN (1ULL << 4) 107 #define AMDVI_MMIO_CONTROL_CMDBUFLEN (1ULL << 12) 108 #define AMDVI_MMIO_CONTROL_GAEN (1ULL << 17) 109 110 /* MMIO status register bits */ 111 #define AMDVI_MMIO_STATUS_CMDBUF_RUN (1 << 4) 112 #define AMDVI_MMIO_STATUS_EVT_RUN (1 << 3) 113 #define AMDVI_MMIO_STATUS_COMP_INT (1 << 2) 114 #define AMDVI_MMIO_STATUS_EVT_OVF (1 << 0) 115 116 #define AMDVI_CMDBUF_ID_BYTE 0x07 117 #define AMDVI_CMDBUF_ID_RSHIFT 4 118 119 #define AMDVI_CMD_COMPLETION_WAIT 0x01 120 #define AMDVI_CMD_INVAL_DEVTAB_ENTRY 0x02 121 #define AMDVI_CMD_INVAL_AMDVI_PAGES 0x03 122 #define AMDVI_CMD_INVAL_IOTLB_PAGES 0x04 123 #define AMDVI_CMD_INVAL_INTR_TABLE 0x05 124 #define AMDVI_CMD_PREFETCH_AMDVI_PAGES 0x06 125 #define AMDVI_CMD_COMPLETE_PPR_REQUEST 0x07 126 #define AMDVI_CMD_INVAL_AMDVI_ALL 0x08 127 128 #define AMDVI_DEVTAB_ENTRY_SIZE 32 129 130 /* Device table entry bits 0:63 */ 131 #define AMDVI_DEV_VALID (1ULL << 0) 132 #define AMDVI_DEV_TRANSLATION_VALID (1ULL << 1) 133 #define AMDVI_DEV_MODE_MASK 0x7 134 #define AMDVI_DEV_MODE_RSHIFT 9 135 #define AMDVI_DEV_PT_ROOT_MASK GENMASK64(51, 12) 136 #define AMDVI_DEV_PT_ROOT_RSHIFT 12 137 #define AMDVI_DEV_PERM_SHIFT 61 138 #define AMDVI_DEV_PERM_READ (1ULL << 61) 139 #define AMDVI_DEV_PERM_WRITE (1ULL << 62) 140 141 /* Device table entry bits 64:127 */ 142 #define AMDVI_DEV_DOMID_ID_MASK GENMASK64(15, 0) 143 144 /* Event codes and flags, as stored in the info field */ 145 #define AMDVI_EVENT_ILLEGAL_DEVTAB_ENTRY (0x1U << 12) 146 #define AMDVI_EVENT_IOPF (0x2U << 12) 147 #define AMDVI_EVENT_IOPF_I (1U << 3) 148 #define AMDVI_EVENT_DEV_TAB_HW_ERROR (0x3U << 12) 149 #define AMDVI_EVENT_PAGE_TAB_HW_ERROR (0x4U << 12) 150 #define AMDVI_EVENT_ILLEGAL_COMMAND_ERROR (0x5U << 12) 151 #define AMDVI_EVENT_COMMAND_HW_ERROR (0x6U << 12) 152 153 #define AMDVI_EVENT_LEN 16 154 #define AMDVI_PERM_READ (1 << 0) 155 #define AMDVI_PERM_WRITE (1 << 1) 156 157 #define AMDVI_FEATURE_PREFETCH (1ULL << 0) /* page prefetch */ 158 #define AMDVI_FEATURE_PPR (1ULL << 1) /* PPR Support */ 159 #define AMDVI_FEATURE_XT (1ULL << 2) /* x2APIC Support */ 160 #define AMDVI_FEATURE_GT (1ULL << 4) /* Guest Translation */ 161 #define AMDVI_FEATURE_IA (1ULL << 6) /* inval all support */ 162 #define AMDVI_FEATURE_GA (1ULL << 7) /* guest VAPIC support */ 163 #define AMDVI_FEATURE_HE (1ULL << 8) /* hardware error regs */ 164 #define AMDVI_FEATURE_PC (1ULL << 9) /* Perf counters */ 165 166 /* reserved DTE bits */ 167 #define AMDVI_DTE_QUAD0_RESERVED (GENMASK64(6, 2) | GENMASK64(63, 63)) 168 #define AMDVI_DTE_QUAD1_RESERVED 0 169 #define AMDVI_DTE_QUAD2_RESERVED GENMASK64(53, 52) 170 #define AMDVI_DTE_QUAD3_RESERVED (GENMASK64(14, 0) | GENMASK64(53, 48)) 171 172 /* AMDVI paging mode */ 173 #define AMDVI_GATS_MODE (2ULL << 12) 174 #define AMDVI_HATS_MODE (2ULL << 10) 175 176 /* IOTLB */ 177 #define AMDVI_IOTLB_MAX_SIZE 1024 178 #define AMDVI_DEVID_SHIFT 36 179 180 /* default extended feature */ 181 #define AMDVI_DEFAULT_EXT_FEATURES \ 182 (AMDVI_FEATURE_PREFETCH | AMDVI_FEATURE_PPR | \ 183 AMDVI_FEATURE_IA | AMDVI_FEATURE_GT | AMDVI_FEATURE_HE | \ 184 AMDVI_GATS_MODE | AMDVI_HATS_MODE | AMDVI_FEATURE_GA) 185 186 /* capabilities header */ 187 #define AMDVI_CAPAB_FEATURES (AMDVI_CAPAB_FLAT_EXT | \ 188 AMDVI_CAPAB_FLAG_NPCACHE | AMDVI_CAPAB_FLAG_IOTLBSUP \ 189 | AMDVI_CAPAB_ID_SEC | AMDVI_CAPAB_INIT_TYPE | \ 190 AMDVI_CAPAB_FLAG_HTTUNNEL | AMDVI_CAPAB_EFR_SUP) 191 192 /* AMDVI default address */ 193 #define AMDVI_BASE_ADDR 0xfed80000ULL 194 195 /* page management constants */ 196 #define AMDVI_PAGE_SHIFT 12 197 #define AMDVI_PAGE_SIZE (1ULL << AMDVI_PAGE_SHIFT) 198 199 #define AMDVI_PAGE_SHIFT_4K 12 200 #define AMDVI_PAGE_MASK_4K GENMASK64(63, 12) 201 202 #define AMDVI_MAX_GVA_ADDR (2UL << 5) 203 #define AMDVI_MAX_PH_ADDR (40UL << 8) 204 #define AMDVI_MAX_VA_ADDR (48UL << 15) 205 206 /* Completion Wait data size */ 207 #define AMDVI_COMPLETION_DATA_SIZE 8 208 209 #define AMDVI_COMMAND_SIZE 16 210 211 #define AMDVI_INT_ADDR_FIRST 0xfee00000 212 #define AMDVI_INT_ADDR_LAST 0xfeefffff 213 #define AMDVI_INT_ADDR_SIZE (AMDVI_INT_ADDR_LAST - AMDVI_INT_ADDR_FIRST + 1) 214 215 /* SB IOAPIC is always on this device in AMD systems */ 216 #define AMDVI_IOAPIC_SB_DEVID PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0)) 217 218 /* Interrupt remapping errors */ 219 #define AMDVI_IR_ERR 0x1 220 #define AMDVI_IR_GET_IRTE 0x2 221 #define AMDVI_IR_TARGET_ABORT 0x3 222 223 /* Interrupt remapping */ 224 #define AMDVI_IR_REMAP_ENABLE 1ULL 225 #define AMDVI_IR_INTCTL_SHIFT 60 226 #define AMDVI_IR_INTCTL_ABORT 0 227 #define AMDVI_IR_INTCTL_PASS 1 228 #define AMDVI_IR_INTCTL_REMAP 2 229 230 #define AMDVI_IR_PHYS_ADDR_MASK GENMASK64(51, 6) 231 232 /* MSI data 10:0 bits (section 2.2.5.1 Fig 14) */ 233 #define AMDVI_IRTE_OFFSET 0x7ff 234 235 /* Delivery mode of MSI data (same as IOAPIC deilver mode encoding) */ 236 #define AMDVI_IOAPIC_INT_TYPE_FIXED 0x0 237 #define AMDVI_IOAPIC_INT_TYPE_ARBITRATED 0x1 238 #define AMDVI_IOAPIC_INT_TYPE_SMI 0x2 239 #define AMDVI_IOAPIC_INT_TYPE_NMI 0x4 240 #define AMDVI_IOAPIC_INT_TYPE_INIT 0x5 241 #define AMDVI_IOAPIC_INT_TYPE_EINT 0x7 242 243 /* Pass through interrupt */ 244 #define AMDVI_DEV_INT_PASS_MASK (1ULL << 56) 245 #define AMDVI_DEV_EINT_PASS_MASK (1ULL << 57) 246 #define AMDVI_DEV_NMI_PASS_MASK (1ULL << 58) 247 #define AMDVI_DEV_LINT0_PASS_MASK (1ULL << 62) 248 #define AMDVI_DEV_LINT1_PASS_MASK (1ULL << 63) 249 250 /* Interrupt remapping table fields (Guest VAPIC not enabled) */ 251 union irte { 252 uint32_t val; 253 struct { 254 uint32_t valid:1, 255 no_fault:1, 256 int_type:3, 257 rq_eoi:1, 258 dm:1, 259 guest_mode:1, 260 destination:8, 261 vector:8, 262 rsvd:8; 263 } fields; 264 }; 265 266 /* Interrupt remapping table fields (Guest VAPIC is enabled) */ 267 union irte_ga_lo { 268 uint64_t val; 269 270 /* For int remapping */ 271 struct { 272 uint64_t valid:1, 273 no_fault:1, 274 /* ------ */ 275 int_type:3, 276 rq_eoi:1, 277 dm:1, 278 /* ------ */ 279 guest_mode:1, 280 destination:24, 281 rsvd_1:32; 282 } fields_remap; 283 }; 284 285 union irte_ga_hi { 286 uint64_t val; 287 struct { 288 uint64_t vector:8, 289 rsvd_2:48, 290 destination_hi:8; 291 } fields; 292 }; 293 294 struct irte_ga { 295 union irte_ga_lo lo; 296 union irte_ga_hi hi; 297 }; 298 299 #define TYPE_AMD_IOMMU_DEVICE "amd-iommu" 300 OBJECT_DECLARE_SIMPLE_TYPE(AMDVIState, AMD_IOMMU_DEVICE) 301 302 #define TYPE_AMD_IOMMU_PCI "AMDVI-PCI" 303 OBJECT_DECLARE_SIMPLE_TYPE(AMDVIPCIState, AMD_IOMMU_PCI) 304 305 #define TYPE_AMD_IOMMU_MEMORY_REGION "amd-iommu-iommu-memory-region" 306 307 typedef struct AMDVIAddressSpace AMDVIAddressSpace; 308 309 /* functions to steal PCI config space */ 310 struct AMDVIPCIState { 311 PCIDevice dev; /* The PCI device itself */ 312 uint32_t capab_offset; /* capability offset pointer */ 313 }; 314 315 struct AMDVIState { 316 X86IOMMUState iommu; /* IOMMU bus device */ 317 AMDVIPCIState pci; /* IOMMU PCI device */ 318 319 uint32_t version; 320 321 uint64_t mmio_addr; 322 323 bool enabled; /* IOMMU enabled */ 324 bool ats_enabled; /* address translation enabled */ 325 bool cmdbuf_enabled; /* command buffer enabled */ 326 bool evtlog_enabled; /* event log enabled */ 327 bool excl_enabled; 328 329 hwaddr devtab; /* base address device table */ 330 size_t devtab_len; /* device table length */ 331 332 hwaddr cmdbuf; /* command buffer base address */ 333 uint64_t cmdbuf_len; /* command buffer length */ 334 uint32_t cmdbuf_head; /* current IOMMU read position */ 335 uint32_t cmdbuf_tail; /* next Software write position */ 336 bool completion_wait_intr; 337 338 hwaddr evtlog; /* base address event log */ 339 bool evtlog_intr; 340 uint32_t evtlog_len; /* event log length */ 341 uint32_t evtlog_head; /* current IOMMU write position */ 342 uint32_t evtlog_tail; /* current Software read position */ 343 344 /* unused for now */ 345 hwaddr excl_base; /* base DVA - IOMMU exclusion range */ 346 hwaddr excl_limit; /* limit of IOMMU exclusion range */ 347 bool excl_allow; /* translate accesses to the exclusion range */ 348 bool excl_enable; /* exclusion range enabled */ 349 350 hwaddr ppr_log; /* base address ppr log */ 351 uint32_t pprlog_len; /* ppr log len */ 352 uint32_t pprlog_head; /* ppr log head */ 353 uint32_t pprlog_tail; /* ppr log tail */ 354 355 MemoryRegion mr_mmio; /* MMIO region */ 356 MemoryRegion mr_sys; 357 MemoryRegion mr_nodma; 358 MemoryRegion mr_ir; 359 uint8_t mmior[AMDVI_MMIO_SIZE]; /* read/write MMIO */ 360 uint8_t w1cmask[AMDVI_MMIO_SIZE]; /* read/write 1 clear mask */ 361 uint8_t romask[AMDVI_MMIO_SIZE]; /* MMIO read/only mask */ 362 bool mmio_enabled; 363 364 /* for each served device */ 365 AMDVIAddressSpace **address_spaces[PCI_BUS_MAX]; 366 367 /* IOTLB */ 368 GHashTable *iotlb; 369 370 /* Interrupt remapping */ 371 bool ga_enabled; 372 bool xtsup; 373 }; 374 375 uint64_t amdvi_extended_feature_register(AMDVIState *s); 376 377 #endif 378