1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #ifndef __AMDGPU_MES_CTX_H__
25 #define __AMDGPU_MES_CTX_H__
26 
27 #include "v10_structs.h"
28 
29 enum {
30 	AMDGPU_MES_CTX_RPTR_OFFS = 0,
31 	AMDGPU_MES_CTX_WPTR_OFFS,
32 	AMDGPU_MES_CTX_FENCE_OFFS,
33 	AMDGPU_MES_CTX_COND_EXE_OFFS,
34 	AMDGPU_MES_CTX_TRAIL_FENCE_OFFS,
35 	AMDGPU_MES_CTX_MAX_OFFS,
36 };
37 
38 enum {
39 	AMDGPU_MES_CTX_RING_OFFS = AMDGPU_MES_CTX_MAX_OFFS,
40 	AMDGPU_MES_CTX_IB_OFFS,
41 	AMDGPU_MES_CTX_PADDING_OFFS,
42 };
43 
44 #define AMDGPU_MES_CTX_MAX_GFX_RINGS            1
45 #define AMDGPU_MES_CTX_MAX_COMPUTE_RINGS        4
46 #define AMDGPU_MES_CTX_MAX_SDMA_RINGS           2
47 #define AMDGPU_MES_CTX_MAX_RINGS					\
48 	(AMDGPU_MES_CTX_MAX_GFX_RINGS +					\
49 	 AMDGPU_MES_CTX_MAX_COMPUTE_RINGS +				\
50 	 AMDGPU_MES_CTX_MAX_SDMA_RINGS)
51 
52 #define AMDGPU_CSA_SDMA_SIZE    64
53 #define GFX10_MEC_HPD_SIZE	2048
54 
55 struct amdgpu_wb_slot {
56 	uint32_t data[8];
57 };
58 
59 struct amdgpu_mes_ctx_meta_data {
60 	struct {
61 		uint8_t ring[PAGE_SIZE * 4];
62 
63 		/* gfx csa */
64 		struct v10_gfx_meta_data gfx_meta_data;
65 
66 		uint8_t gds_backup[64 * 1024];
67 
68 		struct amdgpu_wb_slot slots[AMDGPU_MES_CTX_MAX_OFFS];
69 
70 		/* only for ib test */
71 		uint32_t ib[256] __aligned(256);
72 
73 		uint32_t padding[64];
74 
75 	} __aligned(PAGE_SIZE) gfx[AMDGPU_MES_CTX_MAX_GFX_RINGS];
76 
77 	struct {
78 		uint8_t ring[PAGE_SIZE * 4];
79 
80 		uint8_t mec_hpd[GFX10_MEC_HPD_SIZE];
81 
82 		struct amdgpu_wb_slot slots[AMDGPU_MES_CTX_MAX_OFFS];
83 
84 		/* only for ib test */
85 		uint32_t ib[256] __aligned(256);
86 
87 		uint32_t padding[64];
88 
89 	} __aligned(PAGE_SIZE) compute[AMDGPU_MES_CTX_MAX_COMPUTE_RINGS];
90 
91 	struct {
92 		uint8_t ring[PAGE_SIZE * 4];
93 
94 		/* sdma csa for mcbp */
95 		uint8_t sdma_meta_data[AMDGPU_CSA_SDMA_SIZE];
96 
97 		struct amdgpu_wb_slot slots[AMDGPU_MES_CTX_MAX_OFFS];
98 
99 		/* only for ib test */
100 		uint32_t ib[256] __aligned(256);
101 
102 		uint32_t padding[64];
103 
104 	} __aligned(PAGE_SIZE) sdma[AMDGPU_MES_CTX_MAX_SDMA_RINGS];
105 };
106 
107 struct amdgpu_mes_ctx_data {
108 	struct amdgpu_bo	*meta_data_obj;
109 	uint64_t                meta_data_gpu_addr;
110 	uint64_t                meta_data_mc_addr;
111 	struct amdgpu_bo_va	*meta_data_va;
112 	void                    *meta_data_ptr;
113 	uint32_t                gang_ids[AMDGPU_HW_IP_DMA+1];
114 };
115 
116 #define AMDGPU_FENCE_MES_QUEUE_FLAG     0x1000000u
117 #define AMDGPU_FENCE_MES_QUEUE_ID_MASK  (AMDGPU_FENCE_MES_QUEUE_FLAG - 1)
118 
119 #define AMDGPU_FENCE_MES_QUEUE_FLAG     0x1000000u
120 #define AMDGPU_FENCE_MES_QUEUE_ID_MASK  (AMDGPU_FENCE_MES_QUEUE_FLAG - 1)
121 
122 #endif
123