xref: /openbmc/u-boot/drivers/misc/ali512x.c (revision e8f80a5a)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2002
4  * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
5  */
6 
7 /*
8  * Based on sc520cdp.c from rolo 1.6:
9  *----------------------------------------------------------------------
10  * (C) Copyright 2000
11  * Sysgo Real-Time Solutions GmbH
12  * Klein-Winternheim, Germany
13  *----------------------------------------------------------------------
14  */
15 
16 #include <config.h>
17 
18 #include <common.h>
19 #include <asm/io.h>
20 #include <ali512x.h>
21 
22 
23 /* ALI M5123 Logical device numbers:
24  * 0 FDC
25  * 1 unused?
26  * 2 unused?
27  * 3 lpt
28  * 4 UART1
29  * 5 UART2
30  * 6 RTC
31  * 7 mouse/kbd
32  * 8 CIO
33  */
34 
35 /*
36  ************************************************************
37  *  Some access primitives for the ALi chip:                *
38  ************************************************************
39  */
40 
ali_write(u8 index,u8 value)41 static void ali_write(u8 index, u8 value)
42 {
43 	/* write an arbirary register */
44 	outb(index, ALI_INDEX);
45 	outb(value, ALI_DATA);
46 }
47 
48 #if 0
49 static int ali_read(u8 index)
50 {
51 	outb(index, ALI_INDEX);
52 	return inb(ALI_DATA);
53 }
54 #endif
55 
56 #define ALI_OPEN() \
57 	outb(0x51, ALI_INDEX); \
58 	outb(0x23, ALI_INDEX)
59 
60 
61 #define ALI_CLOSE() \
62 	outb(0xbb, ALI_INDEX)
63 
64 /* Select a logical device */
65 #define ALI_SELDEV(dev)	\
66 	ali_write(0x07, dev)
67 
68 
ali512x_init(void)69 void ali512x_init(void)
70 {
71 	ALI_OPEN();
72 
73 	ali_write(0x02, 0x01);	/* soft reset */
74 	ali_write(0x03, 0x03);	/* disable access to CIOs */
75 	ali_write(0x22, 0x00);	/* disable direct powerdown */
76 	ali_write(0x23, 0x00);	/* disable auto powerdown */
77 	ali_write(0x24, 0x00);	/* IR 8 is active hi, pin26 is PDIR */
78 
79 	ALI_CLOSE();
80 }
81 
ali512x_set_fdc(int enabled,u16 io,u8 irq,u8 dma_channel)82 void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel)
83 {
84 	ALI_OPEN();
85 	ALI_SELDEV(0);
86 
87 	ali_write(0x30, enabled?1:0);
88 	if (enabled) {
89 		ali_write(0x60, io >> 8);
90 		ali_write(0x61, io & 0xff);
91 		ali_write(0x70, irq);
92 		ali_write(0x74, dma_channel);
93 
94 		/* AT mode, no drive swap */
95 		ali_write(0xf0, 0x08);
96 		ali_write(0xf1, 0x00);
97 		ali_write(0xf2, 0xff);
98 		ali_write(0xf4, 0x00);
99 	}
100 	ALI_CLOSE();
101 }
102 
103 
ali512x_set_pp(int enabled,u16 io,u8 irq,u8 dma_channel)104 void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel)
105 {
106 	ALI_OPEN();
107 	ALI_SELDEV(3);
108 
109 	ali_write(0x30, enabled?1:0);
110 	if (enabled) {
111 		ali_write(0x60, io >> 8);
112 		ali_write(0x61, io & 0xff);
113 		ali_write(0x70, irq);
114 		ali_write(0x74, dma_channel);
115 
116 		/* mode: EPP 1.9, ECP FIFO threshold = 7, IRQ active low */
117 		ali_write(0xf0, 0xbc);
118 		/* 12 MHz, Burst DMA in ECP */
119 		ali_write(0xf1, 0x05);
120 	}
121 	ALI_CLOSE();
122 
123 }
124 
ali512x_set_uart(int enabled,int index,u16 io,u8 irq)125 void ali512x_set_uart(int enabled, int index, u16 io, u8 irq)
126 {
127 	ALI_OPEN();
128 	ALI_SELDEV(index?5:4);
129 
130 	ali_write(0x30, enabled?1:0);
131 	if (enabled) {
132 		ali_write(0x60, io >> 8);
133 		ali_write(0x61, io & 0xff);
134 		ali_write(0x70, irq);
135 
136 		ali_write(0xf0, 0x00);
137 		ali_write(0xf1, 0x00);
138 
139 		/* huh? write 0xf2 twice - a typo in rolo
140 		 * or some secret ali errata? Who knows?
141 		 */
142 		if (index) {
143 			ali_write(0xf2, 0x00);
144 		}
145 		ali_write(0xf2, 0x0c);
146 	}
147 	ALI_CLOSE();
148 
149 }
150 
ali512x_set_uart2_irda(int enabled)151 void ali512x_set_uart2_irda(int enabled)
152 {
153 	ALI_OPEN();
154 	ALI_SELDEV(5);
155 
156 	ali_write(0xf1, enabled?0x48:0x00); /* fullduplex IrDa */
157 	ALI_CLOSE();
158 
159 }
160 
ali512x_set_rtc(int enabled,u16 io,u8 irq)161 void ali512x_set_rtc(int enabled, u16 io, u8 irq)
162 {
163 	ALI_OPEN();
164 	ALI_SELDEV(6);
165 
166 	ali_write(0x30, enabled?1:0);
167 	if (enabled) {
168 		ali_write(0x60, io >> 8);
169 		ali_write(0x61, io & 0xff);
170 		ali_write(0x70, irq);
171 
172 		ali_write(0xf0, 0x00);
173 	}
174 	ALI_CLOSE();
175 }
176 
ali512x_set_kbc(int enabled,u8 kbc_irq,u8 mouse_irq)177 void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq)
178 {
179 	ALI_OPEN();
180 	ALI_SELDEV(7);
181 
182 	ali_write(0x30, enabled?1:0);
183 	if (enabled) {
184 		ali_write(0x70, kbc_irq);
185 		ali_write(0x72, mouse_irq);
186 
187 		ali_write(0xf0, 0x00);
188 	}
189 	ALI_CLOSE();
190 }
191 
192 
193 /* Common I/O
194  *
195  * (This descripotsion is base on several incompete sources
196  *  since I have not been able to obtain any datasheet for the device
197  *  there may be some mis-understandings burried in here.
198  *  -- Daniel daniel@omicron.se)
199  *
200  * There are 22 CIO pins numbered
201  * 10-17
202  * 20-25
203  * 30-37
204  *
205  * 20-24 are dedicated CIO pins, the other 17 are muliplexed with
206  * other functions.
207  *
208  *           Secondary
209  * CIO Pin   Function    Decription
210  * =======================================================
211  * CIO10     IRQIN1      Interrupt input 1?
212  * CIO11     IRQIN2      Interrupt input 2?
213  * CIO12     IRRX        IrDa Receive
214  * CIO13     IRTX        IrDa Transmit
215  * CIO14     P21         KBC P21 fucntion
216  * CIO15     P20         KBC P21 fucntion
217  * CIO16     I2C_CLK     I2C Clock
218  * CIO17     I2C_DAT     I2C Data
219  *
220  * CIO20     -
221  * CIO21     -
222  * CIO22     -
223  * CIO23     -
224  * CIO24     -
225  * CIO25     LOCK        Keylock
226  *
227  * CIO30     KBC_CLK     Keybaord Clock
228  * CIO31     CS0J        General Chip Select decoder CS0J
229  * CIO32     CS1J        General Chip Select decoder CS1J
230  * CIO33     ALT_KCLK    Alternative Keyboard Clock
231  * CIO34     ALT_KDAT    Alternative Keyboard Data
232  * CIO35     ALT_MCLK    Alternative Mouse Clock
233  * CIO36     ALT_MDAT    Alternative Mouse Data
234  * CIO37     ALT_KBC     Alternative KBC select
235  *
236  * The CIO use an indirect address scheme.
237  *
238  * Reigster 3 in the SIO is used to select the index and data
239  * port addresses where the CIO I/O registers show up.
240  * The function selection registers are accessible under
241  * function SIO 8.
242  *
243  * SIO reigster 3 (CIO Address Selection) bit definitions:
244  * bit 7   CIO index and data registers enabled
245  * bit 1-0 CIO indirect registers port address select
246  *	 0  index = 0xE0 data = 0xE1
247  *       1  index = 0xE2 data = 0xE3
248  *       2  index = 0xE4 data = 0xE5
249  *       3  index = 0xEA data = 0xEB
250  *
251  * There are three CIO I/O register accessed via CIO index port and CIO data port
252  * 0x01     CIO 10-17 data
253  * 0x02     CIO 20-25 data (bits 7-6 unused)
254  * 0x03     CIO 30-37 data
255  *
256  *
257  * The pin function is accessed through normal
258  * SIO registers, each register have the same format:
259  *
260  * Bit   Function                     Value
261  * 0     Input/output                 1=input
262  * 1     Polarity of signal           1=inverted
263  * 2     Unused                       ??
264  * 3     Function (normal or special) 1=special
265  * 7-4   Unused
266  *
267  * SIO REG
268  * 0xe0     CIO 10 Config
269  * 0xe1     CIO 11 Config
270  * 0xe2     CIO 12 Config
271  * 0xe3     CIO 13 Config
272  * 0xe4     CIO 14 Config
273  * 0xe5     CIO 15 Config
274  * 0xe6     CIO 16 Config
275  * 0xe7     CIO 16 Config
276  *
277  * 0xe8     CIO 20 Config
278  * 0xe9     CIO 21 Config
279  * 0xea     CIO 22 Config
280  * 0xeb     CIO 23 Config
281  * 0xec     CIO 24 Config
282  * 0xed     CIO 25 Config
283  *
284  * 0xf5     CIO 30 Config
285  * 0xf6     CIO 31 Config
286  * 0xf7     CIO 32 Config
287  * 0xf8     CIO 33 Config
288  * 0xf9     CIO 34 Config
289  * 0xfa     CIO 35 Config
290  * 0xfb     CIO 36 Config
291  * 0xfc     CIO 37 Config
292  *
293  */
294 
295 #define ALI_CIO_PORT_SEL 0x83
296 #define ALI_CIO_INDEX    0xea
297 #define ALI_CIO_DATA     0xeb
298 
ali512x_set_cio(int enabled)299 void ali512x_set_cio(int enabled)
300 {
301 	int i;
302 
303 	ALI_OPEN();
304 
305 	if (enabled) {
306 		ali_write(0x3, ALI_CIO_PORT_SEL);    /* Enable CIO data register */
307 	} else {
308 		ali_write(0x3, ALI_CIO_PORT_SEL & ~0x80);
309 	}
310 
311 	ALI_SELDEV(8);
312 
313 	ali_write(0x30, enabled?1:0);
314 
315 	/* set all pins to input to start with */
316 	for (i=0xe0;i<0xee;i++) {
317 		ali_write(i, 1);
318 	}
319 
320 	for (i=0xf5;i<0xfe;i++) {
321 		ali_write(i, 1);
322 	}
323 
324 	ALI_CLOSE();
325 }
326 
327 
ali512x_cio_function(int pin,int special,int inv,int input)328 void ali512x_cio_function(int pin, int special, int inv, int input)
329 {
330 	u8 data;
331 	u8 addr;
332 
333 	/* valid pins are 10-17, 20-25 and 30-37 */
334 	if (pin >= 10 && pin <= 17) {
335 		addr = 0xe0+(pin&7);
336 	} else if (pin >= 20 && pin <= 25) {
337 		addr = 0xe8+(pin&7);
338 	} else if (pin >= 30 && pin <= 37) {
339 		addr = 0xf5+(pin&7);
340 	} else {
341 		return;
342 	}
343 
344 	ALI_OPEN();
345 
346 	ALI_SELDEV(8);
347 
348 
349 	data=0xf4;
350 	if (special) {
351 		data |= 0x08;
352 	} else {
353 		if (inv) {
354 			data |= 0x02;
355 		}
356 		if (input) {
357 			data |= 0x01;
358 		}
359 	}
360 
361 	ali_write(addr, data);
362 
363 	ALI_CLOSE();
364 }
365 
ali512x_cio_out(int pin,int value)366 void ali512x_cio_out(int pin, int value)
367 {
368 	u8 reg;
369 	u8 data;
370 	u8 bit;
371 
372 	reg = pin/10;
373 	bit = 1 << (pin%10);
374 
375 
376 	outb(reg, ALI_CIO_INDEX);     /* select I/O register */
377 	data = inb(ALI_CIO_DATA);
378 	if (value) {
379 		data |= bit;
380 	} else {
381 		data &= ~bit;
382 	}
383 	outb(data, ALI_CIO_DATA);
384 }
385 
ali512x_cio_in(int pin)386 int ali512x_cio_in(int pin)
387 {
388 	u8 reg;
389 	u8 data;
390 	u8 bit;
391 
392 	/* valid pins are 10-17, 20-25 and 30-37 */
393 	reg = pin/10;
394 	bit = 1 << (pin%10);
395 
396 
397 	outb(reg, ALI_CIO_INDEX);     /* select I/O register */
398 	data = inb(ALI_CIO_DATA);
399 
400 	return data & bit;
401 }
402