1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * ahci.c - AHCI SATA support
4 *
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2004-2005 Red Hat, Inc.
10 *
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
13 *
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
17 */
18
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/dmi.h>
28 #include <linux/gfp.h>
29 #include <scsi/scsi_host.h>
30 #include <scsi/scsi_cmnd.h>
31 #include <linux/libata.h>
32 #include <linux/ahci-remap.h>
33 #include <linux/io-64-nonatomic-lo-hi.h>
34 #include "ahci.h"
35
36 #define DRV_NAME "ahci"
37 #define DRV_VERSION "3.0"
38
39 enum {
40 AHCI_PCI_BAR_STA2X11 = 0,
41 AHCI_PCI_BAR_CAVIUM = 0,
42 AHCI_PCI_BAR_LOONGSON = 0,
43 AHCI_PCI_BAR_ENMOTUS = 2,
44 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
45 AHCI_PCI_BAR_STANDARD = 5,
46 };
47
48 enum board_ids {
49 /* board IDs by feature in alphabetical order */
50 board_ahci,
51 board_ahci_43bit_dma,
52 board_ahci_ign_iferr,
53 board_ahci_low_power,
54 board_ahci_no_debounce_delay,
55 board_ahci_nomsi,
56 board_ahci_noncq,
57 board_ahci_nosntf,
58 board_ahci_yes_fbs,
59
60 /* board IDs for specific chipsets in alphabetical order */
61 board_ahci_al,
62 board_ahci_avn,
63 board_ahci_mcp65,
64 board_ahci_mcp77,
65 board_ahci_mcp89,
66 board_ahci_mv,
67 board_ahci_sb600,
68 board_ahci_sb700, /* for SB700 and SB800 */
69 board_ahci_vt8251,
70
71 /*
72 * board IDs for Intel chipsets that support more than 6 ports
73 * *and* end up needing the PCS quirk.
74 */
75 board_ahci_pcs7,
76
77 /* aliases */
78 board_ahci_mcp_linux = board_ahci_mcp65,
79 board_ahci_mcp67 = board_ahci_mcp65,
80 board_ahci_mcp73 = board_ahci_mcp65,
81 board_ahci_mcp79 = board_ahci_mcp77,
82 };
83
84 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
85 static void ahci_remove_one(struct pci_dev *dev);
86 static void ahci_shutdown_one(struct pci_dev *dev);
87 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv);
88 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
91 unsigned long deadline);
92 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
93 static bool is_mcp89_apple(struct pci_dev *pdev);
94 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
95 unsigned long deadline);
96 #ifdef CONFIG_PM
97 static int ahci_pci_device_runtime_suspend(struct device *dev);
98 static int ahci_pci_device_runtime_resume(struct device *dev);
99 #ifdef CONFIG_PM_SLEEP
100 static int ahci_pci_device_suspend(struct device *dev);
101 static int ahci_pci_device_resume(struct device *dev);
102 #endif
103 #endif /* CONFIG_PM */
104
105 static const struct scsi_host_template ahci_sht = {
106 AHCI_SHT("ahci"),
107 };
108
109 static struct ata_port_operations ahci_vt8251_ops = {
110 .inherits = &ahci_ops,
111 .hardreset = ahci_vt8251_hardreset,
112 };
113
114 static struct ata_port_operations ahci_p5wdh_ops = {
115 .inherits = &ahci_ops,
116 .hardreset = ahci_p5wdh_hardreset,
117 };
118
119 static struct ata_port_operations ahci_avn_ops = {
120 .inherits = &ahci_ops,
121 .hardreset = ahci_avn_hardreset,
122 };
123
124 static const struct ata_port_info ahci_port_info[] = {
125 /* by features */
126 [board_ahci] = {
127 .flags = AHCI_FLAG_COMMON,
128 .pio_mask = ATA_PIO4,
129 .udma_mask = ATA_UDMA6,
130 .port_ops = &ahci_ops,
131 },
132 [board_ahci_43bit_dma] = {
133 AHCI_HFLAGS (AHCI_HFLAG_43BIT_ONLY),
134 .flags = AHCI_FLAG_COMMON,
135 .pio_mask = ATA_PIO4,
136 .udma_mask = ATA_UDMA6,
137 .port_ops = &ahci_ops,
138 },
139 [board_ahci_ign_iferr] = {
140 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
141 .flags = AHCI_FLAG_COMMON,
142 .pio_mask = ATA_PIO4,
143 .udma_mask = ATA_UDMA6,
144 .port_ops = &ahci_ops,
145 },
146 [board_ahci_low_power] = {
147 AHCI_HFLAGS (AHCI_HFLAG_USE_LPM_POLICY),
148 .flags = AHCI_FLAG_COMMON,
149 .pio_mask = ATA_PIO4,
150 .udma_mask = ATA_UDMA6,
151 .port_ops = &ahci_ops,
152 },
153 [board_ahci_no_debounce_delay] = {
154 .flags = AHCI_FLAG_COMMON,
155 .link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY,
156 .pio_mask = ATA_PIO4,
157 .udma_mask = ATA_UDMA6,
158 .port_ops = &ahci_ops,
159 },
160 [board_ahci_nomsi] = {
161 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
162 .flags = AHCI_FLAG_COMMON,
163 .pio_mask = ATA_PIO4,
164 .udma_mask = ATA_UDMA6,
165 .port_ops = &ahci_ops,
166 },
167 [board_ahci_noncq] = {
168 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
169 .flags = AHCI_FLAG_COMMON,
170 .pio_mask = ATA_PIO4,
171 .udma_mask = ATA_UDMA6,
172 .port_ops = &ahci_ops,
173 },
174 [board_ahci_nosntf] = {
175 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
176 .flags = AHCI_FLAG_COMMON,
177 .pio_mask = ATA_PIO4,
178 .udma_mask = ATA_UDMA6,
179 .port_ops = &ahci_ops,
180 },
181 [board_ahci_yes_fbs] = {
182 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
183 .flags = AHCI_FLAG_COMMON,
184 .pio_mask = ATA_PIO4,
185 .udma_mask = ATA_UDMA6,
186 .port_ops = &ahci_ops,
187 },
188 /* by chipsets */
189 [board_ahci_al] = {
190 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
191 .flags = AHCI_FLAG_COMMON,
192 .pio_mask = ATA_PIO4,
193 .udma_mask = ATA_UDMA6,
194 .port_ops = &ahci_ops,
195 },
196 [board_ahci_avn] = {
197 .flags = AHCI_FLAG_COMMON,
198 .pio_mask = ATA_PIO4,
199 .udma_mask = ATA_UDMA6,
200 .port_ops = &ahci_avn_ops,
201 },
202 [board_ahci_mcp65] = {
203 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
204 AHCI_HFLAG_YES_NCQ),
205 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
206 .pio_mask = ATA_PIO4,
207 .udma_mask = ATA_UDMA6,
208 .port_ops = &ahci_ops,
209 },
210 [board_ahci_mcp77] = {
211 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
212 .flags = AHCI_FLAG_COMMON,
213 .pio_mask = ATA_PIO4,
214 .udma_mask = ATA_UDMA6,
215 .port_ops = &ahci_ops,
216 },
217 [board_ahci_mcp89] = {
218 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
219 .flags = AHCI_FLAG_COMMON,
220 .pio_mask = ATA_PIO4,
221 .udma_mask = ATA_UDMA6,
222 .port_ops = &ahci_ops,
223 },
224 [board_ahci_mv] = {
225 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
226 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
227 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
228 .pio_mask = ATA_PIO4,
229 .udma_mask = ATA_UDMA6,
230 .port_ops = &ahci_ops,
231 },
232 [board_ahci_sb600] = {
233 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
234 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
235 AHCI_HFLAG_32BIT_ONLY),
236 .flags = AHCI_FLAG_COMMON,
237 .pio_mask = ATA_PIO4,
238 .udma_mask = ATA_UDMA6,
239 .port_ops = &ahci_pmp_retry_srst_ops,
240 },
241 [board_ahci_sb700] = { /* for SB700 and SB800 */
242 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
243 .flags = AHCI_FLAG_COMMON,
244 .pio_mask = ATA_PIO4,
245 .udma_mask = ATA_UDMA6,
246 .port_ops = &ahci_pmp_retry_srst_ops,
247 },
248 [board_ahci_vt8251] = {
249 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
250 .flags = AHCI_FLAG_COMMON,
251 .pio_mask = ATA_PIO4,
252 .udma_mask = ATA_UDMA6,
253 .port_ops = &ahci_vt8251_ops,
254 },
255 [board_ahci_pcs7] = {
256 .flags = AHCI_FLAG_COMMON,
257 .pio_mask = ATA_PIO4,
258 .udma_mask = ATA_UDMA6,
259 .port_ops = &ahci_ops,
260 },
261 };
262
263 static const struct pci_device_id ahci_pci_tbl[] = {
264 /* Intel */
265 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */
266 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
267 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
268 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
269 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
270 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
271 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
272 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
273 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
274 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
275 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
276 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
277 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8/Lewisburg RAID*/
278 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
279 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
280 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
281 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
282 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
283 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
284 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
285 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
286 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_low_power }, /* ICH9M */
287 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_low_power }, /* ICH9M */
288 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_low_power }, /* ICH9M */
289 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_low_power }, /* ICH9M */
290 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_low_power }, /* ICH9M */
291 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
292 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_low_power }, /* ICH9M */
293 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
294 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
295 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
296 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
297 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
298 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
299 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
300 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
301 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
302 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_low_power }, /* PCH M AHCI */
303 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
304 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_low_power }, /* PCH M RAID */
305 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
306 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
307 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
308 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
309 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
310 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
311 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
312 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
313 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
314 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
315 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
316 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
317 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
318 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
319 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
320 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
321 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
322 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
323 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
324 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
325 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
326 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
327 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_low_power }, /* CPT M AHCI */
328 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
329 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_low_power }, /* CPT M RAID */
330 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
331 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
332 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
333 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
334 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
335 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
336 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
337 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_low_power }, /* Panther M AHCI */
338 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
339 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
340 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
341 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_low_power }, /* Panther M RAID */
342 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
343 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
344 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_low_power }, /* Lynx M AHCI */
345 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
346 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_low_power }, /* Lynx M RAID */
347 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
348 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_low_power }, /* Lynx M RAID */
349 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
350 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_low_power }, /* Lynx M RAID */
351 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_low_power }, /* Lynx LP AHCI */
352 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_low_power }, /* Lynx LP AHCI */
353 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_low_power }, /* Lynx LP RAID */
354 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_low_power }, /* Lynx LP RAID */
355 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_low_power }, /* Lynx LP RAID */
356 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_low_power }, /* Lynx LP RAID */
357 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_low_power }, /* Lynx LP RAID */
358 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_low_power }, /* Lynx LP RAID */
359 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_low_power }, /* Cannon Lake PCH-LP AHCI */
360 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
361 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
362 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
363 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
364 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
365 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
366 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
367 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
368 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
369 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
370 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
371 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
372 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
373 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
374 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
375 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
376 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg/Lewisburg AHCI*/
377 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* *burg SATA0 'RAID' */
378 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* *burg SATA1 'RAID' */
379 { PCI_VDEVICE(INTEL, 0x282f), board_ahci }, /* *burg SATA2 'RAID' */
380 { PCI_VDEVICE(INTEL, 0x43d4), board_ahci }, /* Rocket Lake PCH-H RAID */
381 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci }, /* Rocket Lake PCH-H RAID */
382 { PCI_VDEVICE(INTEL, 0x43d6), board_ahci }, /* Rocket Lake PCH-H RAID */
383 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci }, /* Rocket Lake PCH-H RAID */
384 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
385 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
386 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
387 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
388 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
389 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
390 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
391 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
392 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
393 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_low_power }, /* Wildcat LP AHCI */
394 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_low_power }, /* Wildcat LP RAID */
395 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_low_power }, /* Wildcat LP RAID */
396 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_low_power }, /* Wildcat LP RAID */
397 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
398 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_low_power }, /* 9 Series M AHCI */
399 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
400 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_low_power }, /* 9 Series M RAID */
401 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
402 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_low_power }, /* 9 Series M RAID */
403 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
404 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_low_power }, /* 9 Series M RAID */
405 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_low_power }, /* Sunrise LP AHCI */
406 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_low_power }, /* Sunrise LP RAID */
407 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_low_power }, /* Sunrise LP RAID */
408 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
409 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_low_power }, /* Sunrise M AHCI */
410 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
411 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
412 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_low_power }, /* Sunrise M RAID */
413 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
414 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
415 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
416 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
417 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
418 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
419 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
420 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
421 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
422 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
423 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
424 { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */
425 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_low_power }, /* Bay Trail AHCI */
426 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_low_power }, /* Bay Trail AHCI */
427 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_low_power }, /* Cherry Tr. AHCI */
428 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_low_power }, /* ApolloLake AHCI */
429 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_low_power }, /* Ice Lake LP AHCI */
430 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_low_power }, /* Comet Lake PCH-U AHCI */
431 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_low_power }, /* Comet Lake PCH RAID */
432 /* Elkhart Lake IDs 0x4b60 & 0x4b62 https://sata-io.org/product/8803 not tested yet */
433 { PCI_VDEVICE(INTEL, 0x4b63), board_ahci_low_power }, /* Elkhart Lake AHCI */
434
435 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
436 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
437 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
438 /* JMicron 362B and 362C have an AHCI function with IDE class code */
439 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
440 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
441 /* May need to update quirk_jmicron_async_suspend() for additions */
442
443 /* ATI */
444 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
445 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
446 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
447 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
448 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
449 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
450 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
451
452 /* Amazon's Annapurna Labs support */
453 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
454 .class = PCI_CLASS_STORAGE_SATA_AHCI,
455 .class_mask = 0xffffff,
456 board_ahci_al },
457 /* AMD */
458 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
459 { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */
460 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
461 { PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power }, /* AMD Green Sardine */
462 /* AMD is using RAID class only for ahci controllers */
463 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
464 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
465
466 /* Dell S140/S150 */
467 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID,
468 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
469
470 /* VIA */
471 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
472 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
473
474 /* NVIDIA */
475 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
476 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
477 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
478 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
479 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
480 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
481 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
482 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
483 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
484 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
485 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
486 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
487 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
488 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
489 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
490 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
491 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
492 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
493 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
494 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
495 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
496 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
497 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
498 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
499 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
500 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
501 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
502 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
503 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
504 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
505 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
506 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
507 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
508 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
509 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
510 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
511 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
512 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
513 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
514 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
515 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
516 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
517 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
518 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
519 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
520 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
521 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
522 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
523 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
524 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
525 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
526 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
527 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
528 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
529 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
530 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
531 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
532 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
533 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
534 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
535 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
536 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
537 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
538 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
539 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
540 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
541 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
542 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
543 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
544 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
545 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
546 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
547 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
548 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
549 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
550 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
551 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
552 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
553 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
554 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
555 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
556 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
557 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
558 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
559
560 /* SiS */
561 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
562 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
563 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
564
565 /* ST Microelectronics */
566 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
567
568 /* Marvell */
569 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
570 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
571 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
572 .class = PCI_CLASS_STORAGE_SATA_AHCI,
573 .class_mask = 0xffffff,
574 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
575 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
576 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
577 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
578 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
579 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
580 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
581 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
582 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
583 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
584 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
585 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
586 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
587 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
588 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
589 .driver_data = board_ahci_yes_fbs },
590 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
591 .driver_data = board_ahci_yes_fbs },
592 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
593 .driver_data = board_ahci_yes_fbs },
594 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
595 .driver_data = board_ahci_yes_fbs },
596 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9235),
597 .driver_data = board_ahci_no_debounce_delay },
598 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
599 .driver_data = board_ahci_yes_fbs },
600 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
601 .driver_data = board_ahci_yes_fbs },
602
603 /* Promise */
604 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
605 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
606
607 /* ASMedia */
608 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci_43bit_dma }, /* ASM1060 */
609 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci_43bit_dma }, /* ASM1060 */
610 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci_43bit_dma }, /* ASM1061 */
611 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci_43bit_dma }, /* ASM1061/1062 */
612 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci_43bit_dma }, /* ASM1061R */
613 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci_43bit_dma }, /* ASM1062R */
614 { PCI_VDEVICE(ASMEDIA, 0x0624), board_ahci_43bit_dma }, /* ASM1062+JMB575 */
615 { PCI_VDEVICE(ASMEDIA, 0x1062), board_ahci }, /* ASM1062A */
616 { PCI_VDEVICE(ASMEDIA, 0x1064), board_ahci }, /* ASM1064 */
617 { PCI_VDEVICE(ASMEDIA, 0x1164), board_ahci }, /* ASM1164 */
618 { PCI_VDEVICE(ASMEDIA, 0x1165), board_ahci }, /* ASM1165 */
619 { PCI_VDEVICE(ASMEDIA, 0x1166), board_ahci }, /* ASM1166 */
620
621 /*
622 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
623 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
624 */
625 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
626 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
627
628 /* Enmotus */
629 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
630
631 /* Loongson */
632 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
633
634 /* Generic, PCI class code for AHCI */
635 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
636 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
637
638 { } /* terminate list */
639 };
640
641 static const struct dev_pm_ops ahci_pci_pm_ops = {
642 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
643 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
644 ahci_pci_device_runtime_resume, NULL)
645 };
646
647 static struct pci_driver ahci_pci_driver = {
648 .name = DRV_NAME,
649 .id_table = ahci_pci_tbl,
650 .probe = ahci_init_one,
651 .remove = ahci_remove_one,
652 .shutdown = ahci_shutdown_one,
653 .driver = {
654 .pm = &ahci_pci_pm_ops,
655 },
656 };
657
658 #if IS_ENABLED(CONFIG_PATA_MARVELL)
659 static int marvell_enable;
660 #else
661 static int marvell_enable = 1;
662 #endif
663 module_param(marvell_enable, int, 0644);
664 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
665
666 static int mobile_lpm_policy = -1;
667 module_param(mobile_lpm_policy, int, 0644);
668 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
669
ahci_pci_save_initial_config(struct pci_dev * pdev,struct ahci_host_priv * hpriv)670 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
671 struct ahci_host_priv *hpriv)
672 {
673 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
674 dev_info(&pdev->dev, "JMB361 has only one port\n");
675 hpriv->saved_port_map = 1;
676 }
677
678 /*
679 * Temporary Marvell 6145 hack: PATA port presence
680 * is asserted through the standard AHCI port
681 * presence register, as bit 4 (counting from 0)
682 */
683 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
684 if (pdev->device == 0x6121)
685 hpriv->mask_port_map = 0x3;
686 else
687 hpriv->mask_port_map = 0xf;
688 dev_info(&pdev->dev,
689 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
690 }
691
692 ahci_save_initial_config(&pdev->dev, hpriv);
693 }
694
ahci_pci_reset_controller(struct ata_host * host)695 static int ahci_pci_reset_controller(struct ata_host *host)
696 {
697 struct pci_dev *pdev = to_pci_dev(host->dev);
698 struct ahci_host_priv *hpriv = host->private_data;
699 int rc;
700
701 rc = ahci_reset_controller(host);
702 if (rc)
703 return rc;
704
705 /*
706 * If platform firmware failed to enable ports, try to enable
707 * them here.
708 */
709 ahci_intel_pcs_quirk(pdev, hpriv);
710
711 return 0;
712 }
713
ahci_pci_init_controller(struct ata_host * host)714 static void ahci_pci_init_controller(struct ata_host *host)
715 {
716 struct ahci_host_priv *hpriv = host->private_data;
717 struct pci_dev *pdev = to_pci_dev(host->dev);
718 void __iomem *port_mmio;
719 u32 tmp;
720 int mv;
721
722 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
723 if (pdev->device == 0x6121)
724 mv = 2;
725 else
726 mv = 4;
727 port_mmio = __ahci_port_base(hpriv, mv);
728
729 writel(0, port_mmio + PORT_IRQ_MASK);
730
731 /* clear port IRQ */
732 tmp = readl(port_mmio + PORT_IRQ_STAT);
733 dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
734 if (tmp)
735 writel(tmp, port_mmio + PORT_IRQ_STAT);
736 }
737
738 ahci_init_controller(host);
739 }
740
ahci_vt8251_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)741 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
742 unsigned long deadline)
743 {
744 struct ata_port *ap = link->ap;
745 struct ahci_host_priv *hpriv = ap->host->private_data;
746 bool online;
747 int rc;
748
749 hpriv->stop_engine(ap);
750
751 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
752 deadline, &online, NULL);
753
754 hpriv->start_engine(ap);
755
756 /* vt8251 doesn't clear BSY on signature FIS reception,
757 * request follow-up softreset.
758 */
759 return online ? -EAGAIN : rc;
760 }
761
ahci_p5wdh_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)762 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
763 unsigned long deadline)
764 {
765 struct ata_port *ap = link->ap;
766 struct ahci_port_priv *pp = ap->private_data;
767 struct ahci_host_priv *hpriv = ap->host->private_data;
768 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
769 struct ata_taskfile tf;
770 bool online;
771 int rc;
772
773 hpriv->stop_engine(ap);
774
775 /* clear D2H reception area to properly wait for D2H FIS */
776 ata_tf_init(link->device, &tf);
777 tf.status = ATA_BUSY;
778 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
779
780 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
781 deadline, &online, NULL);
782
783 hpriv->start_engine(ap);
784
785 /* The pseudo configuration device on SIMG4726 attached to
786 * ASUS P5W-DH Deluxe doesn't send signature FIS after
787 * hardreset if no device is attached to the first downstream
788 * port && the pseudo device locks up on SRST w/ PMP==0. To
789 * work around this, wait for !BSY only briefly. If BSY isn't
790 * cleared, perform CLO and proceed to IDENTIFY (achieved by
791 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
792 *
793 * Wait for two seconds. Devices attached to downstream port
794 * which can't process the following IDENTIFY after this will
795 * have to be reset again. For most cases, this should
796 * suffice while making probing snappish enough.
797 */
798 if (online) {
799 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
800 ahci_check_ready);
801 if (rc)
802 ahci_kick_engine(ap);
803 }
804 return rc;
805 }
806
807 /*
808 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
809 *
810 * It has been observed with some SSDs that the timing of events in the
811 * link synchronization phase can leave the port in a state that can not
812 * be recovered by a SATA-hard-reset alone. The failing signature is
813 * SStatus.DET stuck at 1 ("Device presence detected but Phy
814 * communication not established"). It was found that unloading and
815 * reloading the driver when this problem occurs allows the drive
816 * connection to be recovered (DET advanced to 0x3). The critical
817 * component of reloading the driver is that the port state machines are
818 * reset by bouncing "port enable" in the AHCI PCS configuration
819 * register. So, reproduce that effect by bouncing a port whenever we
820 * see DET==1 after a reset.
821 */
ahci_avn_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)822 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
823 unsigned long deadline)
824 {
825 const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context);
826 struct ata_port *ap = link->ap;
827 struct ahci_port_priv *pp = ap->private_data;
828 struct ahci_host_priv *hpriv = ap->host->private_data;
829 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
830 unsigned long tmo = deadline - jiffies;
831 struct ata_taskfile tf;
832 bool online;
833 int rc, i;
834
835 hpriv->stop_engine(ap);
836
837 for (i = 0; i < 2; i++) {
838 u16 val;
839 u32 sstatus;
840 int port = ap->port_no;
841 struct ata_host *host = ap->host;
842 struct pci_dev *pdev = to_pci_dev(host->dev);
843
844 /* clear D2H reception area to properly wait for D2H FIS */
845 ata_tf_init(link->device, &tf);
846 tf.status = ATA_BUSY;
847 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
848
849 rc = sata_link_hardreset(link, timing, deadline, &online,
850 ahci_check_ready);
851
852 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
853 (sstatus & 0xf) != 1)
854 break;
855
856 ata_link_info(link, "avn bounce port%d\n", port);
857
858 pci_read_config_word(pdev, 0x92, &val);
859 val &= ~(1 << port);
860 pci_write_config_word(pdev, 0x92, val);
861 ata_msleep(ap, 1000);
862 val |= 1 << port;
863 pci_write_config_word(pdev, 0x92, val);
864 deadline += tmo;
865 }
866
867 hpriv->start_engine(ap);
868
869 if (online)
870 *class = ahci_dev_classify(ap);
871
872 return rc;
873 }
874
875
876 #ifdef CONFIG_PM
ahci_pci_disable_interrupts(struct ata_host * host)877 static void ahci_pci_disable_interrupts(struct ata_host *host)
878 {
879 struct ahci_host_priv *hpriv = host->private_data;
880 void __iomem *mmio = hpriv->mmio;
881 u32 ctl;
882
883 /* AHCI spec rev1.1 section 8.3.3:
884 * Software must disable interrupts prior to requesting a
885 * transition of the HBA to D3 state.
886 */
887 ctl = readl(mmio + HOST_CTL);
888 ctl &= ~HOST_IRQ_EN;
889 writel(ctl, mmio + HOST_CTL);
890 readl(mmio + HOST_CTL); /* flush */
891 }
892
ahci_pci_device_runtime_suspend(struct device * dev)893 static int ahci_pci_device_runtime_suspend(struct device *dev)
894 {
895 struct pci_dev *pdev = to_pci_dev(dev);
896 struct ata_host *host = pci_get_drvdata(pdev);
897
898 ahci_pci_disable_interrupts(host);
899 return 0;
900 }
901
ahci_pci_device_runtime_resume(struct device * dev)902 static int ahci_pci_device_runtime_resume(struct device *dev)
903 {
904 struct pci_dev *pdev = to_pci_dev(dev);
905 struct ata_host *host = pci_get_drvdata(pdev);
906 int rc;
907
908 rc = ahci_pci_reset_controller(host);
909 if (rc)
910 return rc;
911 ahci_pci_init_controller(host);
912 return 0;
913 }
914
915 #ifdef CONFIG_PM_SLEEP
ahci_pci_device_suspend(struct device * dev)916 static int ahci_pci_device_suspend(struct device *dev)
917 {
918 struct pci_dev *pdev = to_pci_dev(dev);
919 struct ata_host *host = pci_get_drvdata(pdev);
920 struct ahci_host_priv *hpriv = host->private_data;
921
922 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
923 dev_err(&pdev->dev,
924 "BIOS update required for suspend/resume\n");
925 return -EIO;
926 }
927
928 ahci_pci_disable_interrupts(host);
929 ata_host_suspend(host, PMSG_SUSPEND);
930 return 0;
931 }
932
ahci_pci_device_resume(struct device * dev)933 static int ahci_pci_device_resume(struct device *dev)
934 {
935 struct pci_dev *pdev = to_pci_dev(dev);
936 struct ata_host *host = pci_get_drvdata(pdev);
937 int rc;
938
939 /* Apple BIOS helpfully mangles the registers on resume */
940 if (is_mcp89_apple(pdev))
941 ahci_mcp89_apple_enable(pdev);
942
943 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
944 rc = ahci_pci_reset_controller(host);
945 if (rc)
946 return rc;
947
948 ahci_pci_init_controller(host);
949 }
950
951 ata_host_resume(host);
952
953 return 0;
954 }
955 #endif
956
957 #endif /* CONFIG_PM */
958
ahci_configure_dma_masks(struct pci_dev * pdev,struct ahci_host_priv * hpriv)959 static int ahci_configure_dma_masks(struct pci_dev *pdev,
960 struct ahci_host_priv *hpriv)
961 {
962 int dma_bits;
963 int rc;
964
965 if (hpriv->cap & HOST_CAP_64) {
966 dma_bits = 64;
967 if (hpriv->flags & AHCI_HFLAG_43BIT_ONLY)
968 dma_bits = 43;
969 } else {
970 dma_bits = 32;
971 }
972
973 /*
974 * If the device fixup already set the dma_mask to some non-standard
975 * value, don't extend it here. This happens on STA2X11, for example.
976 *
977 * XXX: manipulating the DMA mask from platform code is completely
978 * bogus, platform code should use dev->bus_dma_limit instead..
979 */
980 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
981 return 0;
982
983 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
984 if (rc)
985 dev_err(&pdev->dev, "DMA enable failed\n");
986 return rc;
987 }
988
ahci_pci_print_info(struct ata_host * host)989 static void ahci_pci_print_info(struct ata_host *host)
990 {
991 struct pci_dev *pdev = to_pci_dev(host->dev);
992 u16 cc;
993 const char *scc_s;
994
995 pci_read_config_word(pdev, 0x0a, &cc);
996 if (cc == PCI_CLASS_STORAGE_IDE)
997 scc_s = "IDE";
998 else if (cc == PCI_CLASS_STORAGE_SATA)
999 scc_s = "SATA";
1000 else if (cc == PCI_CLASS_STORAGE_RAID)
1001 scc_s = "RAID";
1002 else
1003 scc_s = "unknown";
1004
1005 ahci_print_info(host, scc_s);
1006 }
1007
1008 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
1009 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
1010 * support PMP and the 4726 either directly exports the device
1011 * attached to the first downstream port or acts as a hardware storage
1012 * controller and emulate a single ATA device (can be RAID 0/1 or some
1013 * other configuration).
1014 *
1015 * When there's no device attached to the first downstream port of the
1016 * 4726, "Config Disk" appears, which is a pseudo ATA device to
1017 * configure the 4726. However, ATA emulation of the device is very
1018 * lame. It doesn't send signature D2H Reg FIS after the initial
1019 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
1020 *
1021 * The following function works around the problem by always using
1022 * hardreset on the port and not depending on receiving signature FIS
1023 * afterward. If signature FIS isn't received soon, ATA class is
1024 * assumed without follow-up softreset.
1025 */
ahci_p5wdh_workaround(struct ata_host * host)1026 static void ahci_p5wdh_workaround(struct ata_host *host)
1027 {
1028 static const struct dmi_system_id sysids[] = {
1029 {
1030 .ident = "P5W DH Deluxe",
1031 .matches = {
1032 DMI_MATCH(DMI_SYS_VENDOR,
1033 "ASUSTEK COMPUTER INC"),
1034 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
1035 },
1036 },
1037 { }
1038 };
1039 struct pci_dev *pdev = to_pci_dev(host->dev);
1040
1041 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
1042 dmi_check_system(sysids)) {
1043 struct ata_port *ap = host->ports[1];
1044
1045 dev_info(&pdev->dev,
1046 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1047
1048 ap->ops = &ahci_p5wdh_ops;
1049 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1050 }
1051 }
1052
1053 /*
1054 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1055 * booting in BIOS compatibility mode. We restore the registers but not ID.
1056 */
ahci_mcp89_apple_enable(struct pci_dev * pdev)1057 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1058 {
1059 u32 val;
1060
1061 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1062
1063 pci_read_config_dword(pdev, 0xf8, &val);
1064 val |= 1 << 0x1b;
1065 /* the following changes the device ID, but appears not to affect function */
1066 /* val = (val & ~0xf0000000) | 0x80000000; */
1067 pci_write_config_dword(pdev, 0xf8, val);
1068
1069 pci_read_config_dword(pdev, 0x54c, &val);
1070 val |= 1 << 0xc;
1071 pci_write_config_dword(pdev, 0x54c, val);
1072
1073 pci_read_config_dword(pdev, 0x4a4, &val);
1074 val &= 0xff;
1075 val |= 0x01060100;
1076 pci_write_config_dword(pdev, 0x4a4, val);
1077
1078 pci_read_config_dword(pdev, 0x54c, &val);
1079 val &= ~(1 << 0xc);
1080 pci_write_config_dword(pdev, 0x54c, val);
1081
1082 pci_read_config_dword(pdev, 0xf8, &val);
1083 val &= ~(1 << 0x1b);
1084 pci_write_config_dword(pdev, 0xf8, val);
1085 }
1086
is_mcp89_apple(struct pci_dev * pdev)1087 static bool is_mcp89_apple(struct pci_dev *pdev)
1088 {
1089 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1090 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1091 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1092 pdev->subsystem_device == 0xcb89;
1093 }
1094
1095 /* only some SB600 ahci controllers can do 64bit DMA */
ahci_sb600_enable_64bit(struct pci_dev * pdev)1096 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1097 {
1098 static const struct dmi_system_id sysids[] = {
1099 /*
1100 * The oldest version known to be broken is 0901 and
1101 * working is 1501 which was released on 2007-10-26.
1102 * Enable 64bit DMA on 1501 and anything newer.
1103 *
1104 * Please read bko#9412 for more info.
1105 */
1106 {
1107 .ident = "ASUS M2A-VM",
1108 .matches = {
1109 DMI_MATCH(DMI_BOARD_VENDOR,
1110 "ASUSTeK Computer INC."),
1111 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1112 },
1113 .driver_data = "20071026", /* yyyymmdd */
1114 },
1115 /*
1116 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1117 * support 64bit DMA.
1118 *
1119 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1120 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1121 * This spelling mistake was fixed in BIOS version 1.5, so
1122 * 1.5 and later have the Manufacturer as
1123 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1124 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1125 *
1126 * BIOS versions earlier than 1.9 had a Board Product Name
1127 * DMI field of "MS-7376". This was changed to be
1128 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1129 * match on DMI_BOARD_NAME of "MS-7376".
1130 */
1131 {
1132 .ident = "MSI K9A2 Platinum",
1133 .matches = {
1134 DMI_MATCH(DMI_BOARD_VENDOR,
1135 "MICRO-STAR INTER"),
1136 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1137 },
1138 },
1139 /*
1140 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1141 * 64bit DMA.
1142 *
1143 * This board also had the typo mentioned above in the
1144 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1145 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1146 */
1147 {
1148 .ident = "MSI K9AGM2",
1149 .matches = {
1150 DMI_MATCH(DMI_BOARD_VENDOR,
1151 "MICRO-STAR INTER"),
1152 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1153 },
1154 },
1155 /*
1156 * All BIOS versions for the Asus M3A support 64bit DMA.
1157 * (all release versions from 0301 to 1206 were tested)
1158 */
1159 {
1160 .ident = "ASUS M3A",
1161 .matches = {
1162 DMI_MATCH(DMI_BOARD_VENDOR,
1163 "ASUSTeK Computer INC."),
1164 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1165 },
1166 },
1167 { }
1168 };
1169 const struct dmi_system_id *match;
1170 int year, month, date;
1171 char buf[9];
1172
1173 match = dmi_first_match(sysids);
1174 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1175 !match)
1176 return false;
1177
1178 if (!match->driver_data)
1179 goto enable_64bit;
1180
1181 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1182 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1183
1184 if (strcmp(buf, match->driver_data) >= 0)
1185 goto enable_64bit;
1186 else {
1187 dev_warn(&pdev->dev,
1188 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1189 match->ident);
1190 return false;
1191 }
1192
1193 enable_64bit:
1194 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1195 return true;
1196 }
1197
ahci_broken_system_poweroff(struct pci_dev * pdev)1198 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1199 {
1200 static const struct dmi_system_id broken_systems[] = {
1201 {
1202 .ident = "HP Compaq nx6310",
1203 .matches = {
1204 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1205 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1206 },
1207 /* PCI slot number of the controller */
1208 .driver_data = (void *)0x1FUL,
1209 },
1210 {
1211 .ident = "HP Compaq 6720s",
1212 .matches = {
1213 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1214 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1215 },
1216 /* PCI slot number of the controller */
1217 .driver_data = (void *)0x1FUL,
1218 },
1219
1220 { } /* terminate list */
1221 };
1222 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1223
1224 if (dmi) {
1225 unsigned long slot = (unsigned long)dmi->driver_data;
1226 /* apply the quirk only to on-board controllers */
1227 return slot == PCI_SLOT(pdev->devfn);
1228 }
1229
1230 return false;
1231 }
1232
ahci_broken_suspend(struct pci_dev * pdev)1233 static bool ahci_broken_suspend(struct pci_dev *pdev)
1234 {
1235 static const struct dmi_system_id sysids[] = {
1236 /*
1237 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1238 * to the harddisk doesn't become online after
1239 * resuming from STR. Warn and fail suspend.
1240 *
1241 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1242 *
1243 * Use dates instead of versions to match as HP is
1244 * apparently recycling both product and version
1245 * strings.
1246 *
1247 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1248 */
1249 {
1250 .ident = "dv4",
1251 .matches = {
1252 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1253 DMI_MATCH(DMI_PRODUCT_NAME,
1254 "HP Pavilion dv4 Notebook PC"),
1255 },
1256 .driver_data = "20090105", /* F.30 */
1257 },
1258 {
1259 .ident = "dv5",
1260 .matches = {
1261 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1262 DMI_MATCH(DMI_PRODUCT_NAME,
1263 "HP Pavilion dv5 Notebook PC"),
1264 },
1265 .driver_data = "20090506", /* F.16 */
1266 },
1267 {
1268 .ident = "dv6",
1269 .matches = {
1270 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1271 DMI_MATCH(DMI_PRODUCT_NAME,
1272 "HP Pavilion dv6 Notebook PC"),
1273 },
1274 .driver_data = "20090423", /* F.21 */
1275 },
1276 {
1277 .ident = "HDX18",
1278 .matches = {
1279 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1280 DMI_MATCH(DMI_PRODUCT_NAME,
1281 "HP HDX18 Notebook PC"),
1282 },
1283 .driver_data = "20090430", /* F.23 */
1284 },
1285 /*
1286 * Acer eMachines G725 has the same problem. BIOS
1287 * V1.03 is known to be broken. V3.04 is known to
1288 * work. Between, there are V1.06, V2.06 and V3.03
1289 * that we don't have much idea about. For now,
1290 * blacklist anything older than V3.04.
1291 *
1292 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1293 */
1294 {
1295 .ident = "G725",
1296 .matches = {
1297 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1298 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1299 },
1300 .driver_data = "20091216", /* V3.04 */
1301 },
1302 { } /* terminate list */
1303 };
1304 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1305 int year, month, date;
1306 char buf[9];
1307
1308 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1309 return false;
1310
1311 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1312 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1313
1314 return strcmp(buf, dmi->driver_data) < 0;
1315 }
1316
ahci_broken_lpm(struct pci_dev * pdev)1317 static bool ahci_broken_lpm(struct pci_dev *pdev)
1318 {
1319 static const struct dmi_system_id sysids[] = {
1320 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1321 {
1322 .matches = {
1323 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1324 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1325 },
1326 .driver_data = "20180406", /* 1.31 */
1327 },
1328 {
1329 .matches = {
1330 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1331 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1332 },
1333 .driver_data = "20180420", /* 1.28 */
1334 },
1335 {
1336 .matches = {
1337 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1338 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1339 },
1340 .driver_data = "20180315", /* 1.33 */
1341 },
1342 {
1343 .matches = {
1344 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1345 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1346 },
1347 /*
1348 * Note date based on release notes, 2.35 has been
1349 * reported to be good, but I've been unable to get
1350 * a hold of the reporter to get the DMI BIOS date.
1351 * TODO: fix this.
1352 */
1353 .driver_data = "20180310", /* 2.35 */
1354 },
1355 { } /* terminate list */
1356 };
1357 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1358 int year, month, date;
1359 char buf[9];
1360
1361 if (!dmi)
1362 return false;
1363
1364 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1365 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1366
1367 return strcmp(buf, dmi->driver_data) < 0;
1368 }
1369
ahci_broken_online(struct pci_dev * pdev)1370 static bool ahci_broken_online(struct pci_dev *pdev)
1371 {
1372 #define ENCODE_BUSDEVFN(bus, slot, func) \
1373 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1374 static const struct dmi_system_id sysids[] = {
1375 /*
1376 * There are several gigabyte boards which use
1377 * SIMG5723s configured as hardware RAID. Certain
1378 * 5723 firmware revisions shipped there keep the link
1379 * online but fail to answer properly to SRST or
1380 * IDENTIFY when no device is attached downstream
1381 * causing libata to retry quite a few times leading
1382 * to excessive detection delay.
1383 *
1384 * As these firmwares respond to the second reset try
1385 * with invalid device signature, considering unknown
1386 * sig as offline works around the problem acceptably.
1387 */
1388 {
1389 .ident = "EP45-DQ6",
1390 .matches = {
1391 DMI_MATCH(DMI_BOARD_VENDOR,
1392 "Gigabyte Technology Co., Ltd."),
1393 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1394 },
1395 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1396 },
1397 {
1398 .ident = "EP45-DS5",
1399 .matches = {
1400 DMI_MATCH(DMI_BOARD_VENDOR,
1401 "Gigabyte Technology Co., Ltd."),
1402 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1403 },
1404 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1405 },
1406 { } /* terminate list */
1407 };
1408 #undef ENCODE_BUSDEVFN
1409 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1410 unsigned int val;
1411
1412 if (!dmi)
1413 return false;
1414
1415 val = (unsigned long)dmi->driver_data;
1416
1417 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1418 }
1419
ahci_broken_devslp(struct pci_dev * pdev)1420 static bool ahci_broken_devslp(struct pci_dev *pdev)
1421 {
1422 /* device with broken DEVSLP but still showing SDS capability */
1423 static const struct pci_device_id ids[] = {
1424 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1425 {}
1426 };
1427
1428 return pci_match_id(ids, pdev);
1429 }
1430
1431 #ifdef CONFIG_ATA_ACPI
ahci_gtf_filter_workaround(struct ata_host * host)1432 static void ahci_gtf_filter_workaround(struct ata_host *host)
1433 {
1434 static const struct dmi_system_id sysids[] = {
1435 /*
1436 * Aspire 3810T issues a bunch of SATA enable commands
1437 * via _GTF including an invalid one and one which is
1438 * rejected by the device. Among the successful ones
1439 * is FPDMA non-zero offset enable which when enabled
1440 * only on the drive side leads to NCQ command
1441 * failures. Filter it out.
1442 */
1443 {
1444 .ident = "Aspire 3810T",
1445 .matches = {
1446 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1447 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1448 },
1449 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1450 },
1451 { }
1452 };
1453 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1454 unsigned int filter;
1455 int i;
1456
1457 if (!dmi)
1458 return;
1459
1460 filter = (unsigned long)dmi->driver_data;
1461 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1462 filter, dmi->ident);
1463
1464 for (i = 0; i < host->n_ports; i++) {
1465 struct ata_port *ap = host->ports[i];
1466 struct ata_link *link;
1467 struct ata_device *dev;
1468
1469 ata_for_each_link(link, ap, EDGE)
1470 ata_for_each_dev(dev, link, ALL)
1471 dev->gtf_filter |= filter;
1472 }
1473 }
1474 #else
ahci_gtf_filter_workaround(struct ata_host * host)1475 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1476 {}
1477 #endif
1478
1479 /*
1480 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1481 * as DUMMY, or detected but eventually get a "link down" and never get up
1482 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1483 * port_map may hold a value of 0x00.
1484 *
1485 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1486 * and can significantly reduce the occurrence of the problem.
1487 *
1488 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1489 */
acer_sa5_271_workaround(struct ahci_host_priv * hpriv,struct pci_dev * pdev)1490 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1491 struct pci_dev *pdev)
1492 {
1493 static const struct dmi_system_id sysids[] = {
1494 {
1495 .ident = "Acer Switch Alpha 12",
1496 .matches = {
1497 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1498 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1499 },
1500 },
1501 { }
1502 };
1503
1504 if (dmi_check_system(sysids)) {
1505 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1506 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1507 hpriv->port_map = 0x7;
1508 hpriv->cap = 0xC734FF02;
1509 }
1510 }
1511 }
1512
1513 #ifdef CONFIG_ARM64
1514 /*
1515 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1516 * Workaround is to make sure all pending IRQs are served before leaving
1517 * handler.
1518 */
ahci_thunderx_irq_handler(int irq,void * dev_instance)1519 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1520 {
1521 struct ata_host *host = dev_instance;
1522 struct ahci_host_priv *hpriv;
1523 unsigned int rc = 0;
1524 void __iomem *mmio;
1525 u32 irq_stat, irq_masked;
1526 unsigned int handled = 1;
1527
1528 hpriv = host->private_data;
1529 mmio = hpriv->mmio;
1530 irq_stat = readl(mmio + HOST_IRQ_STAT);
1531 if (!irq_stat)
1532 return IRQ_NONE;
1533
1534 do {
1535 irq_masked = irq_stat & hpriv->port_map;
1536 spin_lock(&host->lock);
1537 rc = ahci_handle_port_intr(host, irq_masked);
1538 if (!rc)
1539 handled = 0;
1540 writel(irq_stat, mmio + HOST_IRQ_STAT);
1541 irq_stat = readl(mmio + HOST_IRQ_STAT);
1542 spin_unlock(&host->lock);
1543 } while (irq_stat);
1544
1545 return IRQ_RETVAL(handled);
1546 }
1547 #endif
1548
ahci_remap_check(struct pci_dev * pdev,int bar,struct ahci_host_priv * hpriv)1549 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1550 struct ahci_host_priv *hpriv)
1551 {
1552 int i;
1553 u32 cap;
1554
1555 /*
1556 * Check if this device might have remapped nvme devices.
1557 */
1558 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1559 pci_resource_len(pdev, bar) < SZ_512K ||
1560 bar != AHCI_PCI_BAR_STANDARD ||
1561 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1562 return;
1563
1564 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1565 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1566 if ((cap & (1 << i)) == 0)
1567 continue;
1568 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1569 != PCI_CLASS_STORAGE_EXPRESS)
1570 continue;
1571
1572 /* We've found a remapped device */
1573 hpriv->remapped_nvme++;
1574 }
1575
1576 if (!hpriv->remapped_nvme)
1577 return;
1578
1579 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
1580 hpriv->remapped_nvme);
1581 dev_warn(&pdev->dev,
1582 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1583
1584 /*
1585 * Don't rely on the msi-x capability in the remap case,
1586 * share the legacy interrupt across ahci and remapped devices.
1587 */
1588 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1589 }
1590
ahci_get_irq_vector(struct ata_host * host,int port)1591 static int ahci_get_irq_vector(struct ata_host *host, int port)
1592 {
1593 return pci_irq_vector(to_pci_dev(host->dev), port);
1594 }
1595
ahci_init_msi(struct pci_dev * pdev,unsigned int n_ports,struct ahci_host_priv * hpriv)1596 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1597 struct ahci_host_priv *hpriv)
1598 {
1599 int nvec;
1600
1601 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1602 return -ENODEV;
1603
1604 /*
1605 * If number of MSIs is less than number of ports then Sharing Last
1606 * Message mode could be enforced. In this case assume that advantage
1607 * of multipe MSIs is negated and use single MSI mode instead.
1608 */
1609 if (n_ports > 1) {
1610 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1611 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1612 if (nvec > 0) {
1613 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1614 hpriv->get_irq_vector = ahci_get_irq_vector;
1615 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1616 return nvec;
1617 }
1618
1619 /*
1620 * Fallback to single MSI mode if the controller
1621 * enforced MRSM mode.
1622 */
1623 printk(KERN_INFO
1624 "ahci: MRSM is on, fallback to single MSI\n");
1625 pci_free_irq_vectors(pdev);
1626 }
1627 }
1628
1629 /*
1630 * If the host is not capable of supporting per-port vectors, fall
1631 * back to single MSI before finally attempting single MSI-X.
1632 */
1633 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1634 if (nvec == 1)
1635 return nvec;
1636 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1637 }
1638
ahci_update_initial_lpm_policy(struct ata_port * ap,struct ahci_host_priv * hpriv)1639 static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1640 struct ahci_host_priv *hpriv)
1641 {
1642 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1643
1644
1645 /* Ignore processing for chipsets that don't use policy */
1646 if (!(hpriv->flags & AHCI_HFLAG_USE_LPM_POLICY))
1647 return;
1648
1649 /* user modified policy via module param */
1650 if (mobile_lpm_policy != -1) {
1651 policy = mobile_lpm_policy;
1652 goto update_policy;
1653 }
1654
1655 if (policy > ATA_LPM_MED_POWER && pm_suspend_default_s2idle()) {
1656 if (hpriv->cap & HOST_CAP_PART)
1657 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1658 else if (hpriv->cap & HOST_CAP_SSC)
1659 policy = ATA_LPM_MIN_POWER;
1660 }
1661
1662 update_policy:
1663 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1664 ap->target_lpm_policy = policy;
1665 }
1666
ahci_intel_pcs_quirk(struct pci_dev * pdev,struct ahci_host_priv * hpriv)1667 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1668 {
1669 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1670 u16 tmp16;
1671
1672 /*
1673 * Only apply the 6-port PCS quirk for known legacy platforms.
1674 */
1675 if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1676 return;
1677
1678 /* Skip applying the quirk on Denverton and beyond */
1679 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
1680 return;
1681
1682 /*
1683 * port_map is determined from PORTS_IMPL PCI register which is
1684 * implemented as write or write-once register. If the register
1685 * isn't programmed, ahci automatically generates it from number
1686 * of ports, which is good enough for PCS programming. It is
1687 * otherwise expected that platform firmware enables the ports
1688 * before the OS boots.
1689 */
1690 pci_read_config_word(pdev, PCS_6, &tmp16);
1691 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1692 tmp16 |= hpriv->port_map;
1693 pci_write_config_word(pdev, PCS_6, tmp16);
1694 }
1695 }
1696
remapped_nvme_show(struct device * dev,struct device_attribute * attr,char * buf)1697 static ssize_t remapped_nvme_show(struct device *dev,
1698 struct device_attribute *attr,
1699 char *buf)
1700 {
1701 struct ata_host *host = dev_get_drvdata(dev);
1702 struct ahci_host_priv *hpriv = host->private_data;
1703
1704 return sysfs_emit(buf, "%u\n", hpriv->remapped_nvme);
1705 }
1706
1707 static DEVICE_ATTR_RO(remapped_nvme);
1708
ahci_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)1709 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1710 {
1711 unsigned int board_id = ent->driver_data;
1712 struct ata_port_info pi = ahci_port_info[board_id];
1713 const struct ata_port_info *ppi[] = { &pi, NULL };
1714 struct device *dev = &pdev->dev;
1715 struct ahci_host_priv *hpriv;
1716 struct ata_host *host;
1717 int n_ports, i, rc;
1718 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1719
1720 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1721
1722 ata_print_version_once(&pdev->dev, DRV_VERSION);
1723
1724 /* The AHCI driver can only drive the SATA ports, the PATA driver
1725 can drive them all so if both drivers are selected make sure
1726 AHCI stays out of the way */
1727 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1728 return -ENODEV;
1729
1730 /* Apple BIOS on MCP89 prevents us using AHCI */
1731 if (is_mcp89_apple(pdev))
1732 ahci_mcp89_apple_enable(pdev);
1733
1734 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1735 * At the moment, we can only use the AHCI mode. Let the users know
1736 * that for SAS drives they're out of luck.
1737 */
1738 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1739 dev_info(&pdev->dev,
1740 "PDC42819 can only drive SATA devices with this driver\n");
1741
1742 /* Some devices use non-standard BARs */
1743 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1744 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1745 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1746 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1747 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1748 if (pdev->device == 0xa01c)
1749 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1750 if (pdev->device == 0xa084)
1751 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1752 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
1753 if (pdev->device == 0x7a08)
1754 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
1755 }
1756
1757 /* acquire resources */
1758 rc = pcim_enable_device(pdev);
1759 if (rc)
1760 return rc;
1761
1762 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1763 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1764 u8 map;
1765
1766 /* ICH6s share the same PCI ID for both piix and ahci
1767 * modes. Enabling ahci mode while MAP indicates
1768 * combined mode is a bad idea. Yield to ata_piix.
1769 */
1770 pci_read_config_byte(pdev, ICH_MAP, &map);
1771 if (map & 0x3) {
1772 dev_info(&pdev->dev,
1773 "controller is in combined mode, can't enable AHCI mode\n");
1774 return -ENODEV;
1775 }
1776 }
1777
1778 /* AHCI controllers often implement SFF compatible interface.
1779 * Grab all PCI BARs just in case.
1780 */
1781 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1782 if (rc == -EBUSY)
1783 pcim_pin_device(pdev);
1784 if (rc)
1785 return rc;
1786
1787 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1788 if (!hpriv)
1789 return -ENOMEM;
1790 hpriv->flags |= (unsigned long)pi.private_data;
1791
1792 /* MCP65 revision A1 and A2 can't do MSI */
1793 if (board_id == board_ahci_mcp65 &&
1794 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1795 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1796
1797 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1798 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1799 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1800
1801 /* only some SB600s can do 64bit DMA */
1802 if (ahci_sb600_enable_64bit(pdev))
1803 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1804
1805 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1806
1807 /* detect remapped nvme devices */
1808 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1809
1810 sysfs_add_file_to_group(&pdev->dev.kobj,
1811 &dev_attr_remapped_nvme.attr,
1812 NULL);
1813
1814 /* must set flag prior to save config in order to take effect */
1815 if (ahci_broken_devslp(pdev))
1816 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1817
1818 #ifdef CONFIG_ARM64
1819 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
1820 pdev->device == 0xa235 &&
1821 pdev->revision < 0x30)
1822 hpriv->flags |= AHCI_HFLAG_NO_SXS;
1823
1824 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1825 hpriv->irq_handler = ahci_thunderx_irq_handler;
1826 #endif
1827
1828 /* save initial config */
1829 ahci_pci_save_initial_config(pdev, hpriv);
1830
1831 /* prepare host */
1832 if (hpriv->cap & HOST_CAP_NCQ) {
1833 pi.flags |= ATA_FLAG_NCQ;
1834 /*
1835 * Auto-activate optimization is supposed to be
1836 * supported on all AHCI controllers indicating NCQ
1837 * capability, but it seems to be broken on some
1838 * chipsets including NVIDIAs.
1839 */
1840 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1841 pi.flags |= ATA_FLAG_FPDMA_AA;
1842
1843 /*
1844 * All AHCI controllers should be forward-compatible
1845 * with the new auxiliary field. This code should be
1846 * conditionalized if any buggy AHCI controllers are
1847 * encountered.
1848 */
1849 pi.flags |= ATA_FLAG_FPDMA_AUX;
1850 }
1851
1852 if (hpriv->cap & HOST_CAP_PMP)
1853 pi.flags |= ATA_FLAG_PMP;
1854
1855 ahci_set_em_messages(hpriv, &pi);
1856
1857 if (ahci_broken_system_poweroff(pdev)) {
1858 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1859 dev_info(&pdev->dev,
1860 "quirky BIOS, skipping spindown on poweroff\n");
1861 }
1862
1863 if (ahci_broken_lpm(pdev)) {
1864 pi.flags |= ATA_FLAG_NO_LPM;
1865 dev_warn(&pdev->dev,
1866 "BIOS update required for Link Power Management support\n");
1867 }
1868
1869 if (ahci_broken_suspend(pdev)) {
1870 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1871 dev_warn(&pdev->dev,
1872 "BIOS update required for suspend/resume\n");
1873 }
1874
1875 if (ahci_broken_online(pdev)) {
1876 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1877 dev_info(&pdev->dev,
1878 "online status unreliable, applying workaround\n");
1879 }
1880
1881
1882 /* Acer SA5-271 workaround modifies private_data */
1883 acer_sa5_271_workaround(hpriv, pdev);
1884
1885 /* CAP.NP sometimes indicate the index of the last enabled
1886 * port, at other times, that of the last possible port, so
1887 * determining the maximum port number requires looking at
1888 * both CAP.NP and port_map.
1889 */
1890 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1891
1892 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1893 if (!host)
1894 return -ENOMEM;
1895 host->private_data = hpriv;
1896
1897 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1898 /* legacy intx interrupts */
1899 pci_intx(pdev, 1);
1900 }
1901 hpriv->irq = pci_irq_vector(pdev, 0);
1902
1903 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1904 host->flags |= ATA_HOST_PARALLEL_SCAN;
1905 else
1906 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1907
1908 if (!(hpriv->cap & HOST_CAP_PART))
1909 host->flags |= ATA_HOST_NO_PART;
1910
1911 if (!(hpriv->cap & HOST_CAP_SSC))
1912 host->flags |= ATA_HOST_NO_SSC;
1913
1914 if (!(hpriv->cap2 & HOST_CAP2_SDS))
1915 host->flags |= ATA_HOST_NO_DEVSLP;
1916
1917 if (pi.flags & ATA_FLAG_EM)
1918 ahci_reset_em(host);
1919
1920 for (i = 0; i < host->n_ports; i++) {
1921 struct ata_port *ap = host->ports[i];
1922
1923 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1924 ata_port_pbar_desc(ap, ahci_pci_bar,
1925 0x100 + ap->port_no * 0x80, "port");
1926
1927 /* set enclosure management message type */
1928 if (ap->flags & ATA_FLAG_EM)
1929 ap->em_message_type = hpriv->em_msg_type;
1930
1931 ahci_update_initial_lpm_policy(ap, hpriv);
1932
1933 /* disabled/not-implemented port */
1934 if (!(hpriv->port_map & (1 << i)))
1935 ap->ops = &ata_dummy_port_ops;
1936 }
1937
1938 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1939 ahci_p5wdh_workaround(host);
1940
1941 /* apply gtf filter quirk */
1942 ahci_gtf_filter_workaround(host);
1943
1944 /* initialize adapter */
1945 rc = ahci_configure_dma_masks(pdev, hpriv);
1946 if (rc)
1947 return rc;
1948
1949 rc = ahci_pci_reset_controller(host);
1950 if (rc)
1951 return rc;
1952
1953 ahci_pci_init_controller(host);
1954 ahci_pci_print_info(host);
1955
1956 pci_set_master(pdev);
1957
1958 rc = ahci_host_activate(host, &ahci_sht);
1959 if (rc)
1960 return rc;
1961
1962 pm_runtime_put_noidle(&pdev->dev);
1963 return 0;
1964 }
1965
ahci_shutdown_one(struct pci_dev * pdev)1966 static void ahci_shutdown_one(struct pci_dev *pdev)
1967 {
1968 ata_pci_shutdown_one(pdev);
1969 }
1970
ahci_remove_one(struct pci_dev * pdev)1971 static void ahci_remove_one(struct pci_dev *pdev)
1972 {
1973 sysfs_remove_file_from_group(&pdev->dev.kobj,
1974 &dev_attr_remapped_nvme.attr,
1975 NULL);
1976 pm_runtime_get_noresume(&pdev->dev);
1977 ata_pci_remove_one(pdev);
1978 }
1979
1980 module_pci_driver(ahci_pci_driver);
1981
1982 MODULE_AUTHOR("Jeff Garzik");
1983 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1984 MODULE_LICENSE("GPL");
1985 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1986 MODULE_VERSION(DRV_VERSION);
1987